To bridge the gap between the physical and digital worlds, any type of product would need to integrate networked electronic components and systems, built on micro/nanotechnologies, in what has been called "Internet of Things" (IoT). To fulfill the IoT vision, many technology enablers are required, with trusted (i.e., reliable and secure) as well as low-power ICs and components, among others, playing a pivotal role. All these enablers must be properly handled with a multidomain approach -covering device, circuit and architectural levels- in a context where technology scaling has slowed down. Thus, at technology level, innovations in materials and device structures will be required and, next to this, low-power robust circuits and alternative architectures will have to be implemented. Consequently, the experience of researchers with complementary expertise must be properly combined under a collaborative framework. Following these guidelines, device reliability engineers (UAB) and analog and digital circuit designers (IMSE and UPC) will work together in this project on the design of low-power, variability-resilient nanoelectronic circuits and systems, by using a multilevel approach and taking into account IoT challenges.
To achieve this general objective, several lines of work will be followed. Since circuit and system design for IoT relies upon a deep knowledge of phenomena at device level, a detailed statistical and multiscale characterization of the variability in advanced CMOS devices will be done in all regimes of operation, for the development of variability-aware compact models. Emerging devices (i.e., memristors and graphene-based devices) will be also considered to evaluate their suitability as building components in alternative circuits and architectures. At circuit and system levels, low-power and variability-resilient design strategies and methodologies will be developed. Variability will be tackled from two perspectives: palliation and exploitation. From a palliative perspective, adequate design methodologies will be created, able to consider and reduce variability across many hierarchical levels in a complex AMS/RF system. Also, the use of Body Bias modulation for variability mitigation in RF and digital circuits in FDSOI technologies will be analyzed. From the exploitation perspective, unreliability aspects in CMOS and memristive devices will be explored for the implementation of cryptographic primitives. Energy-efficient hierarchical design methodologies will be implemented to reduce power consumption in AMS/RF circuits and ultra-low voltage AMS/RF and digital circuits will be designed. Non-conventional strategies for computing systems and non-von Neumann computing architectures will be studied too. Finally, the adoption of emerging technologies for alternative computing architectures (combining memristors and FETs) as well as neuromorphic architectures will be addressed. The innovations in devices, design techniques, extremely low-power and reliable circuits and architectures will enable competitive advantages in numerous IoT applications and markets, supporting the relevance of the proposed research from the societal, industrial and economical points of view. This fact, together with the experience of the proposing partners, foresees publications and technology transfer of the results.