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Author: Vornicu, Ion
Year: Since 2002
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Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology
I. Vornicu, F. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - European Solid-State Device Research Conference ESSDERC 2019
[abstract]
Photon detection at longer wavelengths is much desired for LiDAR applications. Silicon photodiodes with deeper junctions and larger multiplication regions are more sensitive to near-IR photons. This paper presents the complete electro-optical characterization of a P-well/Deep N-well single photon avalanche diode integrated in 110nm CIS technology. Devices with various sizes, shapes and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is of 18V. The proposed structure has 0.4Hz/um2 dark count rate, 0.5% afterpulsing, 188ps FWHM (total) jitter and around 10% photon detection probability at 850nm wavelength. All figures have been measured at 3V excess voltage.

Evaluation of Architectures for FPGA-Implementation of High-Resolution TDCs
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2019
[abstract]
Time-to-digital converters (TDCs) are a central component in systems based on time-delay assessment. The principal characteristics to be sought for in a TDC are high resolution, long time range, linearity and low power consumption. Besides, field-programmable gate arrays (FPGAs) represent an interesting option to explore fully-digital TDC architectures, because of their flexibility, shorter development time and lower implementation cost than ASICs. They are reconfigurable and usually built on the finest silicon technologies. The purpose of this work is to identify the different architectures that lead to high-resolution TDCs on FPGA, and to compare them in terms of the appropriate figures of merit. The most extended method to cover a long time interval while preserving a high time resolution is to combine a coarse counter with a fine time interpolator. Two techniques have been widely used to implement the interpolator, namely a tapped delay line (TDL) and a multiple-phase clock interpolator. Exploiting fast carry chains present in most modern FPGAs, sub-clock-period resolution have been achieved, down to tens of picoseconds. Other important aspects of the TDC design are the thermometer-to-binary encoder, the minimization of the clock skew, the analysis of the influence of voltage and temperature changes and bin-width calibration. Accordingly, we report an analysis of the different TDC architectures on FPGA based on their performance characteristics.

TOF estimation based on compressed real-time histogram builder for SPAD image sensors
I. Vornicu, A. Darie, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
[abstract]
This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation algorithms rely on complete ToF histograms. The next generation of high speed dToF-CIS is expected to have wide dynamic range and high depth resolution. Applications such as 3D imaging based on dToF-CISs require pixel-level ToF histograms which have to be stored by huge fully-random access memory (RAM) modules. The proposed shifted inter-frame histogram (SiFH) algorithm has the same accuracy but requires a memory footprint 128 times smaller than the conventional algorithm. Thus a much larger number of pixels can be resolved using limited block RAM resources of FPGAs. Moreover the overall frame rate is also remarkably improved compared to the scanning method. The proof of concept of the SiFH algorithm on 15 bits has been implemented on Spartan-3E. An automated testbench was developed to confirm that no ambiguity errors occur along the entire dynamic range.

Compact Real-Time Inter-Frame Histogram Builder for 15Bits High-Speed ToF-Imagers based on Single-Photon Detection
I. Vornicu, A. Darie, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper - IEEE Sensors Journal, vol. 19, no. 6, pp 2181-2190, 2019
IEEE    DOI: 10.1109/JSEN.2018.2885960    ISSN: 1530-437X    » doi
[abstract]
Time-of-flight image sensors based on single-photon detection, i.e. SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for ToF computation. This method makes use of the shifted inter-frame histogram (SifH). It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 28 words memory is enough to process histograms containing up to 215 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.

An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation
J.M. López-Martínez, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2018
[abstract]
Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new approach to model them in Verilog-A HDL with the help of a powerful tool: TCAD simulation. Besides, to the best of our knowledge, this is first model to incorporate a trap-assisted tunneling mechanism, a cross-section temperature dependence of the traps, and the self-heating effect. Comparison with experimental data establishes the validity of the model.

CMOS-SPAD camera prototype for single-sensor 2D/3D imaging
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018
[abstract]
One of the research lines explored in project 'iCaveats' has been the combined capture of 2D and 3D visual information. With the objective of power-efficient feature learning/extraction, combined 2D/3D imaging is a useful tool to work on a lightweight but rich description of the scene. Single-sensor capture of both modalities is a potential improvement in cost and efficiency. In this demo, we present the performance and features of a CMOS-SPAD camera prototype that realizes photon counting and direct time-of-flight (d-ToF). The central elements of the camera module are a 64x64 SPAD imager and a FPGA board for real time histograming and image reconstruction at 1kfps.

Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-todigital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper we are covering the modeling, design and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64×64-pixel array. It has been fabricated in a 0.18μm standard CMOS technology. Occupation area is 28×29μm2 and power consumption is 1.17mW at 850MHz. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of -102dBc/Hz at 2MHz offset frequency from 850MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147ps with a RMS DNL/ INL of 0.13/ 1.7LSB.

CMOS Vision Sensors: Embedding Computer Vision at Imaging Front-Ends
A. Rodríguez-Vázquez, J. Fernández-Berni, J.A. Leñero-Bardallo, I. Vornicu and R. Carmona-Galán
Journal Paper - IEEE Circuits and Systems Magazine, vol. 18, no. 2, pp 90-107, 2018
IEEE    DOI: 10.1109/MCAS.2018.2821772    ISSN: 1531-636X    » doi
[abstract]
CMOS Image Sensors (CIS) are key for imaging technologies. These chips are conceived for capturing optical scenes focused on their surface, and for delivering electrical images, commonly in digital format. CISs may incorporate intelligence; however, their smartness basically concerns calibration, error correction and other similar tasks. The term CVISs (CMOS VIsion Sensors) defines other class of sensor front-ends which are aimed at performing vision tasks right at the focal plane. They have been running under names such as computational image sensors, vision sensors and silicon retinas, among others. CVIS and CISs are similar regarding physical implementation. However, while inputs of both CIS and CVIS are images captured by photo-sensors placed at the focal-plane, CVISs primary outputs may not be images but either image features or even decisions based on the spatial-temporal analysis of the scenes. We may hence state that CVISs are more ‘intelligent’ than CISs as they focus on information instead of on raw data. Actually, CVIS architectures capable of extracting and interpreting the information contained in images, and prompting reaction commands thereof, have been explored for years in academia, and industrial applications are recently ramping up. One of the challenges of CVISs architects is incorporating computer vision concepts into the design flow. The endeavor is ambitious because imaging and computer vision communities are rather disjoint groups talking different languages. The Cellular Nonlinear Network Universal Machine (CNNUM) paradigm, proposed by Profs. Chua and Roska, defined an adequate framework for such conciliation as it is particularly well suited for hardware-software co-design. This paper overviews CVISs chips that were conceived and prototyped at IMS E Vision Lab over the past twenty years. Some of them fit the CNNUM paradigm while others are tangential to it. All of them employ per-pixel mixed-signal processing circuitry to achieve sensor-processing concurrency in the quest of fast operation with reduced energy budget.

Real-Time Inter-Frame Histogram Builder for SPAD Image Sensors
I. Vornicu, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper - IEEE Sensors Journal, vol. 18, no. 4, pp 1576-1584, 2018
IEEE    DOI: 10.1109/JSEN.2017.2784484    ISSN: 1530-437X    » doi
[abstract]
CMOS image sensors based on single-photon avalanche-diodes (SPAD) are suitable for 2D and 3D vision. Limited by uncorrelated noise and/or low illumination conditions, image capturing becomes nearly impossible in a single-shot exposure time. Moreover the depth accuracy is affected by jitter. Therefore, many frames need to be taken to reconstruct the final accurate image. The proposed reconstruction algorithm is based on pixel-wise histogram building. Specifically, a histogram is built on the fly for each pixel of the array from the ongoing acquired frames. This paper presents the design and implementation on FPGA of a real-time pixel-wise inter-frame histogram builder at 1kfps. The design has been proven with a 64×64-pixels SPAD camera. Its remarkable robustness has been demonstrated in harsh conditions such as 42 kHz of dark count rate (DCR) and high background illumination up to 20 times larger than the DCR. The system has a graphic user interface for 2D/3D imager configuration, image streaming and pixel-wise histogram streaming.

Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
I. Vornicu, R. Carmona-Galan and Rodriguez-Vazquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 11, pp 2821-2834, 2017
IEEE    DOI: 10.1109/TCSI.2017.2706324    ISSN: 1549-8328    » doi
[abstract]
Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper, we are covering the modeling, design, and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64x64-pixel array. It has been fabricated in a 0.18 mu m standard CMOS technology. Occupation area is 28x29 mu m(2) and power consumption is 1.17 mW at 850 MHz. The measured gain of the VCRO is of 477 MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely, from 400 to 850 MHz. The phase noise is of -102 dBc/Hz at 2 MHz offset frequency from 850 MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147 ps with a rms DNL/INL of 0.13/1.7LSB.

Design of a Compact and Low-Power TDC for an Array of SiPM´s in 110nm CIS Technology
F.N. Bandi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Conference on Ph.D Research in Microelectronics and Electronics PRIME 2017
[abstract]
Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their -to name a few interesting Properties- compactness, lower bias voltage, tolerance to magnetic fields and finer spatial resolution. SiPMs can also be built in CMOS technology. This allows the incorporation of active quenching and recharge schemes at cell level and processing circuitry at pixel level. One of the elements that can lead to finer temporal resolutions is the time-to-digital converter (TDC). In this paper we describe the architecture of a compact TDC to be included at each pixel of an array of SiPMs. It is compact and consumes low power. It is based on a voltage controlled oscillator that generates multiple internal phases that are interpolated to provide time resolution below the time delay of a single gate. Simulation results of a 11b TDC based on a 4-stage VCRO in 110nm CIS technology yield a time resolution of 80.0ps, a DNL of ±0.28 LSB, a INL ±0.52 LSB, and a power consumption of 850μW.

SPAD-Sensor Camera Prototype for 2D/3D Imaging
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2017
[abstract]
This demo presents a camera prototype based on a SPAD (single-photon avalanche diode) image sensor for 2D/3D scene reconstruction. SPADs are intrinsically binary devices that fire at the detection of a single photon entering the capture volume. They can be employed in photon counting mode, which provides a pixel output that is proportional to the brightness of the corresponding object in the scene. They can be employed also in combination with a time-to-digital converter (TDC), in order to provide a timestamp from which the time-of-flight (ToF) of the light reflected by the objects can be inferred, and thus their distance to the objective. In the first case, illumination does not have a structure. In the second case, a pulsed laser with picosecond jitter is required to ensure the appropriate accuracy in the estimation of the distances. The prototype camera presented here employs a 64×64 SPAD array with active quenching and recharge and in-pixel TDC, allowing high frame rate acquisition. Highly efficient circuit design techniques are employed to ensure image capturing under a high level of uncorrelated noise such as dark count and background illumination. It has a depth resolution of 1cm at 6-0.1nW/mm2 illumination power.

VCRO-based TDCs in submicron CIS technology
F.N. Bandi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2017
[abstract]
Time-to-Digital Converters (TDCs) based on Voltage Controlled Ring Oscillators (VCROs) provides a good trade off between area occupation, time resolution and power consumption. These specifications are determined by applications like nuclear medicine and high energy physics imaging, in which an accurate timestamp of the detected photons is needed and small area footprint to maximize fill factor is desired. This is specially true when the number of incident photons is low and oversampling is impossible. Other TDC architectures like pulse stretching, Vernier delay lines, time amplification or multi-path gated ring oscillator are able to provide finer time resolution at the price of higher area occupation and power consumption. If in sensor intregation is desired, these area and power increments are prohibitive. VCROs provides a large number of alternatives during the design phase, each one with their advantages and disadvantages. The first step is the selection of the stage topology, that is, single-ended, differential and pseudo-differential. In this application, pseudo-differential stages outperforms the other alternatives in terms of lower power consumption, lower jitter and better noise rejection. The second step consist in the selection of a pseudo-differential stage using a common metric. To this end, the two most used pseudo-differential stages were compared in terms of time resolution, by using the small signal model and the GBW product. Analytical expression points out that pseudo-differential stage with cross-coupled inverters have finer time resolution than pseudo-differential stage with cross-coupled PMOS. Pre-layout simulations support the analytical expression and shows a clear difference between the time resolution of each stage.

Live Demonstration: Photon Counting and Direct ToF Camera Prototype Based on CMOS SPADs
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
This demonstrator reveals the performance and features of a single photon avalanche diode (SPAD) camera prototype. It is aimed to 2D/3D vision by photon counting and direct time-of-flight (d-ToF), respectively. The imager is built on a standard CMOS technology without any opto flavor or high voltage option. The camera module consists of a 64×64 SPAD imager and a FPGA board for real time image reconstruction at 1kfps.

Photon Counting and Direct ToF Camera Prototype based on CMOS SPADs
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
This paper presents a camera prototype for 2D/3D image capture in low illumination conditions based on single-photon avalanche-diode (SPAD) image sensor for direct time-of-flight (d-ToF). The imager is a 64×64 array with in-pixel TDC for high frame rate acquisition. Circuit design techniques are combined to ensure successful 3D image capturing under low sensitivity conditions and high level of uncorrelated noise such as dark count and background illumination. Among them an innovative time gated front-end for the SPAD detector, a reverse start-stop scheme and real-time image reconstruction at 1kfps are incorporated by the imager. To the best of our knowledge, this is the first ToF camera based on a SPAD sensor fabricated and proved for 3D image reconstruction in a standard CMOS process without any opto-flavor or high voltage option. It has a depth resolution of 1cm at an illumination power from less than 6nW/mm2 down to 0.1nW/mm2.

Compensation of PVT Variations in ToF Imagers with In-Pixel TDC
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - Sensors, vol. 17, no. 5, art. 1072, 2017
MDPI    DOI: 10.3390/s17051072    ISSN: 1424-8220    » doi
[abstract]
The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must contemplate system-level aspects that affect its overall performance. This paper provides a detailed analysis of the impact of process parameters, voltage supply, and temperature (PVT) variations on the time bin of the TDC array. Moreover, the design and characterization of a global compensation loop is presented. It is based on a phase locked loop (PLL) that is integrated on-chip. The main building block of the PLL is a voltage-controlled ring-oscillator (VCRO) that is identical to the ones employed for the in-pixel TDCs. The reference voltage that drives the master VCRO is distributed to the voltage control inputs of the slave VCROs such that their multiphase outputs become invariant to PVT changes. These outputs act as time interpolators for the TDCs. Therefore the compensation scheme prevents the time bin of the TDCs from drifting over time due to the aforementioned factors. Moreover, the same scheme is used to program different time resolutions of the direct time-of-flight (ToF) imager aimed at 3D ranging or depth map imaging. Experimental results that validate the analysis are provided as well. The compensation loop proves to be remarkably effective. The spreading of the TDCs time bin is lowered from: (i) 20% down to 2.4% while the temperature ranges from 0 °C to 100 °C; (ii) 27% down to 0.27%, when the voltage supply changes within ±10% of the nominal value; (iii) 5.2 ps to 2 ps standard deviation over 30 sample chips, due to process parameters´ variation.

A CMOS Digital SiPM with Focal-Plane Light-Spot Statistics for DOI Computation
I. Vornicu, F.N. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, vol. 17, no. 3, pp 632-643, 2017
IEEE    DOI: 10.1109/JSEN.2016.2632200    ISSN: 1530-437X     » doi
[abstract]
Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This paper contemplates the computation of DOI based on the standard deviation of the light distribution. The simulations have been carried out by GAMOS. The design of the proposed digital silicon photomultiplier (d-SiPM) with focal plane detection of the center of mass position and dispersion of the scintillation light is presented. The d-SiPM shares the same off-chip time-to-digital converter such that each pixel can be individually connected to it. A miniature d-SiPM 8×8 single-photon avalanche-diode (SPAD) array has been fabricated as a proof of concept. The SPADs along each row and column are connected through an OR combination technique. It has 256×256μm2 without peripherals circuits and pads. The fill factor is about 11%. The average dark count rate of the mini d-SiPM is of 240 kHz. The average photon detection efficiency is 5% at 480 nm wavelength, room temperature, and 0.9 V excess voltage. The dynamic range is of 96 dB. The sensor array features a time resolution of 212 ps. The photon-timing SNR is 81 dB. The focal plane statistics of the light-spot has been proved as well by measurements.

In-Pixel Voltage-Controlled Ring-Oscillator for Phase Interpolation in ToF Image Sensors
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems, ISCAS 2016
[abstract]
The design and measurements of a CMOS pseudo-differential voltage-controlled ring-oscillator (VCRO) are presented. It is aimed to act as time interpolator for arrayable picosecond time-to-digital convertors (TDC). This design is incorporated into a 64×64 array of TDCs for time-of-flight (ToF) measurement. It has been fabricated in a 0.18µm standard CMOS technology. Small occupation area of 28×29μm2 and low average power consumption of 1.17mW at 850MHz are promising figures for this application field. Embedded phase alignment and instantaneous start-up time are required to minimize the offset of time interval measurements. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of 102dBc/Hz at 2MHz offset frequency from 850MHz.

Compact CMOS active quenching/recharge circuit for SPAD arrays
I. Vornicu, R. Carmona-Galán, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 44, no. 4, pp 917-928, 2016
JOHN WILEY & SONS    DOI: 10.1002/cta.2113    ISSN: 0098-9886    » doi
[abstract]
Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recherge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12 μm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break-down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post- layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse-width jitter is below 1.8 ns when dead time is set to 40 ns.

Time interval generator with 8 ps resolution and wide range for large TDC array characterization
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 87, no. 2, pp 181-189, 2016
SPRINGER    DOI: 10.1007/s10470-015-0641-9    ISSN: 0925-1030    » doi
[abstract]
Accurate generation of picosecond-resolution wide-range time intervals gives rise to a new time-efficient method for the characterization of large arrays of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20 ps RMS jitter for a pulse width ranging from 600 ps to 33 μs. The incremental time resolution is 8 ps and the repetition rate is up to 2 MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27 ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field. The measurement results of the time-to-digital converter array driven by the designed digital-to-time converter module are presented as well. The effectiveness of the proposed method is evaluated by comparing it with the statistical code density test.

On-chip time-of-flight estimation in standard CMOS technology
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper - SPIE Newsroom, Published online Feb 2015
SPIE    DOI: 10.1117/2.1201501.005721    ISSN: 1818-2259    » doi
[abstract]
In the last decade, CMOS image sensors (CISs) have reached a considerable level of maturity and their performance is now comparable with CCD sensors, in terms of image quality. CISs have almost completely replaced CCDs in commercial photo cameras and mobile phones. The main advantage of using CMOS technology is the possibility of integrating additional intelligence at the sensor level. Complex image processing algorithms can be run on-chip at high frame rates. A possible future development for CIS technology is to capture 3D information from a scene. This, however, requires active illumination schemes.

On the Calibration of a SPAD-Based 3D Imager with in-Pixel TDC Using a Time-Gated Technique
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2015
[abstract]
The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. The overall full-width half-maximum (FWHM) of the detector ensemble SPAD plus TDC is 690ps. The sensor has been fabricated in a 0.18μm standard CMOS technology which features an average dark-count rate (DCR) of 42Khz at 1V excess voltage (Ve) and room temperature. The detector successfully uses its time-gating capability to mitigate this large amount of noise enabling the sensor for accurate time-of-flight (ToF) measurements. The effectiveness of the time-gating technique is experimentally demonstrated. According to measurements, a time window of 400ns is enough to ensure that the TDC is triggered by light rather than by spurious events.

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2015
[abstract]
The design and measurements of a CMOS 64×64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reversed start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.

A CMOS imager for time-of-flight and photon counting based on single photon avalanche diodes and in-pixel time-to-digital converters
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Journal Paper - Romanian Journal of Information Science and Technology, vol. 17, no. 4, pp 353-371, 2014
ROMANIAN ACADEMY    ISSN: 1453-8245    
[abstract]
The design of a CMOS image sensor based on single-photon avalanche-diode (SPAD) array with in-pixel time-to-digital converter (TDC) is presented. The architecture of the imager is thoroughly described with emphasis on the characterization of the TDCs array. It is targeted for 3D image reconstruction. Several techniques as fast quenching/recharge circuit with tunable dead-time and time gated-operation are applied to reduce the noise and the power consumption. The chip was fabricated in a 0.18 μm standard CMOS process and implements a double functionality: time-of-flight (ToF) estimation and photon counting. The imager features a programmable time resolution of the array of TDCs down to 145 ps. The measured accuracy of the minimum time bin is lower than ± 1LSB DNL and ± 1.7 LSB INL. The TDC jitter over the full dynamic range is less than 1 LSB.

A CMOS 0.18μm 64x64 Single Photon Image Sensor with in-Pixel 11b Time-to-Digital Converter
I. Vornicu, R. Carmona and Á. Rodríguez-Vázquez
Conference - International Semiconductor Conference CAS 2014
[abstract]
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Wide Range 8ps Incremental Resolution Time Interval Generator based on FPGA technology
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2014
[abstract]
Accurate generation of picosecond-resolution wide-range time intervals has become a necessity for the characterization of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of timeto-digital converters. It can work as periodic pulse/ frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20ps RMS jitter over a time range of 600ps to 33μs. The incremental time resolution is 8ps and the repetition rate is up to 2MHz.The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field.

A CMOS 8×8 SPAD Array for Time-of-Flight Measurement and Light-Spot Statistics
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2013
[abstract]
The design and simulation of a CMOS 8 x 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of on-chip processing simplifies the interfacing of the array with the host system. The pixel pitch is 32μm, while the diameter of the quasi-circular active area of the SPADs is 12μm. The 113μm2 active area is surrounded by a T-well guard ring. The resulting breakdown voltage is 10V with a maximum excess voltage of 1.8V. The pixel incorporates a novel active quenching/reset circuit. The array has been designed to operate with a laser pulsed at 20Mhz. The overall time resolution is 115ps. Focal-plane statistics are obtained in digital format. The maximum throughput of the digital output buffers is 200Mbps.

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