Design considerations of an SRAM array for the statistical validation of time-dependent variability models P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018 abstract
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.
Single Event Transients trigger instability in Sigma-Delta Modulators D. Malagon, J.M. de la Rosa, R. del Río and G. Leger Conference · Conference on Design of Circuits and Integrated Systems DCIS 2014 abstract
In this paper we emulate the errors caused by SET in a Flexible 4th-Order Sigma-Delta Modulator with DC-to-44MHz Tunable Center Frequency in 1.2-V 90-nm CMOS. We identify the virtual ground of the integrators as a sensitive node and show that a charge injection may drive the modulator into long-term instability.
