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Author: Jiménez Través, Manuel
Year: Since 2002
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Hybrid Phase Transition FET Devices for Logic Computation
M. Jiménez, J. Núñez and M.J. Avedillo
Journal Paper - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp 1-8, 2020
IEEE    DOI: 10.1109/JXCDC.2020.2993313    ISSN: 2329-9231    » doi
[abstract]
Hybrid Phase Transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON to OFF current ratio. In this paper, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ONOFF current tradeoffs are evaluated at circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, on the basis of this analysis, the paper proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained which were lower than those achieved with low standby power (LSTP) FinFETs and high performance (HP) FinFETs. The paper also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.

Device circuit co-design of HyperFET transistors
J. Núñez, M. Jiménez and M.J. Avedillo
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2019
[abstract]
In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 50% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 80 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power advantages from the supply voltage reduction permitted by HyperFETs, and suggest guidance both at device and circuit level to take full advantage of these devices.

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
DOI: http://hdl.handle.net/10261/180405    » doi
[abstract]
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.

Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper - IEEE Electron Device Letters, vol. 39, no. 11, pp 1776-1779, 2018
IEEE    DOI: 10.1109/LED.2018.2871855    ISSN: 0741-3106    » doi
[abstract]
Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.

Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jiménez, M.J. Avedillo and J. Núñez
Conference - Conference on Ph.D Research in Microelectronics and Electronics PRIME 2018
[abstract]
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.

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