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Author: David Palomeque Mangut
Year: Since 2002
Journal Papers
A high-voltage floating level shifter for a multi-stage charge-pump in a standard 1.8 V/3.3 V CMOS process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 156, article 154389, 2022
abstract
doi
This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA.
A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · Sensors, vol. 22, no. 17, article 6429, 2022
abstract
doi
This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm(2). Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode-tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology's nominal supply, (2) residual charge-without passive discharging phase-was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.
A comparative study of stacked-diode configurations operating in the photovoltaic region
R. Gómez-Merchán, D. Palomeque-Mangut, J.A. Leñero-Bardallo, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper · IEEE Sensors Journal, vol. 20, no. 16, pp 9105-9113, 2020
abstract
doi
This article presents a detailed comparative analysis of two possible stacked-diode configurations operating as solar cells. The performance of a single p-well - deep n-well diode is compared with the combination of such diode with a n-diff - pwell diode in parallel. Both configurations occupy the same area but offer different performance and, accordingly, they can have different application scopes. A test circuit to gauge the diodes performance and their spectral sensitivity has been integrated along with the two diode configurations in a 0.18 μm CMOS standard fabrication technology. The measured experimental results for the two diode configurations under study are validated with an analytical diode physical model.
Conferences
Experimental Validation of a High-Voltage Compliant Neural Stimulator Implemented in a Standard 1.8V/3.3V CMOS Process
D. Palomeque-Mangut, A. Rodríguez-Vázquez and M Delgado-Restituto
Conference · IEEE Biomedical Circuits and Systems Conference BioCAS 2022
abstract
This paper describes a neural stimulator with 4 × VDD compliance voltage, delivering up to 2.08 mA, and implemented in a standard 180nm 1.8V/3.3V CMOS Process. The wide range of stimulation currents and high compliance voltage makes it suitable for stimulation applications both in rodents and mammals. Besides, it can be configured both as electrical and optical stimulator. Stacked transistor cells with dynamic gate biasing have been used for withstanding voltages well above the nominal supply. The system has been fabricated, occupying an active area of 2.34mm2. The circuit has been experimentally tested by connecting it to a custom μelectrode array which was immersed into a phosphate-buffered saline solution.
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils
D. Palomeque-Mangut, A. Schmid, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · Conference on Ph.D Research in Microelectronics and Electronics PRIME 2022
abstract
This paper proposes a system to transfer both mWpower and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.
A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process
D. Palomeque-Mangut, A. Rodríguez-Vázquez and M. Delgado-Restituto
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2022
abstract
A high-voltage (HV) floating level shifter which slides digital signals by varying the low supply rail from ground to VSSH while preserving the input signal swing is proposed. The cell is based on a periodically-refreshed charge pump circuit and it is suitable for non-HV CMOS processes. Input signals can be non-periodic. The circuit has been designed and implemented in a standard 180nm 1.8V/3.3V CMOS node, occupying 0.02mm2. Post-layout simulations show that VSSH voltage can safely range from 0.5V to 9.5V. The delay response of the circuit is 1.9 ns and it consumes 13.9 μW.
Voice-Controlled Assistance Device for Victims of Gender-Based Violence
M.A. Dominguez, D. Palomeque, J.M. Carrillo, J.M. Valverde, J.F. Duque, B. Perez and R. Perez-Aloe
Conference · Multidisciplinary International Conference of Research Applied to Defense and Security MICRADS 2019
abstract
One of the biggest problems that society is currently facing is violence against women. In recent years, tangible progress in protecting and saving the lives of female victims of intimate partner/family-related homicide has not been made, so targeted responses are clearly needed. In this work, an electronic device to help victims of gender-based violence who live with their aggressor has been designed. The system is built on Bluetooth Low Energy technology allowing a wireless communication between device and mobile phone with a low power consumption. The device is controlled by three different commands and is capable of sending messages through a mobile phone to a Control Center. Depending on the nature of the received messages, the Control Center will take the appropriate measures to assist the victim. The design has been made paying special attention to a reduced size so that the device can easily be camouflaged in any accessory of the victim's jewelry, thus going unperceived to the possible aggressor.
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