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Author: Javad Ahmadi Farsani
Year: Since 2002
Journal Papers
A CMOS-memristor hybrid system for implementing stochastic binary spike timing-dependent plasticity
J. Ahmadi-Farsani, S. Ricci, S. Hashemkhani, D. Ielmini, B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper · Philosophical Transactions. Series A, Mathematical, Physical, and Engineering Sciences, vol. 380, no. 2228, article 20210018, 2022
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This paper describes a fully experimental hybrid system in which a 4x4 memristive crossbar spiking neural network (SNN) was assembled using custom high-resistance state memristors with analogue CMOS neurons fabricated in 180 nm CMOS technology. The custom memristors used NMOS selector transistors, made available on a second 180 nm CMOS chip. One drawback is that memristors operate with currents in the micro-amperes range, while analogue CMOS neurons may need to operate with currents in the pico-amperes range. One possible solution was to use a compact circuit to scale the memristor-domain currents down to the analogue CMOS neuron domain currents by at least 5-6 orders of magnitude. Here, we proposed using an on-chip compact current splitter circuit based on MOS ladders to aggressively attenuate the currents by over 5 orders of magnitude. This circuit was added before each neuron. This paper describes the proper experimental operation of an SNN circuit using a 4x4 1T1R synaptic crossbar together with four post-synaptic CMOS circuits, each with a 5-decade current attenuator and an integrate-and-fire neuron. It also demonstrates one-shot winner-takes-all training and stochastic binary spike-timing-dependent-plasticity learning using this small system.
Reducing the Nonlinearity and Harmonic Distortion in FD-SOI CMOS Current-Starved Inverters and VCROs
P.I. Okorie, J. Ahmadi-Farsani and J.M.de la Rosa
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 142, article 153992, 2021
abstract
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This paper demonstrates experimentally how to reduce the nonlinearity of some analog and mixed-signal circuits by using the enhanced body effect provided by Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology. A current-starved CMOS inverter and a Voltage-Controlled Ring Oscillator (VCRO) are considered as case studies. The inverter is configured as a simple amplifier stage in which the harmonic distortion can be reduced and even removed by the combined action of the control voltages applied at the gate and bulk terminals of the current-source transistors. This current-starved inverter is used as the basic building block of a VCRO, where a more linear voltage-to-frequency characteristic can be achieved if the bulk terminal is used as the control voltage of the oscillator. The circuits under study have been designed and fabricated in a 28-nm FD-SOI technology and experimental results are shown to validate the presented approach.
Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage- Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs
J. Ahmadi-Farsani, V. Zúñiga-González, T. Serrano-Gotarredona, B. Linares-Barranco and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67 ,no. 10, pp 3297-3308, 2020
abstract
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This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks - such as switches, simple-stage transconductors and Voltage-Controlled Ring Oscillators (VCROs). Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor-level simulations of two VCRO-based ΣΔ modulators designed in a 28-nm FD-SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques.
Conferences
A Hybrid Memristor/CMOS SNN for Implementing One-Shot Winner-Takes-All Training
J. Ahmadi-Farsani, S. Ricci, S. Hashemkhani, D. Ielmini, B. Linares-Barranco and T. Serrano-Gotarredona
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2022
abstract
This paper presents a spiking neural network for pattern recognition. The network synapses are realized byReRAM cells, which are a stack of AU/Ti/C/Ti/HfO2/Pt. These cells are connected to an array of NMOS transistors (fabricated in a CMOS 180nm technology) to form a 4by4 1T1R crossbar between pre and post-synaptic circuitries. The pre-synaptic part contains conditioning circuits to reshape the inputs before applying them to the memristive crossbar. The post-synaptic section includes current attenuators that allowed the memristor domain currents to be mapped to neuron domain currents, as well as physiologically realistic neuron circuits fabricated in a CMOS 180nm technology. As a demonstrator, the network is trained with a one-shot winner-takes-all method to differentiate four input patterns in its inference mode.
A Real-Time DSP-based Biohybrid MEA System for Seizure Detection In Vitro
J. Ahmadi-Farsani, D. Caron, G. Panuccio, B. Linares-Barranco and T. Serrano-Gotarredona
Conference · IEEE International Symposium on Medical Measurements and Applications MeMeA 2021
abstract
This paper presents a biohybrid arrangement made of a commercial microelectrode array (MEA) system for seizure-like activity detection in brain slices. The set-up takes advantage of an embedded fixed-point digital signal processor (DSP) to implement a neuron model and a field-potential to spike converter (FP2SP). The neuron model is biologically plausible and capable of generating various firing modalities. Based on a three-step algorithm, FP2SP extracts spikes from the epileptiform activity generated by brain slices. The seizure detector system is developed by connecting the FP2SP to the model neuron and properly tuning the FP2SP parameters. The results show that all the blocks of this system can operate properly in real-time mode and recognize seizure-like activity.
Auxiliary Pulse-Extender and Current-Attenuator Circuits for Flexible Interaction with Memristive Crossbars in SNNs
J. Ahmadi-Farsani, B. Linares-Barranco and T. Serrano-Gotarredona
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2020
abstract
This paper presents a pulse-extender, a delay-element, and a current-attenuator as auxiliary circuits that make it possible to have flexible interaction with memristor crossbars in spiking neural networks. In the presynaptic part, the pulse-extender makes the inputs compatible with the pulsed-characterization of memristors. In the post-synaptic part, the current attenuator relaxes the system in terms of requiring low-offset amplifiers and also makes it possible to design neurons with small membrane capacitors. The circuits are fabricated in a CMOS 180nm technology. The measurements verify that these blocks play an important role in reaching an SNN with real-time performance.
A Current-Attenuator for Performing Read Operation in Memristor-Based Spiking Neural Networks
J. Ahmadi-Farsani, B. Linares-Barranco and T. Serrano-Gotarredona
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
abstract
This paper presents a current attenuator fabricated in a CMOS 180nm technology, which works based on a CMOS ladder scheme. The attenuation factor is 104.14 dB, while it shows a non-linearity feature of less than 1.8 %. The circuit occupies an area of 2448 µm2 . Since the output current could be as low as tens of femtoamperes, an on-chip testing circuit is also proposed to make the lab-measurements as accurate as possible. The final results show that chip-measurements are following simulations. As a demonstrator, the current attenuator is internally connected to a compact CMOS neuron cell. The output membrane potential shows that the neuron is generating a real-time firing modality, and consequently approves that the current-attenuator is working robustly.
Digital-Signal-Processor Realization of Izhikevich Neural Network for Real-Time Interaction with Electrophysiology Experiments
J. Ahmadi-Farsani, B. Linares-Barranco and T. Serrano-Gotarredona
Conference · IEEE International Conference on Electronics Circuits and Systems ICECS 2019
abstract
The paper presents a realization on a digital signal processor of an Izhikevich Neural Network operating with biologically plausible real-time constants. The paper demonstrates the real-time realization of different neuron behavioral modes, i.e., regular spiking, chattering, bursting, and fast spiking under proper parametrization. Real-time spike-timing-dependentplasticity has also been embedded in the neural network realization. The paper studies the maximum array size that can be implemented on a TMS320C6455 microprocessor to be able to reproduce correctly the real-time dynamics of the different behaviors. The TMS320C6454, from the same DSP family as TMS320C6455, is embedded in a commercial microelectrode array system for real time interaction with biological neural cell cultures. As demonstrator, a simple classification of two binary patterns has been implemented. Upon learning activation, the system robustly unsupervisely learns to differentiate the two patterns.
Analysis of Linearity in FD-SOI Body-Input Voltage Controlled Ring Oscillators - Application to ADCs
J. Ahmadi-Farsani and J.M. de la Rosa
Conference · IEEE Midwest Symposium on Circuits and Systems MWSCAS 2019
abstract
This paper studies the use of the body terminal as control voltage of ring oscillators implemented in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) processes, thus allowing a wider tuning range of the threshold voltage. This effect is exploited in this work to improve the linearity of Voltage-Controlled Ring Oscillators (VCROs) to be used as building blocks of Analog-to-Digital Converters (ADCs). An intuitive analysis of basic VCRO current-starved inverter cells is carried out in order to derive an approximate expression of the voltage-to-frequency characteristic. Electrical simulations in a 28-nm node are shown to get insight about the influence of main design parameters and applied to the design of VCRO-based Sigma-Delta (SD) ADCs up to the layout level, whose performance metrics demonstrate the benefits of the presented approach.
Bulk-input VCO-based sigma-delta ADCs with enhanced linearity in 28-nm FD-SOI CMOS
J. Ahmadi-Farsani and J.M. de la Rosa
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2019
abstract
This paper investigates the use of the transistor threshold-voltage tuning feature available in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology in order to improve the performance of Voltage-Controlled Oscillators (VCOs) with application in Analog-to-Digital Converters (ADCs). Circuit techniques that exploit the benefits of the enhanced body-effect biasing tunnability are applied to the proposed VCO in order to improve its linearity, frequency range and robustness to technology-process variations with respect to conventional ring oscillators. The proposed circuit is applied to the design of a second-order ΣΔ ADC clocked at a configurable rate of 1-to-2 GHz. The ADC uses a multi-phase VCO-based front-end integrator as the only analog circuit, while the rest of its building blocks are digital circuits. Transistor-level simulations show that the presented techniques improve the linearity with respect to conventional VCO-based ΣΔMs, featuring 10-bit effective resolution within a 10-MHz signal bandwidth, with an estimated power consumption of 230μW.
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