Spanish National Research Council · University of Seville
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Author: Fernández Fernández, Francisco V.
Year: Since 2002
All publications
Synthesis of mm-Wave circuits using EM-simulated passive structure libraries
F. Passos, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Millimeter-wave circuit design is extremely complex and time-consuming. One of the reasons is the dependence on electromagnetic simulators used to accurately predict the performance of the high amount of passive structures that compose such circuits. Also, achieving optimal performances is not trivial in the millimeter-wave regime. Although synthesis methodologies can aid the designer to achieve optimal circuit performances, the usage of electromagnetic simulators is prohibitive in such methodologies due to efficiency issues. In this work, a new synthesis methodology is presented where the accuracy of electromagnetic simulations can be included without losing efficiency.

Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Reliability in CMOS-based integrated circuits has always been a critical concern. In today′s ultra-scaled technologies, a time-varying kind of variability has raised that, on top of the well-known time-zero variability, threatens to shorten the lifetime of integrated circuits, both analog and digital. Effects like Bias Temperature Instability and Hot Carriers Injection need to be studied, characterized and modeled to include, and, thus, mitigate, their impact in the design of CMOS integrated circuits. This paper presents an array-based integrated circuit whose purpose is precisely that: to observe, quantify and characterize the impact of timedependent variability effects in a specific kind of circuits: Ring Oscillators.

TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Time-Dependent Variability has attracted increasing interest in the last years. In particular, phenomena such as Bias Temperature Instability, Hot Carrier Injection and Random Telegraph Noise can have a large impact on circuit reliability, and must be therefore characterized and modeled. For technologies in the nanometer range, these phenomena reveal a stochastic behavior and must be characterized in a massive manner, with enormous amounts of data being generated in each measurement. In this work, a novel tool with a user-friendly interface, which allows the robust and fullyautomated parameter extraction for RTN, BTI and HCI experiments, is presented.

Two-Step RF IC Block Synthesis with Preoptimized Inductors and Full Layout Generation In-the-Loop
R. Martins, N. Lourenço, F. Passos, R. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández and N. Horta
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 6, pp 989-1002, 2019
IEEE    DOI: 10.1109/TCAD.2018.2834394    ISSN: 0278-0070    » doi
[abstract]
In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper - Microelectronic Engineering, vol. 215, article 111004, 2019
ELSEVIER    DOI: 10.1016/j.mee.2019.111004    ISSN: 0167-9317    » doi
[abstract]
Random Telegraph Noise (RTN) has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which can cause performance degradation in circuits. In this work, the dependence of RTN parameters, namely current jump amplitude and emission and capture time constants, on the bias conditions, both VG and VD, has been studied on a set of devices, with a high granularity in a broad voltage range. The results obtained for the VG dependences corroborate previous works, but suggest a unique trend for all the devices in a VG range that goes from the near-threshold region up to voltages over the nominal operation bias. However, different trends have been observed in the parameters dependence for the case of VD. From the experimental data, the probabilities of occupation of the associated defects have been evaluated, pointing out large device-to-device dispersion in the VD dependences.

Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Design Automation and Test in Europe DATE 2019
[abstract]
Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez
Conference - Design Automation and Test in Europe DATE 2019
[abstract]
Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometerscale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

A new time efficient methodology for the massive characterization of RTN in CMOS devices
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Conference - IEEE International Reliability Physics Symposium IRPS 2019
[abstract]
Abstract not avaliable

A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Journal Paper - Solid-State Electronics, vol. 159, pp 99-105, 2019
ELSEVIER    DOI: 10.1016/j.sse.2019.03.045    ISSN: 0038-1101    » doi
[abstract]
In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.

Flexible Setup for the Measurement of CMOS Time-Dependent Variability with Array-Based Integrated Circuits
J. Diaz-Fortuny, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, F.V. Fernandez and M. Nafria
Journal Paper - IEEE Transactions on Instrumentation and Measurement, first online, 2019
IEEE    DOI: 10.1109/TIM.2019.2906415    ISSN: 0018-9456    » doi
[abstract]
This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

A Multilevel Bottom-up Optimization Methodology for the Automated Synthesis of RF Systems
F. Passos, E. Roca, J. Sieiro, R. Fiorelli, R. Castro-López, J.M. López-Villegas and F.V. Fernández
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2019
IEEE    DOI: 10.1109/TCAD.2018.2890528    ISSN: 0278-0070    » doi
[abstract]
In recent years there has been a growing interest in electronic design automation methodologies for the optimizationbased design of radiofrequency circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle radiofrequency systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this work, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multi-objective optimization algorithms are used to design an entire radiofrequency system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
J. Diaz-Fortuny, J. Martin-Martines, R. Rodriguez, R. Castro-Lopez, E. Roca, X. Aragones, E. Barajas, D. Mateo, F.V. Fernandez and M. Nafria
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp 476-488, 2019
IEEE    DOI: 10.1109/JSSC.2018.2881923    ISSN: 0018-9200    » doi
[abstract]
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm2.

Optimization and CMOS design of chaotic oscillators robust to PVT variations
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, J.M. Muñoz-Pacheco, L.G. de la Fraga, C. Sanchez-Lopez and F.V.Fernandez-Fernandez
Journal Paper - Integration, vol. 65, pp 32-42, 2019
ELSEVIER    DOI: 10.1016/j.vlsi.2018.10.010    ISSN: 0167-9260    » doi
[abstract]
Edward Lorenz was an early pioneer of the chaos theory. He discovered that small changes in initial conditions produce large changes in long-term outcome, and introduced a chaotic attractor already known as Lorenz chaotic oscillator, which produces a butterfly-like behavior. This and all kinds of continuous-time chaotic oscillators can be simulated with different numerical methods. However, a bad choice of the step size and/or parameters of the mathematical models can produce errors or even mitigate the chaotic behavior. These issues are related to the main property of chaotic oscillators, the high sensitivity to the initial conditions, which is quantified by evaluating the maximum Lyapunov exponent (MLE). The Lorenz and other representative oscillators like Lü, Chua's circuit and Rössler have been implemented using different discrete electronic devices and few ones with integrated circuits (IC) using CMOS technologies. Designing CMOS chaotic oscillators is challenging because a very small variation in their parameters from their mathematical models or in the sizes of the MOS transistors may suppress the chaotic behavior. This article describes how to perform a successful simulation and optimization, and how to synthesize the mathematical models using CMOS technology. The application of metaheuristics to optimize MLE by varying the parameters of the oscillators, and the optimization of the CMOS IC design to guarantee robustness to process, voltage and temperature (PVT) variations, are discussed. Finally, we discuss issues on the application of chaos generators in random number generators, robotics and chaotic secure communication systems.

A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - Soft Computing, vol. 23, no. 13, pp 4911-4925, 2019
SPRINGER    DOI: 10.1007/s00500-018-3150-9    ISSN: 1432-7643    » doi
[abstract]
The knowledge-intensive radiofrequency circuit design and the scarce design automation support play against the increasingly stringent time-to-market demands. Optimization algorithms are starting to play a crucial role; however, their effectiveness is dramatically limited by the accuracy of the evaluation functions of objectives and constraints. Accurate performance evaluation of radiofrequency passive elements, e.g., inductors, is provided by electromagnetic simulators, but their computational cost makes their use within iterative optimization loops unaffordable. Surrogate modeling strategies, e.g., Kriging, support vector machines, artificial neural networks, etc., arise as a promising modeling alternative. However, their limited accuracy in this kind of applications has prevented a widespread use. In this paper, inductor performance properties are exploited to develop a two-step surrogate modeling strategy in order to evaluate the behavior of inductors with high efficiency and accuracy. An automated design flow for radiofrequency circuits using this surrogate modeling of passive components is presented. The methodology couples a circuit simulator with evolutionary computation algorithms such as particle swarm optimization, genetic algorithm or non-dominated sorting genetic algorithm (NSGA-II). This methodology ensures optimal performances within short computation times by avoiding electromagnetic simulations of inductors during the entire optimization process and using a surrogate model that has less than 1% error in inductance and quality factor when compared against electromagnetic simulations. Numerous real-life experiments of single-objective and multi-objective low-noise amplifier design demonstrate the accuracy and efficiency of the proposed strategies.

PVT-robust CMOS programmable chaotic oscillator: Synchronization of two 7-scroll attractors
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, C. Sanchez-Lopez and F.V. Fernandez-Fernandez
Journal Paper - Electronics, vol. 7, no. 10, article 252, 2018
MDPI    DOI: 10.3390/electronics7100252    ISSN: 2079-9292    » doi
[abstract]
Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2-7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μm CMOS technology. Post-layout and process-voltage-temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master-slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

A comparison of automated RF circuit design methodologies: online vs. offline passive component design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 11, pp 2386-2394, 2018
IEEE    DOI: 10.1109/TVLSI.2018.2859827    ISSN: 1063-8210    » doi
[abstract]
In this paper, surrogate modeling techniques are applied for passive component modeling. These techniques are exploited to develop and compare two alternative strategies for automated radio-frequency circuit design. The first one is a traditional approach where passive components are designed during the optimization stage. The second one, inspired on bottom-up circuit design methodologies, builds passive component Pareto-optimal fronts (POFs) prior to any circuit optimization. Afterward, these POFs are used as an optimized library from where the passive components are selected. This paper exploits the advantages of evolutionary computation algorithms in order to efficiently explore the circuit design space, and the accuracy and efficiency of surrogate models to model passive components.

CMOS characterization and compact modelling for circuit reliability simulation
J. Diaz Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference - IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
[abstract]
With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.

Analysis of Body Bias and RTN-induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology
E. Barajas, X. Aragones, D. Mateo, F. Moll, J. Martin-Martinez, R. Rodríguez, M. Portí, M. Nafria, R. Castro-López, E. Roca and F.V Fernández-Fernández
Conference - Int. Symposium on Power and Timing Modeling, Optimization and Simulation PATMOS 2018
[abstract]
Electronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant at such supply voltages. This paper evaluates the impact of RTN on additional jitter in a ring oscillator. Since FDSOI allows a large range of body bias voltages, this work studies how body biasing affects the oscillation frequency but also the jitter effects. The impact of RTN in NMOS and PMOS devices on frequency as well as the levels of supplementary jitter introduced by RTN are evaluated and compared with classical device noise.

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Castro-López, R. Póvoa, A. Canelas, N. Horta and F.V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
This paper exposes the problematic issue of not considering device variability and layout parasitic effects in optimization-based design of radiofrequency integrated circuits. Therefore, in order to handle these issues, a new design methodology that performs an all-inclusive optimization is proposed, by taking into account the process variability, and, performing the complete layout automatically while performing an accurate parasitic extraction during the optimization for each candidate solution. Furthermore, the problematic inductor parasitics are also taken into account with EM-accuracy, by using a state-of-the-art surrogate modelling technique. The methodology was applied in the design and optimization of a low-noise amplifier, obtaining a set of extremely robust designs ready for fabrication.

Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs
A. Toro-Frías, P. Martín-Lloret, J. Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability but also the degradation due to time-dependent. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation
J. Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-Lopez, J. Martin-Martinez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by timedependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of aging device effects for reliability circuit

Automated massive RTN characterization using a transistor array chip
P. Saraza-Canflanca, J. Diaz-Fortuny, A. Toro-Frias, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
In this work, a CMOS transistor array for the massive measurement of random telegraph noise (RTN), together with a dedicated experimental setup, is presented. The array chip, called ENDURANCE, allows the massive characterization of the RTN parameters needed for a complete understanding of the phenomenon. Additionally, some experimental results are presented that demonstrate the convenience of the setup.

A novel design methodology for the mixed-domain optimization of a MEMS accelerometer
M. Pak, F.V. Fernandez and G. Dundar
Journal Paper - Integration, vol. 62, pp 314-321, 2018
ELSEVIER    DOI: 10.1016/j.vlsi.2018.03.018    ISSN: 0167-9260    » doi
[abstract]
This paper proposes a novel optimization-based design methodology that can be used for mixed-domain synthesis of MEMS accelerometers. Several problems have been identified with existing methodologies and comparative experiments that demonstrate the superiority of the proposed approach are performed. Highly accurate analytical models of the MEMS accelerometer have been used for the evaluation of the MEMS sensor performances in the mixed-domain optimization. The circuit level simulations, on the other hand, are based on an electrical simulator, e.g., Hspice. The implemented methodology has been tested on the optimization of a MEMS accelerometer that includes a capacitive MEMS sensor and an analog read-out circuitry.

Weighted Time Lag Plot Defect Parameter Extraction and GPU-based BTI Modeling for BTI Variability
V.M. van Santen, J. Diaz-Fortuny, H. Amrouch, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez, J. Henkel and M. Nafria
Conference - IEEE International Reliability Physics Symposium IRPS 2018
[abstract]
Recent MOSFET devices exhibit a strong variability in their Bias Temperature Instability (BTI) induced degradation (e.g., Vth-shift). For identical stress patterns, each device exhibits unique degradation behavior. As BTI variability increases with shrinking device geometries, modeling BTI variability becomes essential. The challenge of modeling BTI variability is the significant time required to characterize a representative set of devices to properly calibrate the BTI variability model. In addition, (SPICE) circuit simulations under BTI variability are extremely time consuming. Both challenges originate from unique uncorrelated BTI behavior in each device. Each device features a unique set of defects with a unique state (occupied/unoccupied) in each defect. In this work, we tackle the characterization challenge by processing the data acquired from our parallel measurement setup with lightweight and fast defect extraction. Our novel weighted time lag plot defect parameter extraction, removes uncorrelated voltage noise and categorizes correlated noise (i.e., Random Telegraph Noise (RTN)) and discrete voltage steps (i.e., BTI). After the measurement data is processed, capture time, emission time and induced degradation of each defect can be extracted. After defect parameters are extracted, we can fit a bi-variate log-normal defect distribution and calibrate our BTI model. To employ a BTI variability model in circuit simulation, it must be able to model thousands of MOSFETs. Circuits consist of thousands of devices, each with unique behavior, resulting in computationally intensive modeling. Our GPU-based BTI variability model employs massive parallelism (beyond 1000 processing cores) found in graphic cards to model thousands of MOSFETs in seconds. Therefore, our novel defect parameter extraction methodology allows lightweight, yet accurate characterization of our model, while our model itself enables circuit simulations in large circuits as it models 100,000 MOSFETs in just 119s.

A noise and RTN-removal smart method for the parameter extraction of CMOS aging compact models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference - Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
[abstract]
This work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔV th ) related to oxide defects in nanometer CMOS transistors during aging tests. The method identifies the V th drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.

Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
S. Ahyoune, J. Sieiro, T. Carrasco, N. Vidal, J.M. López-Villegas, E. Roca and F.V. Fernández
Journal Paper - Integration, vol. 63, pp 332-341, 2018
ELSEVIER    DOI: 10.1016/j.vlsi.2018.02.006    ISSN: 0167-9260    » doi
[abstract]
In this work, a quasi-static implementation of the partial element equivalent circuit (PEEC) method for the analysis of planar radiofrequency (RF) and microwave (uW) components is proposed. The procedure is divided in three parts. First, an alternative PEEC formulation based on energy concepts is described. Second, a smart mesh generator is developed in order to provide an accurate solution at minimum computational costs, taking into account both geometry and device physics as metrics for the correct sizing of mesh elements. And third, a weighted combination of the 2D and 3D quasi-static Green's functions (GF) is proposed for extending the valid frequency range of the quasi-static approximation. It is shown that the 3D-GF is very accurate at low frequency, whereas the 2D-GF is more suitable at higher frequencies. Numerical examples are compared to experimental data for different passive components and technologies in a wide frequency range.

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Póvoa, A. Canelas, R. Castro-López, N. Horta and F.V. Fernández
Journal Paper - Integration, vol. 63, pp 351-361, 2018
ELSEVIER    DOI: 10.1016/j.vlsi.2018.02.005    ISSN: 0167-9260    » doi
[abstract]
In this paper a design strategy based on bottom-up design methodologies is used in order to systematically design a voltage controlled oscillator. The methodology uses two computer-aided design tools: AIDA, a multi-objective multi-constraint circuit optimization tool, and SIDe-O, a tool that characterizes and optimizes integrated inductors with high accuracy (around 1% when compared to electromagnetic simulations). By using such tools, the difficult trade-offs inherent to radio-frequency circuits can be explored efficiently and accurately. Furthermore, with the capability that AIDA has at considering process parameter variations during the optimization, the resulting methodology is able to obtain truly robust circuit designs.

Introduction to the special issue on PRIME 2016 and SMACD 2016
N. Horta, A. Baschirotto, F.V. Fernández, G. Dundar, J. Goes and J. Fernandes
Journal Paper - Integration, the VLSI Journal, vol. 58, pp 411-412, 2017
ELSEVIER    DOI: 10.1016/j.vlsi.2017.03.015    ISSN: 0167-9260    » doi
[abstract]
This special issue of Integration, the VLSI Journal is devoted to the 2016 edition of 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2016) and 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2016), which were co-located and took place on 27th-30th June 2016 in Lisbon, Portugal.

Reliability in the circuit design flow: from characterization and modelling to design automation
R. Castro-López, J. Díaz, J. Martín-Martínez, R. Rodríguez, M. Nafría, A. Toro, P. Martín, E. Roca, F.V. Fernández, E. Barajas, X. Aragonés and D. Mateo
Conference - How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop 2017
[abstract]
Designing reliable analog circuits in advanced process technologies requires an accurate understanding of both device performance and variability. The unavoidable and increasingly important process-induced variations is, today, not alone in perturbing the ideal, intended performance of analog circuits: the so-called aging phenomena, like Bias Temperature Instability and Hot Carriers Injection, are altogether making the analog design business a much more tortuous endeavour. The work presented here will paint a complete picture of how to deal with variability in analog circuits for advanced process technologies. This picture starts with the characterisation and modelling of the aging phenomena at the device level. It then will show how these models can be used in the simulation of analog circuits, explaining the issues to overcome and the solutions that can be adopted. With these accurate models and capable circuit simulation techniques, the picture ends with a proposal for an analog design methodology that, using advanced optimization techniques, can successfully take into accounts all sources of variations (process and aging related) so that reliable analog circuits can be attained.

Efficient Computation of Yield and Lifetime for Analog ICs under Process Variabiliy and Aging
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
[abstract]
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability (i.e., spatial or process variability) but also the degradation due to time-dependent variability (i.e., aging). While process variability has been extensively treated, solutions to cope with aging-related problems are, nowadays, not yet mature enough, especially in the field of analog circuit simulation. Nevertheless, considerable efforts are currently being made to develop new simulation tools and simulation methodologies to evaluate the impact of reliability effects. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

Statistical characterization of reliability effects in nanometer CMOS using a versatile transistor array IC
J. Díaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca, F.V. Fernández, E. Barajas-Ojeda, X. Aragones and D. Mateo-Peña
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
[abstract]
In this work, an experimental framework for the characterization of various reliability effects in modern CMOS technologies is described. The main element in this framework is a versatile transistor array chip, designed to accurately characterize process variability, Random Telegraph Noise and BTI/HCI related time dependent variability effects. The measurement setup, the other element in the framework, has been designed to take full advantage of the array architecture, which allows parallel testing of its 3136 MOS transistors, thereby reducing considerably the total measurement time. Thanks to a control toolbox and a user-friendly GUI, the setup also facilitates the programming of any of the required characterization tests.

A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca, F.V. Fernandez, E. Barajas, X. Aragones and D. Mateo
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.

Optimization of a MEMS Accelerometer using a Multiobjective Evolutionary Algorithm
M. Pak, F.V. Fernandez and G. Dundar
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
This paper focuses on the optimization of a fixed-topology MEMS accelerometer sensor using the MOEA/D evolutionary algorithm. Several methodologies have been implemented for the optimization of MEMS sensors. These techniques are either based on sweeping several design parameters to achieve a good performance or focused on the sensitivity analysis to determine the effects of each design parameter in order to find an optimal point. All of these techniques lead to some high performance device designs; however, with the integration of the sensor models into the MOEA/D optimization algorithm, optimal design points can be achieved by using multi-objective optimization. In this work, highly accurate sensor models have been integrated into the optimization loop in order to obtain optimal Pareto Fronts of a MEMS Accelerometer topology. Both of the sensor models and the optimization algorithm has been implemented using Matlab. The results are compared with a commercial design with the same topology and an improvement of 29% of noise performance for a similar sensor area, or an improvement of 25% sensor area for a similar noise performance has been achieved.

Statistical characterization of unreliability effects in a 65-nm CMOS transistor array
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference - International Mixed-Signals Testing Workshop IMSTW 2017
[abstract]
In this work, a CMOS transistor array is presented which enables characterization of variability, Random Telegraph Noise and BTI/CHC aging. The array integrates 3,136 MOS transistors for massive electrical testing. This array, together with a dedicated test setup with graphical interface feature easy programming of the required characterization tests, visualization of results and post-processing algorithms for the defect characterization required in aging modeling and simulation.

A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs
P. Martín-Lloret, A. Toro-Frías, J. Martin, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. Most of the up to day models focused on the aging phenomena make use of the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occurs while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower computational budgets.

Including a stochastic model of aging in a reliability simulation flow
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
The availability and efficiency of reliability simulators for analog ICs is becoming critical with the scaling of devices down to the nanometer nodes. Two of the main challenges here are how to simultaneously include different sources of unreliability (such as the time-zero or spatial variability and the aging or time-dependent variability), and how to account for the self-induced changes in device biasing (i.e., stress conditions) caused by the device wear-out. In addition to the already existing stochastic models for time-zero variability, new models for the stochastically-distributed aging mechanisms have been developed in recent years. The combination of these challenges with the need for dealing with a stochastic model for aging, causes a serious computational load issue. This paper presents different methods to accurately include reliability in the simulation of analog ICs while preventing the simulation to become unaffordable in terms of CPU time and load.

A strategy to efficiently include electromagnetic simulations in optimization-based RF circuit design methodologies
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, and J.M. López-Villegas
Conference - IEEE MTT-S Int. Conf. on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and Terahertz Applications NEMO 2017
[abstract]
The use of electromagnetic simulations is crucial in radiofrequency and microwave circuits since accurate estimations of parasitics and performances are essential. In addition, design methodologies based on optimization algorithms have been used in order to design such circuits, while efficiently exploring its design trade-offs. However, due to the high computational cost, optimization-based methodologies seldom use electromagnetic simulation. In order to overcome this issue, this paper demonstrates an optimization-based design methodology for radiofrequency circuits which can incorporate electromagnetic simulations without efficiency loss.

Systematic design of a voltage controlled oscillator using a layout-aware approach
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, R. Martins, N. Lourenço, R. Póvoa, A. Canelas and N. Horta
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
This paper focuses on the systematic design of voltage controlled oscillators (VCO), a commonly used radiofrequency (RF) electronic circuit. RF circuits are among the most difficult analog circuits to design due to its trade-offs and high operation frequencies. At such operation frequencies, layout parasitics and accurate passive component characterization become of upmost importance, causing re-design iterations if they are not considered by the designer. To avoid this problem, and reduce the design time, this paper presents a systematic design of a VCO, entailing layout parasitics and accurate characterization of passive components from early design stages. Results clearly illustrate the benefit of this strategy.

An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Conference - IEEE Congress on Evolutionary Computation CEC 2017
[abstract]
This paper describes a class of real-life optimization problems that has not been addressed before: a multi-objective optimization in which one objective is neither minimized nor maximized but uniformly swept over a wide range. The limitations of conventional multi-objective optimization algorithms to deal with this kind of problems are illustrated via the optimization of radiofrequency inductors. For the first time, an algorithm is proposed that provides sets of solutions for this kind of problems.

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks
R. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca and F.V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established computer-aided design tools available nowadays, i.e., off-the-shelf circuit simulator, electromagnetic simulator and layout extractor. The approach intends to bypass the two major bottlenecks of RF-design: the design of reliable integrated inductors and accurate layout parasitic estimates since the early stages of design process.

CASE: A reliability simulation tool for analog ICs
P. Martín-Lloret, A. Toro-Frías, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
With the evolution in the scale of integration in ICs, aging-related problems are becoming more important and, nowadays, solutions to cope with these issues are not yet mature enough, especially in the field of analog circuit simulation. CASE, the novel simulator presented in this paper, can evaluate the impact of reliability effects in analog circuits through a stochastic physic-based model. The implemented simulation flow is accurate and efficient in terms of CPU. The two main improvements over currently reported and commercial tools, is that the simulator can simultaneously take into account both time-zero and time-dependent variability, and that an adaptive method, to account for the strong link between biasing and stress, can improve the accuracy while keeping acceptable CPU times.

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
N. Lourenço, R. Martins, R. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca and F. V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
This paper presents new indexing and mutation operators, in the context of bottom-up hierarchical multi-objective optimization of radio frequency integrated circuits, for pre-optimized sets of solutions from the hierarchical sub-levels when moving up in hierarchy. Two ideas, one based on a Voronoi decomposition and another based on the nearest neighborhood, are explored, where, and unlike previous approaches that are based on sorting, the distance between elements determines the probability of decisions taken during optimization. Three implementations of those ideas were tried in AIDA's NSGAII evolutionary kernel, and successfully used in the optimization of a Voltage Controlled Oscillator and a Low Noise Amplifier with pre-optimized inductor sets obtained using the SIDeO toolbox, showing their strengths when compared to previous state-of-the-art mapping strategies.

TARS: A toolbox for statistical reliability modeling of CMOS devices
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
This paper presents a toolbox for the automation of the electrical characterization of CMOS transistors. The developed software provides a user-friendly interface to carry out different tests to evaluate time-zero (i.e., process) and time-dependent variability in CMOS devices. Also, the software incorporates a post-processing capability that allows users to visualize the data. Moreover, without loss of generality, the toolbox allows the user, from the measured data, to feed a particular physics-based model that accounts for various aging phenomena.

Dependence of MOSFETs threshold voltage variability on channel dimensions
C. Couso, J. Diaz-Fortuny, J. Martin-Martinez, M. Porti, R. Rodriguez, M. Nafria, F.V. Fernandez, E. Roca, R. Castro-Lopez, E. Barajas, D. Mateo and X. Aragones
Conference - Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2017
[abstract]
The dependence of the MOSFET threshold voltage variability on device geometry (width (W) and length (L)) has been studied from experimental data. Our results evidence, in agreement with other works, deviations from the Pelgrom's rule, especially in smaller technologies. TCAD simulations were also performed which further support the experimental data and provide physical information regarding the origin of such deviation. Finally, a new empirical model that assumes different impact of W and L in the device variability has been proposed, which reproduces the experimental results.

Extending the frequency range of quasi-static electromagnetic solvers
S. Ahyoune, J. Sieiro, T. Carrasco, N. Vidal, J. M. López-Villegas, E. Roca and F.V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
[abstract]
In this work, a combination of 2D and 3D quasi-static Green's functions (GF) is proposed for extending the frequency range validity of the quasi-static approximation. It is shown that 3D-GF is very accurate at low frequency, whereas 2D-GF is more suitable at higher frequencies because it is the actual solution of the transverse electromagnetic (TEM) propagation mode. The mixing of both GFs is controlled through the ratio of the main size of the device versus the wavelength at the given simulation frequency. Numerical examples are compared with experimental data for different passives in a broadband frequency range.

Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling
F. Passos, E. Roca, R.Castro-López and F.V. Fernández
Journal Paper - Applied Soft Computing, vol. 60, pp 495-507, 2017
ELSEVIER    DOI: 10.1016/j.asoc.2017.07.036    ISSN: 1568-4946    » doi
[abstract]
In recent years, the application of evolutionary computation techniques to electronic circuit design problems, ranging from digital to analog and radiofrequency circuits, has received increasing attention. The level of maturity runs inversely to the complexity of the design task, less complex in digital circuits, higher in analog ones and still higher in radiofrequency circuits. Radiofrequency inductors are key culprits of such complexity. Their key performance parameters are inductance and quality factors, both a function of the frequency. The inductor optimization requires knowledge of such parameters at a few representative frequencies. Most common approaches for optimization-based radiofrequency circuit design use analytical models for the inductors. Although a lot of effort has been devoted to improve the accuracy of such analytical models, errors in inductance and quality factor in the range of 5%-25% are usual and it may go as high as 200% for some device sizes. When the analytical models are used in optimization-based circuit design approaches, these errors lead to suboptimal results, or, worse, to a disastrous non-fulfilment of specifications. Expert inductor designers rely on iterative evaluations with electromagnetic simulators, which, properly configured, are able to yield a highly accurate performance evaluation. Unfortunately, electromagnetic simulations typically take from some tens of seconds to a few hours, hampering their coupling to evolutionary computation algorithms. Therefore, analytical models and electromagnetic simulation represent extreme cases of the accuracy-efficiency trade-off in performance evaluation of radiofrequency inductors. Surrogate modeling strategies arise as promising candidates to improve such trade-off. However, obtaining the necessary accuracy is not that easy as inductance and quality factor at some representative frequencies must be obtained and both performances change abruptly around the self-resonance frequency, which is particular to each device and may be located above or below the frequencies of interest. Both, offline and online training methods will be considered in this work and a new two-step strategy for inductor modeling is proposed that significantly improves the accuracy of offline methods The new strategy is demonstrated and compared for both, single-objective and multi-objective optimization scenarios. Numerous experimental results show that the proposed two-step approach outperforms simpler application strategies of surrogate modelling techniques, getting comparable performances to approaches based on electromagnetic simulation but with orders of magnitude less computational effort.

Parametric macromodeling of integrated inductors for RF circuit design
F. Passos, Y. Ye, D. Spina, E. Roca, R. Castro-López, T. Dhaene and F.V. Fernández
Journal Paper - Microwave and Optical Technology Letters, vol. 59, no. 5, pp 1207-1212, 2017
JOHN WILEY & SONS    DOI: 10.1002/mop.30498    ISSN: 1098-2760    » doi
[abstract]
Nowadays, parametric macromodeling techniques are widely used to describe electromagnetic structures. In this contribution, the application of such parametric macromodeling techniques to the design of integrated inductors and radio-frequency circuit design is investigated. In order to allow such different operations, a new modeling methodology is proposed, which improves the modeling accuracy when compared to former techniques. The new methodology is tailored to the unique characteristics of the devices under study. The obtained parametric macromodel is then used in a synthesis methodology and in the design of a voltage controlled oscillator in a 0.35-μm CMOS technology.

An inductor modeling and optimization toolbox for RF circuit design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - Integration, the VLSI Journal, vol. 58, pp 463-472, 2017
ELSEVIER    DOI: 10.1016/j.vlsi.2017.01.009    ISSN: 0167-9260    » doi
[abstract]
This paper describes the SIDe-O toolbox and the support it can provide to the radio-frequency designer. SIDe-O is a computer-aided design toolbox developed for the design of integrated inductors based on surrogate modeling techniques and the usage of evolutionary optimization algorithms. The models used feature less than 1% error when compared to electromagnetic simulations while reducing the simulation time by several orders of magnitude. Furthermore, the tool allows the creation of S-parameter files that accurately describe the behavior of inductors for a given range of frequencies, which can later be used in SPICE-like simulations for circuit design in commercial environments. This toolbox provides a solution to the problem of accurately and efficiently optimizing inductors, which alleviates the bottleneck that these devices represent in the radio-frequency circuit design process.

An automated design methodology of RF circuits by using Pareto-optimal fronts of EM-simulated inductors
R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, J. Sieiro, J.M. López-Villegas and N. Vidal
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp 15-26, 2017
IEEE    DOI: 10.1109/TCAD.2016.2564362    ISSN: 0278-0070    » doi
[abstract]
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a single-objective and a multi-objective optimization of a Low Noise Amplifier.

A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs
P. Martín, A. Toro, R. Castro, E. Roca, F.V. Fernández, J. Martín-Martínez and M. Nafría
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2016
[abstract]
Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. Most of the up to day models focused on the aging phenomena make use of the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occurs while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower computational budgets.

A Hierarchical Design Automation Concept for Analog Circuits
G. Berkol, E. Afacan, G. Dündar and F.V. Fernandez
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2016
[abstract]
This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.

Optimization of LDO Voltage Regulators by NSGA-II
J. López-Arredondo, E. Tlelo-Cuautle and F.V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2016
[abstract]
Two different low-dropout (LDO) voltage regulators are optimized by applying the Non-Dominated Sorting Genetic Algorithm II (NSGA-II). First, from a sensitivity analysis a set of design variables are selected to establish a reduced chromosome for performing multi-objective optimization by NSGA-II. The computed sensitivities are used to reduce the search spaces for the design variables included into the chromosome, so that the optimization process is accelerated. Second, a comparison between traditional and optimization-based design approaches is shown by considering 2 figures of merit (FoM). Finally, we list the results for optimizing 2 LDO voltage regulators for the 2 FoMs, and provide optimized sizes that are compared to traditional design.

Introduction to the special issue on SMACD 2015
G. Dundar, N. Horta and F.V. Fernandez
Journal Paper - Integration, the VLSI Journal, vol. 55, pp 293-294, 2016
ELSEVIER    DOI: 10.1016/j.vlsi.2016.09.001    ISSN: 0167-9260    » doi
[abstract]
Abstract not avaliable

SIDe-O: A Toolbox for Surrogate Inductor Design and Optimization
F. Passos, E. Roca, R. Castro-López, F. V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2016
[abstract]
This paper presents SIDe-O, a CAD tool developed for the design and optimization of integrated inductors based on surrogate modeling techniques. This tool provides a solution to the problem of accurately and efficiently optimizing the design of inductors. The models used present less than 1% error when compared to EM simulations while reducing the simulation time by several orders of magnitude. Additionally, the tool provides the ability to create new surrogate models for different technologies and inductor topologies. The tool also allows the creation of an S-Parameter file that accurately describes the behavior of the inductor for a given range of frequencies, which can later be used in SPICE-like simulations.

Frequency-Dependent Parameterized Macromodeling of Integrated Inductors
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, Y. Ye, D. Spina and T. Dhaene
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2016
[abstract]
Integrated inductors are one of the most important passive elements in radio frequency design, due to their wide usage in wireless communication circuits. Typically, electromagnetic simulators are used in order to estimate the inductors performance with high accuracy as a function of the inductor geometrical and electrical parameters. Such simulations offer high-accuracy, but are computationally expensive and extremely time consuming. In this paper, a frequency-dependent parameterized macromodeling technique is adopted in order to overcome this problem. The proposed approach offers a high degree of automation, since it is based on sequential sampling algorithms, high efficiency and flexibility: a continuous frequency-domain model is given for each value of the chosen inductors parameters in the design space.

Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis
M. Paka, F.V. Fernandez and G. Dundar
Journal Paper - Integration, the VLSI Journal, vol. 55, pp 357-365, 2016
ELSEVIER    DOI: 10.1016/j.vlsi.2016.04.004    ISSN: 0167-9260    » doi
[abstract]
This paper focuses on the implementation of different techniques for the integration of yield estimation in the synthesis loop of analog integrated circuits (ICs). MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is considered to be a very powerful multi-objective optimization algorithm. For the consideration of yield, several techniques are discussed and three different yield-aware Pareto front (PF) generation techniques have been implemented on the MOEA/D optimizer. The implemented yield-aware PF techniques are compared by designing a fully-differential folded-cascode amplifier with different number of objectives. In order to embed the variation effects into the optimization loop, the statistical analysis of the circuit has been carried out by using a Quasi Monte Carlo (QMC) technique. The results suggest that especially two of these techniques look promising for high dimensional robust optimization of analog circuits.

Reliability simulation for analog ICs: Goals, solutions, and challenges
A. Toro-Frías, P. Martín-Lloret, J. Martin-Martinez, R. Castro-López, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernández
Journal Paper - Integration, the VLSI Journal, vol. 55, pp 341-348, 2016
ELSEVIER    DOI: 10.1016/j.vlsi.2016.05.002    ISSN: 0167-9260    » doi
[abstract]
The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.

Circuit Realization of the Synchronization of Two Chaotic Oscillators with Optimized Maximum Lyapunov Exponent
V.H. Carbajal-Gómez, E. Tlelo-Cuautle and F.V. Fernández
Book Chapter - Advances in Chaos Theory and Intelligent Control, STUDFUZZ, vol. 337, pp 627-651, 2016
SPRINGER    DOI: 10.1007/978-3-319-30340-6_26    ISBN: 978-3-319-30338-3    » doi
[abstract]
The modeling, simulation and circuit realization of the synchronization of two optimized multi-scroll chaotic oscillators is described herein. The case of study is the master-slave synchronization of two multi-scroll chaotic oscillators generating four to seven scrolls, based on saturated function series. The maximum Lyapunov exponent (MLE) of the chaotic oscillator is optimized by applying meta-heuristics. We show the behavior on the synchronization for chaotic oscillators with low and high MLEs, while the synchronization is performed by generalized Hamiltonian forms and observer approach from nonlinear control theory. Numerical simulation results are given for the chaotic oscillators with and without optimized MLEs, and for their master-slave synchronization. Finally, we show the good agreement between theoretical results, SPICE simulations and the experimental results when the whole synchronized system is implemented with commercially available operational amplifiers.

Accurate Synthesis of Integrated RF Passive Components using Surrogate Models
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernández
Conference - Design, Automation and Test in Europe DATE 2016
[abstract]
Passive components play a key role on the design of RF CMOS integrated circuits. Their synthesis, however, is still an unsolved problem due to the lack of accurate analytical models that can replace the computationally expensive electromagnetic simulations (EM). Both, physical-based and surrogate models have been reported that fail to accurately model the complete design space of inductors. Surrogate-assisted optimization techniques, where coarse models are locally enhanced during the inductor synthesis process by using new EM-simulated points to update the model, have been proposed, but either the efficiency is dramatically decreased due to the online EM simulations or the optimization may converge to suboptimal regions. In this paper, we present a new surrogate model, valid in the entire design space with less than 1% error when compared with EM simulations. This model can be generated offline, and, when embedded within an optimization algorithm, allows the synthesis of integrated inductors with high accuracy and high efficiency, reducing the synthesis time in three orders of magnitude.

Aplicación de algoritmos evolutivos multiobjectivo al diseño de circuitos integrados: criterios de detención
E. Roca, R. Castro-Lopez and F.V. Fernández
Conference - Congreso Español de Metaheurísticas, Algoritmos Evolutivos y Bioinspirados MAEB 2015
[abstract]
Abstract not avaliable

SMAS: A Generalized and Efficient Framework for Computationally Expensive Electronic Design Optimization Problems
B. Liu, F.V. Fernández, G. Gielen, A. Karkar, A. Yakovlev and V. Grout
Book Chapter - Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp 251-275, 2015
SPRINGER    DOI: 10.1007/978-3-319-19872-9_9    ISBN: 978-3-319-19871-2    » doi
[abstract]
Many electronic design automation (EDA) problems encounter computationally expensive simulations, making simulation-based optimization impractical for many popular synthesis methods. Not only are they computationally expensive, but some EDA problems also have dozens of design variables, tight constraints, and discrete landscapes. Few available computational intelligence (CI) methods can solve them effectively and efficiently. This chapter introduces a surrogate model-aware evolutionary search (SMAS) framework, which is able to use much fewer expensive exact evaluations with comparable or better solution quality. SMAS-based methods for mm-wave integrated circuit synthesis and network-on-chip parameter design optimization are proposed and are tested on several practical problems. Experimental results show that the developed EDA methods can obtain highly optimized designs within practical time limitations.

Application of Computational Intelligence Techniques to Maximize Unpredictability in Multiscroll Chaotic Oscillators
V.H. Carbajal-Gómez, E. Tlelo-Cuautle and F.V. Fernández
Book Chapter - Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp 59-81, 2015
SPRINGER     DOI: 10.1007/978-3-319-19872-9_3    ISBN: 978-3-319-19871-2    » doi
[abstract]
This chapter applies and compares three computational intelligence algorithms -genetic algorithm (GA), differential evolution (DE), and particle swarm optimization (PSO)- to maximize the positive Lyapunov exponent in a multiscroll chaotic oscillator based on a saturated nonlinear function series based on the modification of the standard settings of the coefficient values of the mathematical description, and taking into account the correct distribution of the scrolls drawing the phase-space diagram. The experimental results show that the DE and PSO algorithms help to maximize the positive Lyapunov exponent of truncated coefficients over the continuous spaces.

Computational Intelligence Techniques for Determining Optimal Performance Trade-Offs for RF Inductors
E. Roca, R. Castro-López, F.V. Fernández, R. González-Echevarría, J. Sieiro, N. Vidal and J.M. López-Villegas
Book Chapter - Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp 277-296, 2015
SPRINGER    DOI: 10.1007/978-3-319-19872-9_10    ISBN: 978-3-319-19871-2    » doi
[abstract]
The automatic synthesis of integrated inductors for radio frequency (RF) integrated circuits is one of the most challenging problems that RF designers have to face. In this chapter, computational intelligence techniques are applied to automatically obtain the optimal performance trade-offs of integrated inductors. A methodology is presented that combines a multi-objective evolutionary algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. The methodology is illustrated with a complete set of examples where different inductor trade-offs are obtained.

Integration of QMC Based Yield-Aware Pareto Front Techniques on MOEA/D for Robust Analog Synthesis
M. Pak, G. Dündar and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
[abstract]
This paper focuses on the implementation of different techniques for the integration of yield in the synthesis loop of analog ICs. Several algorithms have been developed for multi-objective optimization. Among these optimizers, MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is known as a powerful synthesizer. By using MOEA/D, some quality checks on practical designs have been realized in order to show the algorithm is well-suited for robust multi-objective optimization of analog circuits. Another issue that is considered is the inclusion of yield for obtaining robust PFs for analog sizing problems. Several techniques are discussed and three different yield-aware PF techniques have been implemented on MOEA/D. The implemented yield-aware PF techniques are compared by using a fully-differential folded-cascode amplifier. The results suggest that all three of these techniques look promising for high dimensional robust optimization of analog circuits.

A Fast and Accurate Reliability Simulation Method for Analog Circuits
A. Toro-Frias, R. Castro-Lopez, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
[abstract]
Reliability has become a critical challenge in integrated circuit design in today's CMOS technologies. Aging problems have been added to the well-known issues due to spatial variations that are caused by imperfections in the fabrication process. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers (HC) cause a time-dependent variability that is added to the spatial variability. In addition, the BTI presents a stochastic behaviour, which may cause, for instance, time-varying mismatch. In this work, a model based on the physics of this phenomenon is implemented to accurately know its impact on the circuit performances. This method is focused on the analysis of analog circuits, taking into account the impact of both temporal and spatial variability. An effient simulation flow is implemented to evaluate the circuit performance at any instant of the circuit lifetime.

Transformation conditions of performance fronts of operational amplifiers
E. Roca, R. Castro-Lopez, M. Velasco-Jiménez and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
[abstract]
Pareto fronts of circuits whose performance depend on other circuits that they are connected to must be updated for each interconnection conditions. This paper reports, for the first time, the conditions for which a transformation without loss of information is guaranteed.

Surrogate Modeling and Optimization of Inductor Performances using Kriging functions
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
[abstract]
Integrated inductors are one of the most important passive elements in RF circuits. However, time-consuming simulations, such as electromagnetic simulations, have to be used to evaluate their performances with high accuracy. In order to overcome this problem, analytical models can be used. In this paper, a surrogate model based on Kriging functions is presented that accurately predicts the performance parameters of integrated inductors. The different approaches followed to obtain the model are presented. Finally, the model is linked to an evolutionary algorithm to optimize inductor performances.

A simulation methodology for the reliability-aware design of analog circuits
A. Toro, R. Castro-López, E. Roca, F.V. Fernández, J. Martín-Martinez, R. Rodriguez and M. Nafria
Conference - International Mixed-Signals Testing Workshop IMSTW 2015
[abstract]
With the scale of integration of modern transistors entering the atomic size and an increase of the gate-oxide field, reliability of electronic circuits is today more demanding than ever. Both spatial (i.e., process) variations and time-dependent (i.e., aging) variations dramatically reduce the yield and shortens the circuit lifetime, which prompt for reliability aspects to be considered in the design flow in order to attain resilient circuits featuring longer lifetimes. Aging effects such as as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) should be included just as well as process variations are.

A two-step layout-in-the-loop design automation tool
G. Berkol, A. Unutulmaz, E. Afacan, G. Dundar, F.V. Fernandez, A.E. Pusane and F. Baskaya
Conference - IEEE International New Circuits and Systems Conference NEWCAS 2015
[abstract]
There exists circuit sizing and layout generation tools for analog circuit designers to speed up the design process. Generally, these tools handle the circuit sizing and the layout generation processes separately, which may cause performance failures and laborious redesign iterations. Recently, new tools have been developed which simultaneously take care of circuit sizing and layout generation. However, they either suffer from long run times or limited accuracy of the utilized parasitic model. This paper presents a complete layout-aware design automation tool for analog circuits. The proposed tool combines a simulation-based circuit sizing tool with a template-based layout generation tool. The layout-induced parasitics are automatically extracted via a commercially available extractor. To reduce the run time cost originating from parasitic extraction, a two step methodology is followed, where infeasible solutions are prohibited from costly extraction process.

Design Space Exploration using Hierarchical Composition of Performance Models
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2015
[abstract]
Bottom-up synthesis approaches based on the hierarchical composition of performance models have been proposed as a promising alternative to conventional top-down hierarchical synthesis approaches. This paper discusses problems related to the context-dependence of performance models and proposes possible solutions. Techniques for the composition of multi-dimensional performance models so that the efficiency of the design space exploration is maximized are also discussed. An active filter is used to demonstrate the accuracy and efficiency of the techniques discussed here.

On the convex formulation of area for slicing floorplans
A. Unutulmaz, G. Dündar and F.V. Fernández
Journal Paper - Integration, the VLSI Journal, vol. 50, pp 74-80, 2015
ELSEVIER    DOI: 10.1016/j.vlsi.2015.01.008    ISSN: 0167-9260    » doi
[abstract]
Abstract In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with continuous convex functions of the width (height). It is proved that the area of a compact slicing floorplan is a convex function of its width (height). The convexity is shown for the cases with and without dead (empty) space. This feature can be exploited to efficiently optimize the dimensions of layout components with multiple variants, without enumerating all possible combinations. Layout of a voltage-doubler circuit is used to quantitatively verify the proof.

Physical vs. Surrogate Models of Passive RF Devices
F. Passos, M. Kotti, R. González-Echevarría, M.H. Fino, M. Fakhfakh, E. Roca, R.Castro-López and F.V. Fernández
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2015
[abstract]
The accuracy of high-frequency models of passive RF devices, e.g., inductors or transformers, presents one of the most challenging problems for RF integrated circuits. Accuracy limitations lead RF designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. The first one is based on the segmented model approach, in which each device segment is characterized with a lumped element model. The second technique is based on the generation of surrogate models from the electromagnetic simulation of a set of device samples. Different modeling strategies (frequency separation, filtering according to self-resonance frequency, etc.) will be considered. Efficiency and accuracy of both, physical and surrogate, modeling techniques will be compared using a Si process technology.

Statistical analysis of active and passive RF devices
M. Pak, A.E. Yarimbiyik, G. Dundar and F. Fernandez
Conference - Int. Conf. on Advanced Semiconductor Devices & Microsystems ASDAM 2014
[abstract]
Since statistical circuit analysis are vital for robust circuit designs, different techniques like Monte-Carlo or response surface models have been developed. These tools are adapted with passive and active devices with process variations in order to statistically analyse ICs. In this paper, a similar idea has been applied for statistical analysis at device level, instead of circuits, for some RF components. By using the physical variations of the fabrication environment, process and device simulations can be realized; thus the electrical variations of the devices can be obtained. This technique is expected to shorten time-to-market in different ways. To illustrate the idea, analysis of a 0.25μm SiGe transistor and 1nH spiral inductor have been realized.

Hierarchical Composition of Pareto-Optimal Fronts of Analog Circuits: Implementation Issues
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2014
[abstract]
The use of Pareto-optimal fronts (PoFs) is becoming key in the development of new hierarchical design methodologies that aim to reduce the bottleneck in the design of analog and mixed-signal systems caused by the design of the analog components. An important aspect of these new methodologies, the hierarchical composition of lower-level PoFs, has received little attention in the literature. This composition presents two key issues. The first issue is the context-dependent performances of analog circuits, which obligate to re-evaluate the PoFs of these circuits when their surrounding circuitry changes. The second issue is related to how multi-dimensional low-level PoFs are used when generating the PoFs of high-level blocks so that the efficiency of the design space exploration is not affected. This work presents new mechanisms that can be used to solve both issues. The generation of the performance model of an active filter by hierarchical composition of previously generated PoFs of operational amplifiers is used to demonstrate the validity of the approaches presented here.

Characterization of Random Telegraph Noise and its impact on reliability of SRAM sense amplifiers
J. Martin-Martinez, J. Diaz, R. Rodriguez, M. Nafria, X. Aymerich, E. Roca, F.V. Fernandez and A. Rubio
Conference - European Workshop on CMOS Variability VARI 2014
[abstract]
A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate the RTN-related variation of the device drain current. The RTN parameters obtained from experimental traces are used to simulate the impact of RTN in the drain current of pMOS transistors in SRAM voltage sense amplifiers. The results show that RTN can lead to read errors of the stored data.

Maximizing Lyapunov Exponents in a Chaotic Oscillator by Applying Differential Evolution
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, F.V. Fernandez, L.G. de la Fraga and C. Sanchez-Lopez
Journal Paper - International Journal of Nonlinear Sciences and Numerical Simulation, vol. 15, no. 1, pp. 11-17, 2014
DE GRUYTER    DOI: 10.1515/ijnsns-2011-0014    ISSN: 1565-1339    » doi
[abstract]
This paper shows the application of the heuristic Differential Evolution (DE) algorithm to maximize the positive Lyapunov exponent in a third-order multi-scroll chaotic oscillator. The case of study is the saturated nonlinear function series-based chaotic oscillator. The positive Lyapunov exponent is computed for a 4-scrolls chaotic oscillator by varying the coefficients of the dynamical system (a, b, c, d(1)), in the range [0.001..1.000]. The experiments are performed and compared executing DE and a simple Genetic algorithm. The results show that DE algorithm is quite suitable to maximize the positive Lyapunov exponent of truncated coefficients over the continuous parameter spaces, because statistical studies show a small standard deviation. The comparison of the phase space diagrams of non-optimized and optimized chaotic oscillators show that for a low value of the positive Lyapunov exponent the attractor is well defined, while for its maximum value the attractor is not well appreciated, but the higher value of the exponent increases the unpredictability grade of the chaotic system.

Automated generation of the optimal performance trade-offs of integrated inductors
R. González-Echevarría, R. Castro-López, E. Roca, F.V. Fernández, J. Sieiro, N.Vidal and J.M. López-Villegas
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 8, pp. 1269-1273, 2014
IEEE    DOI: 10.1109/TCAD.2014.2316092    ISSN: 0278-0070    » doi
[abstract]
In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.

Model-based hierarchical optimization strategies for analog design automation
E. Afacan, G. Dundar, F. Baskaya and F.V. Fernández-Fernández
Conference - Design Automation and Test in Europe DATE 2014
[abstract]
The design of complex analog circuits by using flat optimization-based approaches is inefficient, even impossible, due to the high number of design variables and the growth of the cost of performance evaluation with the circuit size. Over the past two decades, top-down hierarchical design approaches have been developed and applied. They are based on hierarchical circuit decomposition and specification transmission from top-level to lower level blocks. However, such specification transmission is usually performed with little knowledge on the feasibility of the specifications, leading, therefore, to costly redesign iterations. Even if the specification transmission is successful, there is no guarantee that it is optimal in terms of e.g., power consumption or area occupation. To palliate this problem, two novel model-based hierarchical synthesis methods are proposed in this paper: ModelBased Hierarchical Optimization (MBHO) and Improved ModelBased Hierarchical Optimization (IMBHO). They are based on the concurrent design at higher and lower hierarchical levels and appropriate communication between the different processes. Experimental results on a filter example comparing the new approaches and the conventional top-down design approach are provided.

Automated design of analog and high-frequency circuits: a computational intelligence approach
B. Liu, G. Gielen and F.V. Fernandez-Fernandez
Book - SCI, vol. 501, 235 p, 2014
SPRINGER    ISBN: 978-3-642-39161-3    » link
[abstract]
Computational intelligence techniques are becoming more and more important for automated problem solving nowadays. Due to the growing complexity of industrial applications and the increasingly tight time-to-market requirements, the time available for thorough problem analysis and development of tailored solution methods is decreasing. There is no doubt that this trend will continue in the foreseeable future. Hence, it is not surprising that robust and general automated problem solving methods with satisfactory performance are needed.

Template coding with LDS and applications of LDS in EDA
A. Unutulmaz, G. Dundar and F.V. Fernandez-Fernandez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 78, no. 1, pp 137-151, 2014
SPRINGER    DOI: 10.1007/s10470-013-0213-9    ISSN: 0925-1030    » doi
[abstract]
This paper presents the layout description script (LDS), which is a domain specific language intended to code layout templates to be used for layout-aware circuit synthesis. LDS supports both sequential and constraint programming and is suitable for both manual coding and automatic code generation. LDS is compared with previous approaches related to layout description. Code samples are given for alignment, abutment, symmetry, and similar constraints. Also, implementation of the LDS compiler is discussed and a methodology for handling complex constraints is presented. Due to its support for constraint programming, it is possible to constrain topological representations and even combine them. It is also possible to combine and constrain placement and routing in an LDS template. Finally, a capture tool has been implemented. This tool is designed to extract a template from an expert-drawn layout. Capture converts a data structure extracted through a guided user interface into a template. This tool highlights the compatibility of LDS with electronic design automation.

Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors
M. Kotti, R. González-Echevarría, F.V. Fernández, E. Roca, J. Sieiro, R. Castro-López, M. Fakhfakh and J.M. López-Villegas
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 78, no. 1, pp 87-97, 2014
SPRINGER    DOI: 10.1007/s10470-013-0230-8    ISSN: 0925-1030    » doi
[abstract]
Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-μm CMOS technology are provided.

Introduction to the special issue on SMACD 2012
F.V. Fernández, E. Roca and R. Castro-López
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 78, no. 1, pp 61-63, 2014
SPRINGER    DOI: 10.1007/s10470-013-0227-3    ISSN: 0925-1030    » doi
[abstract]
Abstract not avaliable

Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference - Design Automation and Test in Europe DATE 2014
[abstract]
Emerging hierarchical design methodologies based on the use of Pareto-optimal fronts (PoFs) are promising candidates to reduce the bottleneck in the design of analog circuits. However, little work has been reported about how to transmit the information provided by the PoFs of low hierarchical level blocks through the hierarchy to compose the performance models of higher-level blocks. This composition actually poses several problems such as the dependence of the PoF performances on the surrounding circuitry and the complexity of dealing with multi-dimensional PoFs in order to explore more efficiently the design space. To deal with these problems, this paper proposes new mechanisms to represent and select candidate solutions from multi-dimensional PoFs that are transformed to the changing operating conditions enforced by the surrounding circuitry. These mechanisms are demonstrated with the generation of the performance model of an active filter by composing previously generated PoFs of operational amplifiers.

A Wideband Lumped-Element Model for Integrated Spiral Inductors
F. Passos, M.H. Fino, E. Roca, R. González-Echevarría and F.V. Fernández
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2013
[abstract]
Abstract not available

Paving the way for new sizing approaches of analog and RF circuits
F.V. Fernández
Conference - IEEE/ACM Int. Workshop on Design Automation for Analog and Mixed-Signal Circuits 2013
[abstract]
Abstract not available

Optimizing the positive Lyapunov exponent in multi-scroll chaotic oscillators with differential evolution algorithm
V.H. Carbajal-Gómez, E. Tlelo-Cuautle and F.V. Fernández
Journal Paper - Applied Mathematics and Computation, vol. 219, no. 15, pp 8163-8168, 2013
ELSEVIER    DOI: 10.1016/j.amc.2013.01.072    ISSN: 0096-3003    » doi
[abstract]
We introduce the application of the differential evolution algorithm (DE) to optimize the positive Lyapunov exponent in a multi-scroll chaotic oscillator based on saturated nonlinear function series. The positive Lyapunov exponent is optimized from two to nine scrolls by sweeping the coefficients of the chaotic oscillator. In this article, the case of study has four coefficients, so that the feasible solutions for a,b,c, and d1, are used to generate the bifurcation diagrams for the cases from two to nine scrolls taking c as the bifurcation parameter to demonstrate that high values of the positive Lyapunov exponent can be guaranteed when a,b,d1 take values higher than 0.7, while c takes values lower than 0.3.

Lumped Element Model for Arbitrarily Shaped Integrated Inductors - A Statistical Analysis
F. Passos, M.H. Fino, E. Roca, R. González-Echevarría and F.V. Fernández
Conference - IEEE Int. Conf. on Microwaves, Communications, Antennas and Electronic Systems COMCAS 2013
[abstract]
In this paper a model based in lumped elements is presented for the haracterization of integrated inductors. The model allows the modelling of integrated inductors for a wide range of frequencies and different inductor topologies, thus granting the evaluation of important design parameters such as inductance, quality factor and self-resonance frequency. The model will be explained in detail and compared against electromagnetic simulations for a 0.35μm and 0.13μm CMOS technologies. Results for square and octagonal geometries are presented. A statistic analysis is also presented for the octagonal topology in order to validate the model over a wide range of geometric variables in 0.35μm CMOS technology.

Behavioral modeling of SNFS for synthesizing multi-scroll chaotic attractors
C. Sánchez-López, F.V. Fernández, F.V., V.H. Carbajal-Gómez, E. Tlelo-Cuautle, J. Mendoza-López
Journal Paper - International Journal of Nonlinear Sciences and Numerical Simulation, vol. 14, no. 7-8, pp 463-469, 2013
DE GRUYTER    DOI: 10.1515/ijnsns-2011-0052    ISSN: 1565-1339    » doi
[abstract]
Existing models of continuous nonlinear functions used for generating multi-scroll chaotic attractors are based on a piece-wise linear (PWL) approach. These models, although relatively easy to build, do not include any information related to the performance parameters of active devices, in the context of a possible physical implementation. This is a serious drawback, since the use of a PWL model introduces a level of inaccuracy into a numerical analysis which is more evident when numerical and experimental results are compared. This paper proposes a methodology to generate the behavioral model of continuous nonlinear functions, but unlike PWL approaches, real physical active device parameters are herein taken into account. In particular, we generate the behavioral model of a nonlinear function called saturated nonlinear function series (SNFS), but in general, the proposed approach can be used to generate the behavioral model of other continuous nonlinear functions. Our results indicate that the proposed approach yields a more realistic and accurate behavioral model than PWL models. As a consequence, not only the generation of chaotic attractors is more precise, but the metrics used to measure the complexity of a chaotic system can also be better predicted. Numerical and electrical simulation results at both domains, phase and time, illustrate the benefits of the new proposed model.

Area optimization on fixed analog floorplans using convex area functions
A. Unutulmaz, G. Dundar and F.V. Fernández
Conference - Design Automation and Test in Europe Conference DATE 2013
[abstract]
A methodology to optimize the area of a fixed nonslicing floorplan is presented in this paper. Areas of transistors, capacitors and resistors are formulated as convex functions and area is minimized by solving a sequence of convex problems. The methodology is practical even with many components and variants. Moreover symmetry constraints are satisfied during optimization.

An efficient evolutionary algorithm for chance-constrained bi-objective stochastic optimization
B. Liu, Q. Zhang, F.V. Fernandez and G.G.E. Gielen
Journal Paper - IEEE Transactions on Evolutionary Computation, vol. 17 , no. 6, 2013
IEEE    DOI: 10.1109/TEVC.2013.2244898    ISSN: 1089-778X    » doi
[abstract]
In engineering design and manufacturing optimization, the trade-off between a quality performance metric and the probability of satisfying all performance specifications (yield) of a product naturally leads to a chance-constrained bi-objective stochastic optimization problem (CBSOP). A new method, called MOOLP (multi-objective uncertain optimization with ordinal optimization (OO)), Latin supercube sampling and parallel computation), is proposed in this paper for dealing with the CBSOP. This proposed method consists of a constraint satisfaction phase and an objective optimization phase. In its constraint satisfaction phase, by using the OO technique, an adequate number of samples are allocated to promising solutions, and the number of unnecessary MC simulations for noncritical solutions can be reduced. This can achieve more than five times speed enhancement compared to the application of using an equal number of samples for each candidate solution. In its MOEA/D-based objective optimization phase, by using LSS, more than five times speed enhancement can be achieved with the same estimation accuracy compared to primitive MC simulation. Parallel computation is also used for speedup. A real-world problem of the bi-objective variation-aware sizing for an analog integrated circuit is used in this paper as a practical application. The experiments clearly demonstrate the advantages of MOOLP.

Design of analog circuits through symbolic analysis
M. Fakhfakh (Ed.), E. Tlelo-Cuautle and F.V. Fernandez-Fernandez (Co-Eds.)
Book - 477 p, 2012
BENTHAM    ISBN: 978-1-60805-425-1    » link
[abstract]
This edited book provides an overview of the current state of the art in symbolic analysis. The editors have compiled chapters from the key contributors to the field of symbolic analysis. These chapters neatly describe the latest results in terms of algorithms as well as applications of symbolic analysis techniques for analog circuits. Recent algorithmic improvements highlight the potential of today´s symbolic analysis methods, both in terms of circuit complexity and of circuit characteristics that can be analyzed. The second part of the book presents the wide span of applications that utilize symbolic analysis, ranging from behavioral and performance modeling over design centering and fault diagnosis to automated design and system architectural exploration. These chapters clearly demonstrate the potential of symbolic analysis for analog circuits, in complement to or in combination with numerical simulation techniques.

Systematic Generation of Performance Models of Reconfigurable Analog Circuits
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
[abstract]
In this work, a systematic technique to generate performance models of reconfigurable analog circuits is presented. The performance models are obtained in the form of multi-mode Pareto-optimal fronts (mm-PoFs), a new type of Pareto-optimal front (PoF) that characterizes the set of different performances that reconfigurable circuits can attain. The technique is based on the use of an evolutionary algorithm (EA) that acts as an optimizer, and the simulator HSPICE to measure the circuit performances. The use of this technique will be illustrated for a wireless multistandard problem, where a reconfigurable op-amp will be considered.

Symbolic Pole/Zero Analysis
F.V. Fernández, C. Sánchez-López, R. Castro-López and E. Roca
Book Chapter - Design of Analog Circuits through Symbolic Analysis, pp 287-304, 2012
BENTHAM    DOI: 10.2174/978160805095611201010287    ISBN: 978-1-60805-425-1    » doi
[abstract]
Extraction of pole/zero expressions as a function of circuit parameters has traditionally been an essential tool for designers. In this Chapter, the main specific techniques for symbolic pole/zero extraction are described and their pros and cons are discussed. The application of the different techniques is illustrated with experimental results on practical circuits.

Surrogate models of Pareto-optimal planar inductors
M. Kotti, R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, M. Fakhfakh, J. Sieiro and J.M. López-Villegas
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
[abstract]
Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is obtained by embedding an electromagnetic simulator into a multi-objective optimization tool. Then, starting from the obtained optimal samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35 μm CMOS technology are provided.

New approaches to bridge the design gap of analog and RF circuits
F.V. Fernández, E. Roca and R. Castro-López
Conference - International Conference on Analog VLSI Circuits AVIC 2012
[abstract]
The increasing gap between IC complexity and the capacity to deal with it in the design process is worrisome. Design productivity has and must be improved in this sense. The picture is even worse for analog, mixed-signal and radiofrequency circuits due to the lesser development of commercial CAD tools and methodologies with respect to their digital counterparts. From the several directions proposed to bridge this gap, this talk will focus on two of them: improving existing hierarchical synthesis methods and reducing the iterations between separate design stages.

LDS based tools to ease template construction
A. Unutulmaz, G. Dundar and F.V. Fernández-Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
[abstract]
Layout Description Script (LDS) is a domain specific language (DSL) intended to describe analog layouts. This paper introduces an LDS based tool, Capture, and an add-on, LDS Analyzer, for LDS. Capture aims to convert layout images into layout templates. Components of a layout are extracted with this tool and a template is synthesized from the extracted data. LDS Analyzer is an enhanced LDS parser. Analyzer investigates an LDS statement and conducts either simple parsing or enhanced parsing which make use of symbolic variables.

Approximation Techniques in Symbolic Circuit Analysis
F.V. Fernández, C. Sánchez-López, R. Castro-López and E. Roca
Book Chapter - Design of Analog Circuits through Symbolic Analysis, pp 173-201, 2012
BENTHAM    DOI: 10.2174/978160805095611201010173    ISBN: 978-1-60805-425-1    » doi
[abstract]
Symbolic circuit analysis suffers from the exponential growth of expression complexity with circuit size. Therefore, either if the symbolic expressions are used for gaining insight into circuit operation or for repetitive computer-based evaluations, simplification becomes mandatory. This chapter reviews the different existing techniques for symbolic expression simplification, classifying them into three categories according to the step at which the simplification is performed: on the circuit equations, during the solution of the circuit equations or after the circuit equations have been solved. Pros and cons of each approach are discussed.

An Automated Layout-Aware Design Flow
A. Toro-Frías, R. Castro-López, E. Roca and F.V. Fernández
Conference - Int. Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
[abstract]
In analog integrated circuit design, it has always been necessary to improve the designer's productivity. The iterations between the electrical and physical synthesis, required to correct deviations due to parasitics, do degrade that productivity. The inclusion of the physical implementation directly within the electrical synthesis process, would in principle remove many or all of these iterations. This paper presents a fully-automated layout-aware design flow, whose key aspects are: (1) it uses commercially available tools and platforms to attain a highly integrated solution, (2) it provides solutions in the form of Pareto-optimal fronts, which represent the circuit's valuable trade-offs (and can be used in modern design flows), and (3) it allows including the impact of parasitics right into the fronts. This paper details the necessary tools and their integration for automation of the design flow and provides several examples of its use.

A fully automated design flow for planar inductors
R. González-Echevarría, R. Castro-López, E. Roca, F.V. Fernández, J.M. López-Villegas and J. Sieiro
Conference - Int. Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
[abstract]
Integrated inductors performances are difficult to model due to the parasitic effects present at high frequencies. Typically, RF designers use electromagnetic simulation during the design flow to tune their circuits until all designs requirements are fulfilled or use the set of, not always conveniently tuned, inductors provided by the foundries. In this paper, a multi-objective optimization algorithm is combined with a full-wave electromagnetic evaluator to obtain a tool for synthesis of inductors with optimum performance trade-offs. The automation of layout generation and simulation tasks are described in details.

Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
E. Roca-Moreno, M. Velasco-Jiménez, R. Castro-López and F.V. Fernández-Fernández
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 73, no. 1, pp 65-76, 2012
SPRINGER    DOI: 10.1007/s10470-011-9785-4    ISSN: 1573-1979    » doi
[abstract]
The use of Pareto-optimal performance fronts in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of traditional design methodologies. However, most techniques to generate the fronts reported so far neglect the effect that the surrounding circuitry (such as the load impedance) has on the Pareto-front, thereby making it only realistic for the context where the front was generated. This strongly limits the use of the Pareto front because of the strong dependence between the key performances of an analog circuit and its surrounding circuitry, but, more importantly, because this circuitry remains unknown until the Pareto-optimal front is being used. Since performance front generation is a costly process, this paper proposes that performance fronts for a new context of use of a given circuit can be obtained from fronts that were previously generated under some different conditions. Towards this goal, a transformation methodology for performance objectives of operational amplifiers has been developed. Experimental results for a folded-cascode and a Miller-compensated operational amplifiers show that this is a promising approach to reuse the fronts in multiple contexts.

Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian process surrogate model assisted evolutionary algorithms
B. Liu, Q. Zhang, F.V. Fernández and G. Gielen
Conference - IEEE Congress on Evolutionary Computation CEC 2012
[abstract]
Surrogate model assisted evolutionary algorithms are receiving much attention for the solution of optimization problems with computationally expensive function evaluations. For small scale problems, the use of a Gaussian Process surrogate model and prescreening methods has proven to be effective. However, each commonly used prescreening method is only suitable for some types of problems, and the proper prescreening method for an unknown problem cannot be stated beforehand. In this paper, the four existing prescreening methods are analyzed and a new method, called self-adaptive lower confidence bound (ALCB), is proposed. The extent of rewarding the prediction uncertainty is adjusted on line based on the density of samples in a local area and the function properties. The exploration and exploitation ability of prescreening can thus be better balanced. Experimental results on benchmark problems show that ALCB has two main advantages: (1) it is more general for different problem landscapes than any of the four existing prescreening methods; (2) it typically can achieve the best result among all available prescreening methods.

Behavioral Modeling of Mixed-Mode Integrated Circuits
E. Tlelo-Cuautle, E. Martínez-Romero, C. Sánchez-López, F.V. Fernández, Sheldon X.-D. Tan, Peng Li and M. Fakhfakh
Book Chapter - Advances in Analog Circuits, pp 85-108, 2011
INTECH    DOI: 10.5772/15864    ISBN: 978-953-307-323-1    » doi
[abstract]
An approach to the symbolic noise analysis on linear or linearized analog circuits at the transistor level of abstraction is presented. A brief exposition on the signal-path approach into analog circuits working in voltage-mode and current-mode, which are modeled with nullors, is given. Therefore, symbolic noise parameters, such as: V2n,out, V2n,in, NFv, I2n,out, I2n,in and NFi, of analog circuits are computed, where all the noise sources associated to MOS transistors and passive elements are assumed to be uncorrelated. Two examples are introduced to illustrate the potentiality of the approach proposed. The first example is a voltage-mode analog circuit, where the signal-path is approached by using the nullator concept and its properties. On the contrary, in the second example, a current-mode analog circuit is considered where the signal-path is approached by using the norator concept along with its properties.

Closing the gap between electrical and physical design: the layout-aware solution
R. Castro-López, E. Roca and F.V. Fernández
Book Chapter - Analog layout synthesis. A Survey of Topological Approaches, pp 243-268, 2011
SPRINGER    DOI: 10.1007/978-1-4419-6932-3_6    ISBN: 978-1-4419-6931-6    » doi
[abstract]
Iterations between separate phases in any procedural design process, usually a by-product of unexpected (or, simply, very complex to consider) adverse effects, clearly play against any time-to-market requirements. In analog integrated circuit (IC) design, going back and forth between electrical and physical synthe- sis to counterbalance layout-induced performance degradations needs to be thus avoided as much as possible. One possible solution involves the integration of the 1 traditionally separated electrical and physical synthesis phases, by including layout- induced effects, in the form of layout parasitics, right into the electrical synthesis phase, in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of the occu- pied area or fulfillment of certain layout aspect ratio, among others), whose effects on the resulting parasitics are not usually considered during electrical synthesis. In this chapter, a layout-aware solution that tackles both geometric and parasitic-aware electrical synthesis is proposed. This technique uses a combination of simulation- based optimization, procedural layout generation, exhaustive geometric evaluation algorithms, and several mechanisms for parasitic estimation. Thanks to the nature of this combination, the solution benefits from, and also fosters, reuse of analog intellectual property (IP) blocks. Several detailed design examples are provided.

A template router
A. Unutulmaz, G. Dundar and F.V. Fernandez
Conference - European Conference on Circuit Theory and Design ECCTD 2011
[abstract]
Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine these approaches. However, a new type of router is required for such a combination; namely, the template router. This paper presents a template router and discusses how routing is coded and how this code is generated using the well known A* Algorithm. © 2011 IEEE.

Layout-aware Pareto fronts of electronic circuits
A. Toro-Frías, R. Castro-López, E. Roca and F.V. Fernández
Conference - European Conference on Circuit Theory and Design ECCTD 2011
[abstract]
Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such as the yield or the reconfiguration capabilities. However, the effect of layout parasitics is the factor that has been missing in the literature: the accuracy may be seriously degraded by layout parasitics not considered during the front generation. In this paper, we present a technique to generate layout-aware Pareto fronts that accurately accounts for the impact of both geometry and parasitics. © 2011 IEEE.

LDS - A description script for layout templates
A. Unutulmaz, G. Dundar and F.V. Fernandez
Conference - European Conference on Circuit Theory and Design ECCTD 2011
[abstract]
In this paper a simple declarative language to define layout templates of analog circuits, named Layout Description Script (LDS), is introduced. In contrast to sequential description languages, coding constraints of a template is very easy with LDS. A methodology based on linear programming (LP) is presented to instantiate a layout from a set of LDS statements. Due to the LP formulation, area and wire length minimization is also applied during instantiation. Also a methodology to extract LDS from a pre-drawn layout is presented. These methodologies and the description language itself are illustrated by synthesizing an amplifier. The proposed methodology is able to synthesize a layout in a few seconds. © 2011 IEEE.

Pathological element-based active device models and their application to symbolic analysis
C. Sánchez-López, F.V. Fernández, E. Tlelo-Cuautle and S.X. Tan
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, no. 6, pp 1382-1395, 2011
IEEE    DOI: 10.1109/TCSI.2010.2097696    ISSN: 1549-8328    » doi
[abstract]
This paper proposes new pathological element-based active device models which can be used in analysis tasks of linear(ized) analog circuits. Nullators and norators along with the voltage mirror-current mirror (VM-CM) pair (collectively known as pathological elements) are used to model the behavior of active devices in voltage-, current-, and mixed-mode, also considering parasitic elements. Since analog circuits are transformed to nullor-based equivalent circuits or VM-CM pairs or as a combination of both, standard nodal analysis can be used to formulate the admittance matrix. We present a formulation method in order to build the nodal admittance (NA) matrix of nullor-equivalent circuits, where the order of the matrix is given by the number of nodes minus the number of nullors. Since pathological elements are used to model the behavior of active devices, we introduce a more efficient formulation method in order to compute small-signal characteristics of pathological element-based equivalent circuits, where the order of the NA matrix is given by the number of nodes minus the number of pathological elements. Examples are discussed in order to illustrate the potential of the proposed pathological element-based active device models and the new formulation method in performing symbolic analysis of analog circuits. The improved formulation method is compared with traditional formulation methods, showing that the NA matrix is more compact and the generation of nonzero coefficients is reduced. As a consequence, the proposed formulation method is the most efficient one reported so far, since the CPU time and memory consumption is reduced when recursive determinant-expansion techniques are used to solve the NA matrix.

Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques
B. Liu, F.V. Fernández and G.G.E. Gielen
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 6, pp 793-805, 2011
IEEE    DOI: 10.1109/TCAD.2011.2106850    ISSN: 0278-0070    » doi
[abstract]
In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires many yield estimations, practical. In this paper, techniques inspired by computational intelligence are used to speed up yield optimization without sacrificing accuracy. A new sampling-based yield optimization approach, which determines the device sizes to optimize yield, is presented, called the ordinal optimization (OO)-based random-scale differential evolution (ORDE) algorithm. By proposing a two-stage estimation flow and introducing the OO technique in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed evolutionary algorithm that uses differential evolution for global search and a random-scale mutation operator for fine tunings, the convergence speed of the yield optimization can be enhanced significantly. With the same accuracy, the resulting ORDE algorithm can achieve approximately a tenfold improvement in computational effort compared to an improved MC-based yield optimization algorithm integrating the infeasible sampling and Latin-hypercube sampling techniques. Furthermore, ORDE is extended from plain yield optimization to process-variation-aware single-objective circuit sizing.

Load-Independent Characterization of Trade-Off Fronts for Operational Amplifiers
E. Roca, M. Velasco-Jiménez, R.l Castro-López and F.V. Fernández
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2010
[abstract]
In emerging design methodologies for analog integrated circuits, the use of performance trade-off fronts, also known as Pareto fronts, is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the front neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We will address this problem by proposing a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a commonly used circuit, the operational amplifier, and experimental results show that this is a promising approach to solve the issue.

A Pareto-based systematic design technique for reconfigurable analog circuits using an evolutionary optimization algorithm
M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2010
[abstract]
Abstract not avaliable

A bottom-up approach to the systematic design of LNAs using evolutionary optimization
C. Sánchez-López, R. Castro-López, E. Roca, F.V. Fernández, R. González-Echevarría, J. Esteban-Muller, J.M. López-Villegas, J. Sieiro and N. Vidal
Conference - International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010
[abstract]
A systematic design methodology for low-noise amplifiers (LNAs) is introduced. This methodology follows a bottom-up approach that employs a multi-objective evolutionary optimization algorithm, which is used at two levels. First, it is used to generate Pareto-based performance models for integrated planar inductors. To do so, an electromagnetic simulator that takes into account the inductor's layout, thus providing highly accurate performance evaluations, is coupled to the optimizer. Unlike foundry-provided inductor libraries, these Pareto-based models offer a detailed insight of the trade-offs between inductance, quality factor and area. Afterwards the Pareto-based models for the inductors are used as design variables to generate the LNA Pareto surface, thus providing highly accurate performance trade-offs of the LNA.

Multi-objective performance optimization of planar inductors
J. Esteban-Muller, R. González-Echevarría, C. Sánchez-López, E. Roca, R. Castro-López, F.V. Fernández, J.M. López-Villegas, J. Sieiro and N. Vidal
Conference - Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010
[abstract]
Inductors play an essential role in the design of RF circuits. The parasitic effects plaguing integrated planar inductors require an accurate modeling and the careful exploration of their performance trade-offs. In this paper, a multi-objective performance modeling technique of planar inductors is presented, that supports both top-down and bottom-up design of RF circuits. ©2010 IEEE.

Context-independent performance modeling of operational amplifiers using Pareto fronts
E. Roca, M. Velasco-Jiménez, R. Castro-López and F.V. Fernández
Conference - Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2010
[abstract]
The use of performance trade-off fronts, also known as Pareto fronts, in emerging design methodologies for analog integrated circuits is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the fronts neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We propose a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a Miller operational amplifier, and experimental results show that this is a promising approach to solve the issue. ©2010 IEEE.

An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique
B. Liu, F.V. Fernández and G. Gielen
Conference - Design, Automation and Test in Europe DATE 2010
[abstract]
Monte-Carlo (MC) simulation is still the most commonly used technique for yield estimation of analog integrated circuits, because of its generality and accuracy. However, although some speed acceleration methods for MC simulation have been proposed, their efficiency is not high enough for MC-based yield optimization (determines optimal device sizes and optimizes yield at the same time), which requires repeated yield calculations. In this paper, a new sampling-based yield optimization approach is presented, called the Memetic Ordinal Optimization (OO)-based Hybrid Evolutionary Constrained Optimization (MOHECO) algorithm, which significantly enhances the efficiency for yield optimization while maintaining the high accuracy and generality of MC simulation. By proposing a two-stage estimation flow and introducing the OO technology in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed memetic search operators, the convergence speed of the algorithm can considerably be enhanced. With the same accuracy, the resulting MOHECO algorithm can achieve yield optimization by approximately 7 times less computational effort compared to a state-of-the-art MC-based algorithm integrating the acceptance sampling (AS) plus the Latin-hypercube sampling (LHS) techniques. Experiments and comparisons in 0.35 um and 90nm CMOS technologies show that MOHECO presents important advantages in terms of accuracy and efficiency. © 2010 EDAA.

Generalized admittance matrix models of OTRAs and COAs
C. Sánchez-López, F.V. Fernández and E. Tlelo-Cuautle
Journal Paper - Microelectronics Journal, vol. 41, no. 8, pp 502-505, 2010
ELSEVIER    DOI: 10.1016/j.mejo.2010.06.010    ISSN: 0026-2692    » doi
[abstract]
This paper proposes new admittance matrix models to approach the behavior of fully-differential Operational Transresistance Amplifiers (OTRAs) and Current Operational Amplifiers (COAs). The infinity-variables method is used in order to derive the new generalized models. As a consequence, standard nodal analysis being improved to compute fully-symbolic small-signal characteristics of fully-differential analog circuits. (C) 2010 Elsevier Ltd. All rights reserved.

Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors
F.V. Fernández, J. Esteban-Muller, E. Roca and R. Castro-López
Conference - International Conference on Evolutionary Computation CEC 2010
[abstract]
In this paper, the application of multi-objective evolutionary algorithms to the evaluation of performance trade-offs of planar inductors, an almost ubiquitous device in radio-frequency microelectronics, is studied. The absence of appropriate stopping criteria in most evolutionary algorithms reveals to be critical in this application. A new stopping criterion based on monitoring a set of performance metrics that account for convergence and diversity is proposed and demonstrated with practical radio-frequency circuit design problems.

Analog Layout Synthesis: Recent advances in topological approaches
H. Graeb, F. Balasa, R. Castro-López, Yao-wen Chang, F.V. Fernandez-Fernandez, Po-hung Lin and M. Strasser
Conference - Design Automation and Test in Europe Conference and Exhibition DATE 2009
[abstract]
This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

Analog circuit optimization system based on hybrid evolutionary algorithms
B. Liu, Y. Wang, Z. Yu, L. Liu, M. Li, Z. Wang, J. Lu and Fernández, F.V.
Journal Paper - Integration, the VLSI Journal, vol. 42, no. 2, pp 137-148, 2009
ELSEVIER    DOI: 10.1016/j.vlsi.2008.04.003    ISSN: 0167-9260    » doi
[abstract]
This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.

A fuzzy selection based constraint handling method for multi-objective optimization of analog cells
B. Liu, F.V. Fernández, P. Gao and G. Gielen
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
In this paper, a constraint handling technique for multi-objective optimization of analog cells is presented. Selection-based constraint handling and fuzzy membership functions are combined to construct a new constraint handling method, multi-objective fuzzy selection (MOFS). This is integrated with multi-objective sizing, which has the following two advantages: (1) enhances the effectiveness and efficiency of handling specifications distinctly; (2) specializes in solving multi-objective analog sizing problems mimicking the designer's interactive design process, avoiding inflexibility of crisp constraint sizing methods. ©2009 IEEE.

Applications of evolutionary computation techniques to analog, Mixed-signal and RF circuit design - an overview
E. Roca, M. Fakhfakh, R. Castro-López and F.V. Fernández
Conference - IEEE International Conference on Electronics, Circuits and Systems ICECS 2009
[abstract]
This paper review. The application of evolutionary computation techniques to analog, mixed-signal and radio-frequency design problems. Design needs, limitations of existing approaches and open challenges are pointed out. © 2009 IEEE.

Less expensive and high quality stopping criteria for MC-based analog IC yield optimization
B. Liu, F.V. Fernández, D. De Jonghe and G. Gielen
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2009
[abstract]
This paper investigate. The stopping criteria for Monte-Carlo (MC)-based yield optimization of analog integrated circuits. Available stopping criteria are briefly reviewed and a new adaptive criterion, called combined global and local improvement (Comlmp) is presented. Experimental results show that the proposed stopping criterion hat the following two advantages: (1) low risk of early termination befor. The optimum has been reached wit. The desired accuracy; (2) less additional function evaluations afte. The convergence has already been reached. ©2009 IEEE.

Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions
B. Liu, F.V. Fernández and G. Gielen
Conference - IEEE Congress on Evolutionary Computation CEC 2009
[abstract]
In this paper, a fuzzy selection-based differential evolution algorithm (FSBDE) for analog cell sizing is investigated. By combining the selection-based constraint handling method and fuzzy membership functions, a new selection methodology for handling fuzzy constraints is proposed and is integrated with the differential evolution (DE) algorithm to construct FSBDE. FSBDE specializes in solving analog sizing problems capturing imprecise human intentions, both avoiding the inflexibility of crisp constraint sizing methods and the excessive relaxation of available fuzzy sizing approaches. The high optimization ability of the DE algorithm is also inherited in this approach. Comparisons are carried out with the crisp selection-based differential evolution algorithm (SBDE) and DE in conjunction with available fuzzy optimization methods, showing that the proposed FSBDEalgorithm presents important advantages in terms of fuzzy constraint handling ability and optimization quality.© 2009 IEEE.

Hierarchical synthesis based on Pareto-optimal fronts
E. Roca, R. Castro-López and F.V. Fernández
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
Pareto-optimal fronts have recently arisen as a promising alternative for design space exploration, potentially enabling better and more efficient hierarchical synthesis. This paper reviews the Pareto front generation problem, extends this concept to reconfigurable circuits, and discusses alternative applications to hierarchical synthesis approaches.

Using Pareto-optimal fronts in the design of reconfigurable data converters
R. Castro-López, E. Roca and F.V. Fernández
Conference - International Conference on Advances in Circuits, Electronics and Microelectronics CENICS 2009
[abstract]
Analog design is a bottleneck in the design of integrated circuits. A recently proposed method to cope with the complexity of analog design is the use of a multi-objective bottom-up flow, which makes use of the concept of Pareto-optimal front (POF) to capture performance trade-offs of analog components, and through which these can be exploited during top-down design of a complex (hierarchically-wise) analog circuit. In this paper, we describe a step forward and transform this technique, through a new type of front we call Multi-Mode Pareto-optimal Front, to design reconfigurable Analog-to-Digital Converters (ADCs). We demonstrate that not only design time is shortened but also that design complexity of reconfigurable circuits can be more systematically and efficiently managed.

A memetic approach to the automatic design of high-performance analog integrated circuits
B. Liu, F.V. Fernández, G. Gielen, R. Castro-López and E. Roca
Journal Paper - Transactions on Design Automation of Electronic Systems, vol. 14, no. 3, pp 42, 2009
ASSOC COMPUTING MACHINERY    DOI: 10.1145/1529255.1529264    ISSN: 1084-4309    » doi
[abstract]
This article introduces an evolution-based methodology, named memetic single-objective evolutionary algorithm (MSOEA), for automated sizing of high-performance analog integrated circuits. Memetic algorithms may achieve higher global and local search ability by properly combining operators from different standard evolutionary algorithms. By integrating operators from the differential evolution algorithm, from the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes in handling analog circuit design problems with numerous and tight design constraints. The method has been tested through the sizing of several analog circuits. The results show that design specifications are met and objective functions are highly optimized. Comparisons with available methods like genetic algorithm and differential evolution in conjunction with static penalty functions, as well as with intelligent selection-based differential evolution, are also carried out, showing that the proposed algorithm has important advantages in terms of constraint handling ability and optimization quality.

Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey
J.M. de la Rosa, R. Castro-López, A. Morgado, E.C. Becerra Alvarez, R. del Río, F.V. Fernández and B. Pérez-Verdú
Journal Paper - Microelectronics Journal, vol. 40, no. 1, pp 156-176, 2009
ELSEVIER    DOI: 10.1016/j.mejo.2008.07.001    ISSN: 0026-2692    » doi
[abstract]
The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems. (C) 2008 Elsevier Ltd. All rights reserved.

Multimode Pareto fronts for design of reconfigurable analogue circuits
R. Castro-López, E. Roca and F.V. Fernández
Journal Paper - Electronics Letters, vol. 45, no. 2, pp 95-96, 2009
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el:20091795    ISSN: 0013-5194    » doi
[abstract]
Multimode Pareto-optimal fronts are presented. This is a novel concept that can be key in the design of reconfigurable analogue circuits, because it contains information not only on the trade-offs among the circuit performances, but also on its reconfiguration capabilities. A method to generate the front, relying on evolutionary optimisation, and a general dominance sorting algorithm that guides the optimisation, are both described.

Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers
R. Castro-López, A. Morgado, O. Guerra, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and F. Fernández
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp 227-241, 2009
SPRINGER    DOI: 10.1007/s10470-007-9122-0    ISSN: 0925-1030    » doi
[abstract]
This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.

AMS/RF-CMOS circuit design for wireless transceivers
R. Castro-López, D.R. de Llera, M. Ismail and F.V. Fernández
Journal Paper - Integration, the VLSI Journal, vol. 42, no. 1, pp 1-2, 2009
ELSEVIER    DOI: 10.1016/j.vlsi.2008.09.001    ISSN: 0167-9260    » doi
[abstract]
Abstract not available

Editorial
F.V. Fernández
Journal Paper - Integration, the VLSI Journal, vol. 41, no. 3, pp 317-318, 2008
ELSEVIER    DOI: 10.1016/j.vlsi.2008.04.005    ISSN: 0167-9260    » doi
[abstract]
Abstract not avaliable

Quality Metrics of Pareto-Optimal Fronts for Multi-Objective Synthesis of Analog ICs
F.V. Fernández, B. Liu, R. Castro-López and E. Roca
Conference - International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2008
[abstract]
Evolutionary computation (EC) techniques can be applied to synthesize analog integrated circuits via the Pareto dominance concept and multi-objective optimization. In order to find out which of the EC techniques available yields better results for analog circuit design, a set of metrics are required that compares and characterizes the Pareto-optimal fronts in terms of their analog design quality. In this paper, we select and classify existing, widely used quality metrics and propose new ones for analog multi-objective synthesis. Several experiments are used that back up the proposed metrics.

MSOEA: A New Methodology for Synthesis of High Performance Analog Integrated Circuits
B. Liu, F.V. Fernández, G. Gielen, R. Castro-López, E. Roca and J. Luo
Conference - Xth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2008
[abstract]
This paper introduces an evolution-based methodology, named memetic single objective evolutionary algorithm (MSOEA), for automated sizing of high performance analog integrated circuits. By combining operators from the differential evolution algorithm, the real-coded genetic algorithm, operators inspired by the simulated annealing algorithm, and a set of constraint handling techniques, MSOEA specializes on handling analog circuit synthesis problems with numerous and tight design constraints. The method has been tested on several analog circuits. Comparisons with available methods show that the proposed algorithm presents important advantages in constraint handling ability and optimization quality.

Hierarchical Design of Reconfigurable Analog Circuits using Multi-Mode Pareto Fronts
R. Castro-López, F.V. Fernández and E. Roca
Conference - Int. Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design SM2ACD 2008
[abstract]
Most reconfigurable analog integrated circuits reported follow an ad-hoc design approach, which do not guarantee neither efficient area occupation nor minimized power consumption for all operation modes. A clear example is the Analog-to-Digital Converter (ADC), used in multi-standard transceivers. This paper tries to formulate a hierarchical design approach based on the following elements: (1) An improved top-down synthesis with bottom-up generated low-level design information; (2) An original definition of the reconfiguration capabilities of the building blocks; (3) A optimization-based technique for the exploration of candidate architectures; (4) Last but not least, a clear definition of metrics for reconfigurability to measure how good is a design in terms its reconfiguration capabilities. This methodology is illustrated through the design of a multi-standard ΣΔ modulator.

An integrated layout-synthesis approach for analog ICs
R. Castro-López, O. Guerra, E. Roca and F.V. Fernández
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 7, pp 1179-1189, 2008
IEEE    DOI: 10.1109/TCAD.2008.923417    ISSN: 0278-0070    » doi
[abstract]
In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.

Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform
R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper - Microelectronics Journal, vol. 39, no. 1, pp 137-151, 2008
ELSEVIER    DOI: 10.1016/j.mejo.2007.10.005    ISSN: 0026-2692    » doi
[abstract]
This paper presents a detailed study of the clock jitter error in multi-bit continuous-time EA modulators with non-return-to-zero feedback waveform. It is demonstrated that jitter-induced noise power can be separated into two main components: one that depends on the modulator loop-filter transfer function and the other dependent on input signal parameters, i.e. amplitude and frequency. The latter component, not considered in previous approaches, allows us accurately to predict the resolution loss caused by jitter, showing effects not taken into account previously in literature despite the fact that they are especially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Closed-form expressions are derived for in-band error power and signal-to-noise ratio that can be used to optimize modulator performance in terms of jitter insensitivity. Time-domain simulations of several modulator topologies (both single-loop and cascade) intended for VDSL application demonstrate the validity of the presented approach. (c) 2007 Elsevier Ltd. All rights reserved.

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK
A. Morgado, V.J. Rivas, R. del Río, R. Castro-López, F.V. Fernández and J.M. de la Rosa
Journal Paper - Integration, the VLSI Journal, vol. 41, no. 2, pp 269-280, 2008
ELSEVIER    DOI: 10.1016/j.vlsi.2007.07.001    ISSN: 0167-9260    » doi
[abstract]
This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise, characterized by the noise figure and the signal-to-noise ratio, and non-linearity, represented by the input-referred second-order and third-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some block-specific errors have also been included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, which makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard direct-conversion receiver intended for 4G telecom systems is modeled and simulated considering the building block requirements for the different standards. (C) 2007 Elsevier B.V. All rights reserved.

Systematic design of high-resolution high-frequency cascade continuous-time sigma-delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, E. Roca, A. Rodríguez Vázquez and F.V. Fernández
Journal Paper - ETRI Journal, vol. 30, no. 4, pp 535-545, 2008
ETRI    DOI: 10.4218/etrij.08.0107.0225    ISSN: 1225-6463    » doi
[abstract]
This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigma-delta (SIGMA DELTA) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT SIGMA DELTA modulator in a 1.2 V 130 nm CMOS technology.

A 12-bit@40 MS/s Gm-C cascade 3-2 continuous-time sigma-delta modulator
R. Tortosa, A. Aceituno, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2007
[abstract]
This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade Sigma Delta modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.(dagger 1).

Towards systematic design of multi-standard converters
V.J. Rivas, R. Castro-López, A. Morgado, O. Guerra, E. Roca, R. del Río, J.M. de la Rosa and F.V. Fernández
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard YEA modulator meeting the specifications of three wireless communication standards.

A design tool for high-resolution high-frequency cascade continuous-time sigma delta modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V Fernández
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade EA modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Sigma Delta modulator in a 1.2V 130nm CMOS technology.

Reuse-Based Methodologies And Tools in the Design of Analog and Mixed-Signal Integrated Circuits
R. Castro-López, F.V. Fernández-Fernández, O. Guerra-Vinuesa and A. Rodríguez-Vázquez
Book - 393 p, 2006
SPRINGER    ISBN: 978-1-4020-5126-5    » link
[abstract]
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moore Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design -more subtle, hierarchically loose, and handicraft-demanding- has hindered a similar level of consensus and development. Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance.

Design of a 1.2-V 130 nm CMOS 13-bit@40 MS/s cascade 2-2-1 continuous-time sigma delta modulator
R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Conference - IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2006
[abstract]
This paper presents the design of a continuous-time multibit cascade 2-2-1 Sigma Delta modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.

Design of a 1.2-V cascade continuous-time Sigma triangle modulator for broadband telecommunications
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - International Symposium on Circuits and Systems ISCAS 2006
[abstract]
This paper presents the design of a continuous-time multibit cascade 2-2-1 Sigma Delta modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 0.13 mu m CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth.

Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2006
[abstract]
This paper presents design considerations for cascade Sigma-Delta Modulators (Sigma Delta Ms) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1(L-2) expandible Sigma Delta M is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach.

A new high-level synthesis methodology of cascaded continuous-time sigma delta modulators
R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, pp 739-743, 2006
IEEE    DOI: 10.1109/TCSII.2006.875310    ISSN: 1057-7130    » doi
[abstract]
This brief presents an efficient method for synthesizing cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to placing the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and. robustness with respect to circuit errors.

Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2005
[abstract]
This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other one due to the input signal parameters, i.e amplitude and frequency. The latter component, not considered in previous approaches, allows us to accurately predict the resolution loss caused by jitter, showing effects not taken into account up to now in literature which are specially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Time-domain simulations of several modulator topologies intended for VDSL application are given to validate the presented analysis.

Design Considerations for Multistandard Cascade ΣΔ Modulators
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2005
[abstract]
This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.

An approach to the design of the design of multistandard ΣΔ modulators
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference - WSEAS Int. Conf. on Electronics, Control and Signal Processing ICECS 2005
[abstract]
This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture-and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach.

Mixed analogue/digital and RF
R. Castro-López and F.V. Fernández-Fernández
Book Chapter - Medea + Design Automation Roadmap, pp 105-122, 2005
MEDEA +    ISBN: 2-9520704-2-3    
[abstract]
Abstract not available

An approach to the design of cascade sigma delta modulators for multistandard wireless transceivers
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper - WSEAS Transactions on Circuits and Systems, vol. 4, no. 12, pp 1811-1818, 2005
WSEAS    ISSN: 1109-2734    
[abstract]
This paper discusses issues concerning the design of reconfigurable cascade sigma-delta modulators for multistandard wireless transceivers. The use of an expandible cascade modulator is considered as the starting point to boost reconfigurability at the architectural level. Then, a top-down methodology is proposed to obtain the cascade candidates that better fulfil the requirements of each standard with adaptive power consumption, taking into account the complexity of the reconfiguration at both architecture- and circuit-level. Several reconfiguration strategies are presented and validated by time-domain behavioural simulations.

A reuse-based framework for the design of analog and mixed-signal ICs
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.

Continuous-time cascaded delta sigma modulators for VDSL: A comparative study
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes new cascaded continuous-time Sigma Delta modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely: transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.

Geometrically-constrained, parasitic-aware synthesis of analog ICs
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very timeconsuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenaRío is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
R. Castro-López, F.V. Fernández and A.R. Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.

A direct synthesis method of cascaded continuous-time sigma-delta modulators
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2005
[abstract]
This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to place the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealifies.(dagger 1)

Analysis of clock jitter error in multibit continuous-time sigma delta modulators with NRZ feedback waveform
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2005
[abstract]
This paper presents a detailed study of the clock jitter error in multibit continuous-time Sigma Delta modulators with non-return-to-zero feedback waveform. Closed-form expressions are derived for the in-band error power and the signal-to-noise ratio showing that the jitter-induced noise can be separated into two main components: one depending on the modulator loop filter and the other one due to the input signal. The latter, not considered in previous approaches, allows us to accurately predict the signal-to-noise ratio degradation and to optimize the modulator performance in terms of jitter insensitivity. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascaded or single-loop architectures. Time-domain simulations of several modulators are shown to validate the presented approach.(dagger 1)

High-level synthesis of switched-capacitor, switched-current and continuous-time sigma delta modulators using SIMULINK-based time-domain behavioral models
J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernández, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 9, pp 1795-1810, 2005
IEEE    DOI: 10.1109/TCSI.2005.852479    ISSN: 1057-7122    » doi
[abstract]
This paper presents a high-level synthesis tool for Sigma Delta modulators (Sigma Delta Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for Sigma Delta M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Sigma Delta Ms using both discrete-time and continuous-time circuit techniques.

A New Method for the High-Level Synthesis of Continuous-Time Cascaded ΣΔ Modulators
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2004
[abstract]
This paper presents an efficient method to design cascaded ΣΔ modulators implemented with continuous-time circuits. Instead of using a discrete-to-continuous time transformation, the proposed methodology is based on the direct synthesis of the whole cascaded architecture. This leads to more efficient topologies in terms of circuit complexity, power consumption and robustness with respect to parasitics. As an application, new cascaded topologies are synthesized and optimized to cope with VDSL specifications.

An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma delta modulators in the MATLAB/SIMULINK environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
This paper presents a MATLAB toolbox for the automated high-level sizing of SigmaDelta Modulators (SigmaDeltaMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.)

Synthesis of a wireless communication analog back-end based on a mismatch-aware symbolic approach
R. Castro-López, O. Guerra, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 40, no. 3, pp 215-233, 2004
SPRINGER    DOI: 10.1023/B:ALOG.0000034825.47829.04    ISSN: 0925-1030    » doi
[abstract]
In this paper, a methodology to automate the synthesis of an industrial-purpose analog integrated circuit, namely the back-end of an I&Q transmit interface, is presented. A good matching between both I and Q channels is desirable to ensure the correct circuit functioning. The proposed methodology combines the use of symbolic expressions with numerical approaches. While the symbolic expressions allow a fast iterative evaluation of the circuit performance, the numerical capabilities ensure a rapid optimization of the results. Unlike other approaches, the methodology uses symbolic expressions explicitly considering device mismatch, which are evaluated performing a Monte-Carlo analysis. The expressions have been obtained using an error-control process guided by the mean and standard deviation values of the circuit performance characteristics. This provides two benefits. First, smaller expressions are obtained. Second, expression evaluation is faster: smaller number of operations - symbol products and term sums - are carried out since, at each Monte-Carlo run, only those symbols related to device mismatch are to be changed, while the rest remains constant. A comparison between the presented synthesis technique and other purely numerical and numerical/symbolic approaches is also given.

Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Forum on Specification & Design Languages FDL 2003
[abstract]
Abstract not available

Design methodologies for sigma-delta converters
F.V. Fernández, R. del Río, R. Castro-López, F. Medeiro and B. Pérez-Verdú
Book Chapter - CMOS Telecom Data Converters, pp 523-559, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_15    ISBN: 978-1-4419-5382-7    » doi
[abstract]
Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.

Editorial - Analog and mixed-signal IC design and design methodologies
F.V. Fernández
Journal Paper - Integration, the VLSI Journal, vol. 36, no. 4, pp 157-159, 2003
ELSEVIER    DOI: 10.1016/j.vlsi.2003.09.002    ISSN: 0167-9260    » doi
[abstract]
Abstract not available

Behavioural modelling and simulation of sigma delta modulators using hardware description languages
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2003
[abstract]
Behavioural simulation is the common alternative to the costly electrical simulation of SigmaDelta modulators (EAMs). This paper explores the behavioural modelling and simulation of SigmaDeltaMs by using hardware description languages (HDLs) and commercial behavioural simulators,, as an alternative to the common special-purpose behavioural simulators. A library of building blocks, where a HDL has been used to model a complete set of circuit non-idealities influencing the performance of SigmaAMs, is introduced. Three alternatives for introducing SigmaDeltaM topologies have been implemented Experimental results of the simulation of a fourth-order 2-1-1 cascade multi-bit YAM are given.

Accurate VHDL-based simulation of sigma delta modulators
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
Computational cost of transient simulation of SigmaDelta modulators (SigmaDeltaMs) at the electrical level is prohibitively high. Behavioral simulation techniques arise as a promising solution to this problem. This paper demonstrates that both, hardware description languages (HDLs) and commercial HDL simulators, constitute a valuable alternative to traditional special-purpose SigmaDelta behavioral simulators. In this sense, a library of HDL building blocks, modeling a complete set of circuit non-idealities which influence the performance of SigmaDeltaMs, is presented. With these blocks, SigmaDeltaM architectures can be described in two different ways, which are analyzed in detail. Experimental results are provided through several simulations of a fourth-order 2-1-1 cascade multi-bit SigmaDeltaM.

Generation of technology-portable flexible analog blocks
R. Castro-López, F.V. Fernández, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even to different technology processes. By careful integration of the tuning process of design parameters with layout generation, fully functional designs are generated in a few minutes of CPU time.

A symbolic pole/zero extraction methodology based on analysis of circuit time-constants
O. Guerra, J.D. Rodríguez-García, F.V. Fernández and A. Rodríguez-Vázquez
Conference - International Workshop on Symbolic Methods and Applications to Circuit Design SMACD 2002
[abstract]
This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.

Approximate symbolic analysis of hierarchically decomposed analog circuits
O. Guerra, E. Roca, F.V. Fernandez and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp 131-145, 2002
KLUWER ACADEMIC    DOI: 10.1023/A:1015094011107    ISSN: 0925-1030    » doi
[abstract]
This paper presents a methodology for the symbolic analysis of large analog integrated circuits using a hierarchical approach. The drawbacks of previous approaches are solved by the introduction of error-controlled approximation strategies. A proper modeling methodology through the different hierarchical levels allows to combine the optimum techniques for generation of the symbolic expressions and the most efficient numerical techniques for error control. These approximation strategies together with mechanisms for partitioning and union of blocks through the hierarchy yield optimum results in terms of speed, accuracy and complexity of the symbolic results.

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