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Author: Núñez Martínez, Juan
Year: Since 2002
All publications
Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Reliability in CMOS-based integrated circuits has always been a critical concern. In today′s ultra-scaled technologies, a time-varying kind of variability has raised that, on top of the well-known time-zero variability, threatens to shorten the lifetime of integrated circuits, both analog and digital. Effects like Bias Temperature Instability and Hot Carriers Injection need to be studied, characterized and modeled to include, and, thus, mitigate, their impact in the design of CMOS integrated circuits. This paper presents an array-based integrated circuit whose purpose is precisely that: to observe, quantify and characterize the impact of timedependent variability effects in a specific kind of circuits: Ring Oscillators.

Device Circuit Co-Design of HyperFET Transistors
J. Núñez and M.J. Avedillo
Conference - International Forum on Information Systems and Technologies INFOS2019
[abstract]
In this paper, we describe a device-circuit codesign experiment for Hybrid Phase Transition FETs (HyperFETs) transistors. Inverter chains and ring oscillators are evaluated using three HyperFETs devices. Our results suggest guidance for device design to avoid known power penalty mechanisms at the circuit level.

Power and Speed Evaluation of Hyper-FET Circuits
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Access, vol. 7, pp 6724-6732, 2019
IEEE    DOI: 10.1109/ACCESS.2018.2889016    ISSN: 2169-3536    » doi
[abstract]
Many emerging devices are currently being explored as potential alternatives to complementary metal-oxide-semiconductor (CMOS) technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at circuit level. In this paper, we investigate the speed and power performance of Hyper-Field Effect Transistor (Hyper-FET) circuits, comparing them with both high-performance (HP) and low stand-by power (LSTP) Fin-Shaped Field Effect Transistor (FinFET) designs on the same technology node. The evaluation, which was carried out at gate and circuit level, includes characterization of 8 bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from transistor and gate level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated which support the obtained results.

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
DOI: http://hdl.handle.net/10261/180405    » doi
[abstract]
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.

Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper - IEEE Electron Device Letters, vol. 39, no. 11, pp 1776-1779, 2018
IEEE    DOI: 10.1109/LED.2018.2871855    ISSN: 0741-3106    » doi
[abstract]
Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.

Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jiménez, M.J. Avedillo and J. Núñez
Conference - Conference on Ph.D Research in Microelectronics and Electronics PRIME 2018
[abstract]
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.

Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Impact of TFET reverse currents into circuit operation: A case study
J. Nuñez
Conference - Joint Int. EUROSOI Workshop and Int. Conf. on Ultimate Integration on Silicon EUROSOI-ULIS 2018
[abstract]
Tunnel FET transistors (TFETs) are one of the most promising candidates to replace CMOS transistors for future integrated circuits. However TFET-based circuit design can exhibit significant limitations due to their reverse conduction currents caused by the direct bias of the intrinsic diode of these transistors. In this paper we analyze in depth this issue through the design of charge pump (DC-DC step up converters) circuits for energy harvesting applications. The proposed solution mitigates the impact of reverse conduction currents and, thus, improves power conversion efficiencies (PCE) compared to previous designs.

Impact of the RT-level architecture on the power performance of tunnel transistor circuits
M.J. Avedillo and J. Núñez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 46, no. 3, pp 647-655, 2018
JOHN WILEY & SONS    DOI: 10.1002/cta.2398    ISSN: 0098-9886    » doi
[abstract]
Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer-level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth.

Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
J. Nuñez and M.J. Avedillo
Journal Paper - IEEE Journal of the Electron Devices Society, vol. 5, no. 6, pp 530-534, 2017
IEEE    DOI: 10.1109/JEDS.2017.2737598    ISSN: 2168-6734    » doi
[abstract]
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical TFET rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.

Insights into the Operation of Hyper-FET-Based Circuits
M.J. Avedillo and J. Nuñez
Journal Paper - IEEE Transactions on Electron Devices, vol. 64, no. 9, pp 3912-3918, 2017
IEEE    DOI: 10.1109/TED.2017.2726765    ISSN: 0018-9383    » doi
[abstract]
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I-ON/I-OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.

Exploring Logic Architectures Suitable for TFETs Devices
J. Núñez and M.J. Avedillo
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates to overcome the power density and energy inefficiency limitations of CMOS technology, which are critical for IoT development. Although they show higher ON currents than CMOS at low supply voltages, currently TFETs do not reach those exhibited by CMOS at its nominal supply voltage and so they have being identified to be competitive for moderate operating frequencies. However, in many cases, architectural choices are not taken into account when benchmarking them against CMOS. In this paper we claim that the logic architecture should be selected in order to take full advantage of the specific characteristics of these devices. Widely used circuits are designed and evaluated showing how properly tuning the logic architecture results in raising the frequency up to which TFETs are competitive or in increasing power savings at lower frequencies.

Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Transactions on Nanotechnology, vol. 16, no, 1, pp 83-89, 2017
IEEE    DOI: 10.1109/TNANO.2016.2629264    ISSN: 1536-125X    » doi
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power-speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four MOSFET and FinFET transistors. The impact of logic depth, switching activity and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.

Complementary Tunnel Gate Topology to Reduce Crosstalk Effects
J. Núñez and M.J. Avedillo
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2016
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated.

Impact of Pipeline in the Power Performance of Tunnel Transistor Circuits
M.J. Avedillo and J. Núñez
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
[abstract]
Tunnel transistors are one of the most attractive steep sub threshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, we analyze the impact of the logic depth into the power consumption and energy efficiency of logic circuits and show critical differences between tunnel transistors and CMOS technologies, due to the distinct delay versus supply voltages exhibited by each type of device. Obtained results show that reducing logic depth as a power reduction technique is more efficient for tunnel transistors circuits than for their CMOS counterparts. A simple model to estimate the power reductions achieved when using pipeline to cut down logic depth, and taking into account the power overheads associated to the pipelined registers is developed. It shows that in CMOS power benefits cancels with the incorporation of a number of flip-flops equal to the 5% of the number of gates in the original circuit while this number rises to 90% for tunnel circuits. Simulation experiments of a simple adder tree are carried out to validate our analysis. No power savings are obtained by the CMOS pipelined circuit while the TFET pipelined circuit saves 77% of power. The results of this work suggest that architectural issues should be considered in the evaluation of this type of transistors.

Secure Cryptographic Hardware Implementation Issues for High-Performance Applications
E. Tena-Sánchez, A.J. Acosta and J. Nuñez
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2016
[abstract]
In this paper the effect of high-performance techniques for high speed applications in secure cryptographic implementations is studied. The use of dual precharge logic styles with fine-grained pipelining with an overlapping three-phase clock scheme is studied, also including a correct distribution of the clock signal in the cryptographic implementation. To make this study, four different implementations of the Sbox-9 of the Kasumi algorithm have been implemented using an 90nm TSMC technology. Simulation-based DPA attacks have been carried out, showing how the proper synchronization of data signals gives better results in terms of power consumption and operating frequency, but affects negatively the security against side channel attacks, decreasing the number of input patterns needed to disclosure the secret key.

Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
J. Núñez and M.J. Avedillo
Journal Paper - IEEE Transactions on Electron Devices, vol. 63, no. 12, pp 5012-5020, 2016
IEEE    DOI: 10.1109/TED.2016.2616891    ISSN: 0018-9383    » doi
[abstract]
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
J. Núñez, A.J. Ginés, E. Peralías and A. Rueda
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 89, no. 33, pp 593-609, 2016
SPRINGER    DOI: 10.1007/s10470-016-0870-6    ISSN: 0925-1030    » doi
[abstract]
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 μm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.

Assessing application areas for tunnel transistor technologies
M.J. Avedillo and J. Núñez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.

Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J. Núñez, A.J. Gines, E. Peralías and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18μm commercial CMOS process.

Improving robustness of dynamic logic based pipelines
H.J. Quintero, M.J. Avedillo and J. Núñez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.

Improving speed of tunnel FETs logic circuits
M.J. Avedillo and J. Núñez
Journal Paper - Electronics Letters, vol. 51, no. 21, pp 1702-1704, 2015
IEEE    DOI: 10.1049/el.2015.2416    ISSN: 0013-5194    » doi
[abstract]
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8-bit ripple carry adders when implemented with the solution.

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs
J. Núñez, A.J. Ginés, E.J. Peralías and A. Rueda
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
[abstract]
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for highperformance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm).

DOE Based High-Performance Gate-Level Pipelines
J. Núñez, M.J. Avedillo and H.J. Quintero
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2014
[abstract]
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the noninverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic one, a non-inverting gate requires one or more of its inputs to be also at logic one. We analyze the operation of gate-level pipelines implemented with domino and with Delayed Output Evaluation (DOE), an inverting dynamic gate we have recently proposed, and compare their performance. Using domino and DOE gates similar in terms of delay, improvements in operating frequencies around 50% have been obtained by the DOE pipelines.

Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements
J. Nuñez, M.L. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp 2238-2242, 2014
IEEE    DOI: 10.1109/TVLSI.2013.2283306    ISSN: 1063-8210    » doi
[abstract]
Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable (MOBILE) gates are very suitable for implementing gate-level pipelines, which can be achieved without resorting to memory elements. The MOBILE operating principle is implemented operating two series connected negative differential resistance devices with a clock bias. This brief describes and experimentally validates a two-phase clock scheme for such MOBILE-based ultragrained pipelines. Its advantages over other reported interconnection schemes for MOBILE gates, and also over pure CMOS two-phase counterparts, are stated and analyzed. Chains of MOBILE gates have been fabricated and the experimental results of their correct operation with a two-phase clock scheme are provided. As far as we know, this is the first working MOBILE circuit to have been reported with this interconnection architecture.

Novel dynamic gate topology for superpipelines in DSM technologies
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference - Euromicro Conference on Digital System Design DSD 2013
[abstract]
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high throughput. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and the Carry-Merge chain of a Kogge-Stone adder is designed as an application example.

Improving delay-noise trade-off of dynamic gates for fine-grained pipelined applications
J. Núñez, M.J. Avedillo, J.M. Quintana and H.J. Quintero
Conference - Conference on the Design of Circuits and Integrated Systems DCIS 2013
[abstract]
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained by their functional limitation, being able to implement only non inverting functions and the labor-intensive design required due to timing challenges of fine grained pipelines used for high through-output. Development of novel topologies aiming to cope with all these challenges is an area of active research. In this paper, we describe a novel topology that addresses all the above stated problems. The proposed gate implements inverting functionalities, exhibits very competitive delay-noise tradeoffs and it is well suited to implement building blocks with function-independent delays which can simplify design. Unlike previous reported solutions, it is the gate static output stage which is modified. The novel topology is analyzed and evaluated, and a gate per phase Carry Look Ahead adder is designed as an application example.

Novel pipeline architectures based on Negative Differential Resistance devices
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Microelectronics Journal, vol. 44, no. 9, pp 807-813, 2013
ELSEVIER    DOI: 10.1016/j.mejo.2013.06.012    ISSN: 0026-2692    » doi
[abstract]
Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.

Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Nuñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an 'all MOS' version of one previously reported which uses Resonant Tunneling Diodes (RTDs). The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.

Two-phase RTD-CMOS pipelined circuits
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Nanotechnology, vol. 11, no. 6, pp 1063-1066, 2012
IEEE    DOI: 10.1109/TNANO.2012.2213839    ISSN: 1536-125X    » doi
[abstract]
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations.

Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
[abstract]
Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved without resorting to memory elements. MOBILE operating principle is implemented using two series connected Negative Differential Resistance (NDR) devices with a clocked bias. This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.

Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
J. Núñez-Martínez, M.J. Avedillo and J.M. Quintana-Toledo
Conference - Iberchip XVIII Workshop IWS 2012
[abstract]
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an I-V characteristic exhibiting Negative Differential Resistance (NDR) built from MOS transistors plus an inductor and a resistor. Frequency division is obtained from the period adding sequences which appear in its bifurcation diagram. The analyzed circuit is an ¿all MOS¿ version of one previously reported which use Resonant Tunneling Diodes (RTDs) The results show that the dividing ratio can be selected by modulating the input signal frequency, in a similar way to the RTD-based circuit.

Compact and Power Efficient MOS-NDR Muller C-Elements
J. Núñez-Martínez, M. J. Avedillo and J.M. Quintana-Toledo
Conference - IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems DoCEIS 2012
[abstract]
Recently there is a renewed interest in the development of transistor circuits which emulate the Negative Differential Resistance (NDR) exhibited by different emerging devices like Resonant Tunneling Diodes (RTDs). These MOS-NDR circuits easily allow the prototyping of design concepts and techniques developed for such NDR devices. The importation of those concepts into transistor technologies can result in circuit realizations which are advantageous for some functionalities and application fields. This paper describes a Muller C-element which illustrates this statement which is inspired in an RTD-based topology. The required RTD is implemented by means of the MOS-NDR device. A 4-input Muller C-element has been fabricated and experimentally validated. The proposed circuit compares favorably with respect to a well-known conventional gate realization.

Domino inspired MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 48, no. 5, pp 292-293, 2012
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2011.3295    ISSN: 0013-5194    » doi
[abstract]
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported that alternates rising and falling edge-triggered MOBILE gates. A novel two-phase interconnection scheme resembling conventional domino pipelines is proposed and validated. It exhibits advantages in terms of speed with respect to both four-phase and single-phase interconnection schemes. In addition, the new architecture improves logic flexibility regarding the domino pipeline counterpart, since inverting and non-inverting stages can be interspersed.

Diseño lógico de circuitos digitales usando dispositivos con característica NDR
J. Núñez-Martínez
Thesis - Date of defense: 04/02/2011
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos con una, o varias, regiones de resistencia diferencial negativa (Negative Differential Resistance, NDR) en su característica IV. Uno de los dispositivos más representativos con este tipo de característica es el diodo basado en el efecto túnel resonante (Resonant Tunneling Diode, RTD). Las ventajas de velocidad, consumo y complejidad reducidas que ofrecen estos diodos frente a realizaciones convencionales, ya demostradas en tecnologías III/V, se asocian a la presencia de esta región NDR. El escalado de la tecnología MOS basada en silicio está alcanzando sus límites, en cuanto a densidad y prestaciones, debido a limitaciones físicas fundamentales por lo que la inclusión de dispositivos nanoelectrónicos, en los que se utilizan efectos cuánticos para obtener las funciones típicas del transistor, es una alternativa que debe ser considerada para la que, de hecho, puede constatarse una creciente actividad investigadora.

Efficient realization of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - Great Lakes Symposium on VLSI GLSVLSI 2011
[abstract]
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined. Lower average power and energy per cycle are obtained for RTD/CMOS implementations. Copyright © 2011 by ASME.

RTD-CMOS pipelined networks for reduced power consumption
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper - IEEE Transactions on Nanotechnology, vol. 10, no. 6, pp 1217-1220, 2011
IEEE    DOI: 10.1109/TNANO.2011.2157518    ISSN: 1536-125X    » doi
[abstract]
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations.

Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs
J. Nuñez, M.J. Avedillo and J.M. Quintana
Conference - SPIE Microtechnologies for the New Millennium 2011
[abstract]
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. We compare RTD-CMOS and pure CMOS realizations of a network of logic gates which can be operated in a gate-level pipeline. Significant lower average power is obtained for RTD-CMOS implementations.

Simplified single-phase clock scheme for MOBILE networks
J. Nuñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 47, no. 11, pp 648-649, 2011
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2011.0186    ISSN: 0013-5194    » doi
[abstract]
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required for this. A single-phase scheme is possible adding latches to the MOBILE gates. Proposed and experimentally validated is a new single-phase interconnection scheme that simplifies the inter-stage element, which translates in power, area and clock load advantages with respect to using latches.

Redes MOBILE MOS-NDR operando con reloj de una fase
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - Iberchip XVI Workshop IWS 2010
[abstract]
La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative Differential Resistance, NDR) resulta atractiva desde el punto de vista del diseño de circuitos, como ha sido demostrado por los circuitos que usan diodos basados en el efecto túnel resonante (Resonant Tunneling Diodes, RTDs). Ideas procedentes de diseños con RTDs pueden exportarse a un entorno 'todo CMOS' en el que la característica NDR se obtiene mediante transistores (MOS-NDR). En este artículo se proponen estructuras MOS-NDR para realizar puertas lógicas (Threshold Gates, TGs) que operan según el principio de operación MOBILE (MOnostable to BIstable Logic Element). Además, se demuestra que estas puertas pueden interconectarse para formar redes que operan en modo pipeline usando un esquema de reloj de una fase.

Analytic Approach to the Operation of RTD Ternary Inverters Based on MML
J. Núñez, J.M. Quintana and M.J. Avedillo
Book Chapter - Cutting Edge Nanotechnology, pp 97-112, 2010
INTECH    DOI: 10.5772/8847    ISBN: 978-953-7619-93-0    » doi
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaMultiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.

Evaluation of RTD-CMOS logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - Euromicro Conference on Digital System Design DSD 2010
[abstract]
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined fashion, thus allows estimating logic networks operating frequency. Lower power-delay products are obtained for RTD/CMOS implementations. © 2010 IEEE.

Single phase MOS-NDR mobile networks
J. Núñez, M.J. Avedillo and J.M. Quintana
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2010
[abstract]
Devices with an I-V characteristic exhibiting Negative Differential Resistance (NDR) are attractive from the circuit design point of view as it has been demonstrated by Resonant Tunneling Diodes (RTDs) circuits. Ideas coming from RTD-based designs can be exported to an "all CMOS" environment by using transistor circuits to generate the NDR characteristic (MOS-NDR). In this paper novel programmable MOS-NDRs are proposed and used to realize threshold logic gates on the basis of the MOnostable to BIstable Operating principle. It is shown that these gates can be connected to build up networks that are operated in a pipelined fashion using a single phase clock scheme.

Fast and area efficient multi-input Muller C-element based on MOS-NDR
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2009
[abstract]
A new multi-input Muller C-element based on a MOS-NDR device is proposed in this contribution. This design overcomes some drawbacks of previously proposed structures. A comparison in terms of area, delay and power consumption over another efficient CMOS Muller C-element circuit has been performed, resulting that our structure improves this performance.

Efficient realisation of MOS-NDR threshold logic gates
J. Núñez, M.J. Avedillo and J.M. Quintana
Journal Paper - Electronics Letters, vol. 45, no. 23, pp 1158-1159, 2009
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2009.1651    ISSN: 0013-5194    » doi
[abstract]
A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.

Operation limits for RTD-based MOBILE circuits
J.M. Quintana, M.J. Avedillo, J. Nuñez and H.P. Roldan
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 2, pp 350-363, 2009
IEEE    DOI: 10.1109/TCSI.2008.925943    ISSN: 1549-8328    » doi
[abstract]
Resonant-tunneling-diode (RTD)-based MOnostable-BIstable Logic Element (MOBILE) circuits operate properly in a certain frequency range. They exhibit both a minimum operating frequency and a maximum one. From a design point of view, it should be desirable to have gates with a correct operation from do up to the maximum operating frequency (i.e., without the minimum bound). This paper undertakes this problem by analyzing how transistors and RTDs interact in RTD-based circuits. Two malfunctions have been identified: the incorrect evaluation of inputs and the lack of self-latching operation. The difficulty to study these problems in an analytical way has been overcome by resorting to series expansions for both the RTD and the heterojunction field-effect transistor I-V characteristics in the points of interest. We have obtained analytical expression linking representative device parameters and technological setup, for a MOBILE-based circuit to operate correctly.

Design of RTD-based NMIN/NMAX gates
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE Conference on Nanotechnology, IEEE-NANO 2008
[abstract]
A novel implementation of NMIN/NMAX gates based on RTDs and transistors is presented. In this paper we will derive the relations that circuit representative parameters must verify to obtain a correct behaviour by means of the principles of the Monostable-to-Multistable Logic (MML). HSPICE simulations will be used to check our theoretical results. © 2008 IEEE.

Limits to a correct evaluation in RTD-based quaternary inverters
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - International Symposium on Multiple-Valued Logic ISMVL 2007
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML quaternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.

Operation limits for MOBILE followers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2006
[abstract]
This paper analyses how the presence of the HFET transistor modifies the DC operation of a Resonant Tunneling Logic Follower MOBILE, and can prevent its correct operation. The difficulty of an analytical study for the resulting circuit has been overcome by resorting to series expansions for both the RTD and the HFET I-V characteristics in the points of interest. We have obtained analytical expressions describing the regions where a MOBILE follower operates correctly. © 2006 IEEE.

Holding Dissapearance in RTD-based Quantizers
J. Núñez, J.M. Quintana and M.J. Avedillo
Conference - European Nano Systems Worshop ENS 2005
[abstract]
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation of such quantizer has two steps : sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to MML circuit topologies. This paper analyses the case of an MML ternary inverter used as a quantizer, and determines the relations that circuit representative parameters must verify to avoid this malfunction.

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