Publicaciones del IMSE

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Autor: Antonio Toro Frías
Año: Desde 2002

Artículos de revistas


Reliability simulation for analog ICs: Goals, solutions, and challenges
A. Toro-Frías, P. Martín-Lloret, J. Martin-Martinez, R. Castro-López, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernández
Journal Paper · Integration, the VLSI Journal, vol. 55, pp 341-348, 2016
resumen      doi      

The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.

Congresos


Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock
M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martin-Martinez, E. Roca, R. Castro-Lopez, R. Rodriguez, P. Martin-Lloret, A. Toro-Frias, D. Mateo, E. Barajas, X. Aragones and F.V. Fernandez
Conference · IEEE Latin America Electron Devices Conference LAEDC 2021
resumen     

The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.

Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Design Automation and Test in Europe DATE 2019
resumen     

Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen     

Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs
A. Toro-Frías, P. Martín-Lloret, J. Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen     

With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability but also the degradation due to time-dependent. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation
J. Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-Lopez, J. Martin-Martinez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen     

In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by timedependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of aging device effects for reliability circuit

Automated massive RTN characterization using a transistor array chip
P. Saraza-Canflanca, J. Diaz-Fortuny, A. Toro-Frias, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
resumen     

In this work, a CMOS transistor array for the massive measurement of random telegraph noise (RTN), together with a dedicated experimental setup, is presented. The array chip, called ENDURANCE, allows the massive characterization of the RTN parameters needed for a complete understanding of the phenomenon. Additionally, some experimental results are presented that demonstrate the convenience of the setup.

Reliability in the circuit design flow: from characterization and modelling to design automation
R. Castro-López, J. Díaz, J. Martín-Martínez, R. Rodríguez, M. Nafría, A. Toro, P. Martín, E. Roca, F.V. Fernández, E. Barajas, X. Aragonés and D. Mateo
Conference · How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop 2017
resumen     

Designing reliable analog circuits in advanced process technologies requires an accurate understanding of both device performance and variability. The unavoidable and increasingly important process-induced variations is, today, not alone in perturbing the ideal, intended performance of analog circuits: the so-called aging phenomena, like Bias Temperature Instability and Hot Carriers Injection, are altogether making the analog design business a much more tortuous endeavour. The work presented here will paint a complete picture of how to deal with variability in analog circuits for advanced process technologies. This picture starts with the characterisation and modelling of the aging phenomena at the device level. It then will show how these models can be used in the simulation of analog circuits, explaining the issues to overcome and the solutions that can be adopted. With these accurate models and capable circuit simulation techniques, the picture ends with a proposal for an analog design methodology that, using advanced optimization techniques, can successfully take into accounts all sources of variations (process and aging related) so that reliable analog circuits can be attained.

Efficient Computation of Yield and Lifetime for Analog ICs under Process Variabiliy and Aging
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2017
resumen     

With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability (i.e., spatial or process variability) but also the degradation due to time-dependent variability (i.e., aging). While process variability has been extensively treated, solutions to cope with aging-related problems are, nowadays, not yet mature enough, especially in the field of analog circuit simulation. Nevertheless, considerable efforts are currently being made to develop new simulation tools and simulation methodologies to evaluate the impact of reliability effects. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs
P. Martín-Lloret, A. Toro-Frías, J. Martin, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2017
resumen     

Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. Most of the up to day models focused on the aging phenomena make use of the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occurs while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower computational budgets.

Including a stochastic model of aging in a reliability simulation flow
A. Toro-Frías, P. Martin-Lloret, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen     

The availability and efficiency of reliability simulators for analog ICs is becoming critical with the scaling of devices down to the nanometer nodes. Two of the main challenges here are how to simultaneously include different sources of unreliability (such as the time-zero or spatial variability and the aging or time-dependent variability), and how to account for the self-induced changes in device biasing (i.e., stress conditions) caused by the device wear-out. In addition to the already existing stochastic models for time-zero variability, new models for the stochastically-distributed aging mechanisms have been developed in recent years. The combination of these challenges with the need for dealing with a stochastic model for aging, causes a serious computational load issue. This paper presents different methods to accurately include reliability in the simulation of analog ICs while preventing the simulation to become unaffordable in terms of CPU time and load.

CASE: A reliability simulation tool for analog ICs
P. Martín-Lloret, A. Toro-Frías, R. Castro-López, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2017
resumen     

With the evolution in the scale of integration in ICs, aging-related problems are becoming more important and, nowadays, solutions to cope with these issues are not yet mature enough, especially in the field of analog circuit simulation. CASE, the novel simulator presented in this paper, can evaluate the impact of reliability effects in analog circuits through a stochastic physic-based model. The implemented simulation flow is accurate and efficient in terms of CPU. The two main improvements over currently reported and commercial tools, is that the simulator can simultaneously take into account both time-zero and time-dependent variability, and that an adaptive method, to account for the strong link between biasing and stress, can improve the accuracy while keeping acceptable CPU times.

A Size-Adaptive Time-Step Algorithm for Accurate Simulation of Aging in Analog ICs
P. Martín, A. Toro, R. Castro, E. Roca, F.V. Fernández, J. Martín-Martínez and M. Nafría
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2016
resumen     

Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. Most of the up to day models focused on the aging phenomena make use of the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occurs while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower computational budgets.

A Fast and Accurate Reliability Simulation Method for Analog Circuits
A. Toro-Frias, R. Castro-Lopez, E. Roca, F.V. Fernández, J. Martin-Martinez, R. Rodriguez and M. Nafria
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
resumen     

Reliability has become a critical challenge in integrated circuit design in today's CMOS technologies. Aging problems have been added to the well-known issues due to spatial variations that are caused by imperfections in the fabrication process. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers (HC) cause a time-dependent variability that is added to the spatial variability. In addition, the BTI presents a stochastic behaviour, which may cause, for instance, time-varying mismatch. In this work, a model based on the physics of this phenomenon is implemented to accurately know its impact on the circuit performances. This method is focused on the analysis of analog circuits, taking into account the impact of both temporal and spatial variability. An effient simulation flow is implemented to evaluate the circuit performance at any instant of the circuit lifetime.

A simulation methodology for the reliability-aware design of analog circuits
A. Toro, R. Castro-López, E. Roca, F.V. Fernández, J. Martín-Martinez, R. Rodriguez and M. Nafria
Conference · International Mixed-Signals Testing Workshop IMSTW 2015
resumen     

With the scale of integration of modern transistors entering the atomic size and an increase of the gate-oxide field, reliability of electronic circuits is today more demanding than ever. Both spatial (i.e., process) variations and time-dependent (i.e., aging) variations dramatically reduce the yield and shortens the circuit lifetime, which prompt for reliability aspects to be considered in the design flow in order to attain resilient circuits featuring longer lifetimes. Aging effects such as as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) should be included just as well as process variations are.

An Automated Layout-Aware Design Flow
A. Toro-Frías, R. Castro-López, E. Roca and F.V. Fernández
Conference · Int. Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2012
resumen     

In analog integrated circuit design, it has always been necessary to improve the designer's productivity. The iterations between the electrical and physical synthesis, required to correct deviations due to parasitics, do degrade that productivity. The inclusion of the physical implementation directly within the electrical synthesis process, would in principle remove many or all of these iterations. This paper presents a fully-automated layout-aware design flow, whose key aspects are: (1) it uses commercially available tools and platforms to attain a highly integrated solution, (2) it provides solutions in the form of Pareto-optimal fronts, which represent the circuit's valuable trade-offs (and can be used in modern design flows), and (3) it allows including the impact of parasitics right into the fronts. This paper details the necessary tools and their integration for automation of the design flow and provides several examples of its use.

Layout-aware Pareto fronts of electronic circuits
A. Toro-Frías, R. Castro-López, E. Roca and F.V. Fernández
Conference · European Conference on Circuit Theory and Design ECCTD 2011
resumen      pdf

Pareto-optimal performance fronts have gained popularity as a representation of performance trade-offs of electronic circuits. They are also essential to support efficient bottom-up hierarchical design methodologies. Being such a key element in these methodologies, there have been many reported efforts to enhance the fronts with valuable information that goes beyond the nominal circuit behavior, such as the yield or the reconfiguration capabilities. However, the effect of layout parasitics is the factor that has been missing in the literature: the accuracy may be seriously degraded by layout parasitics not considered during the front generation. In this paper, we present a technique to generate layout-aware Pareto fronts that accurately accounts for the impact of both geometry and parasitics. © 2011 IEEE.

Libros


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Capítulos de libros


Modeling of variability and reliability in analog circuits
J. Martin-Martinez, J. Diaz-Fortuny, A. Toro-Frias, P. Martin-Lloret, P. Saraza-Canflanca, R. Castro-Lopez, R. Rodriguez, E. Roca, F.V. Fernandez and M. Nafria
Book Chapter · Modelling Methodologies in Analogue Integrated Circuit Design, pp 179-206, 2020
resumen      doi      

This chapter is divided into four sections. In Section 8.1, the probabilistic defect occupancy (PDO) model, a physics-based compact model, is introduced, which can be easily implemented into circuit simulators. Section 8.2 describes a purposely designed IC which contains suitable test structures, together with a full instrumentation system for the massive characterization of TZV and TDV in CMOS transistors, from which aging of the technology under study can be statistically evaluated. Section 8.3 is devoted to a smart methodology, which allows extracting the statistical distributions of the main physical parameters related to TDV from the measurements performed with the instrumentation system. Finally, Section 8.4 describes CASE, a new reliability simulation tool that accounts for TZV and TDV in analog circuits, covering important aspects, such as the device degradation evaluation, by means of stochastic modeling and the link between the device biasing and its degradation. As an example, the shifts of the performance of a Miller operational amplifier related to the device TDV is evaluated using CASE. Finally, in Section 8.5 the main conclusions are summarized.

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