Publicaciones del IMSE

Encontrados resultados para:

Autor: Fernando Medeiro Hidalgo
Año: Desde 2002

Artículos de revistas


A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces
A. Rodriguez-Pérez, M. Delgado-Restituto and F. Medeiro
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, vol. 8, no. 3, pp 358-370, 2014
resumen      doi      pdf

This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a novel implementation of the binary search algorithm that is complemented with adaptive biasing techniques for power saving. It has been fabricated in a standard CMOS 130 nm technology and only occupies 0.0326mm2. The PG-ADC has been optimized to operate under two different sampling modes, 27 kS/s and 90 kS/s. The former is tailored for raw data conversion of neural activity, whereas the latter is used for the on-the-fly feature extraction of neural spikes. Experimental results show that, under a voltage supply of 1.2 V, the PG-ADC obtains an ENOB of 7.56 bit (8-bit output) for both sampling modes, regardless of the gain setting. The amplification gain can be programmed from 0 to 18 dB. The power consumption of the PG-ADC at 90 kS/s is 1.52μW with a FoM of 89.49 fJ/conv, whereas at 27 kS/s it consumes 515 nW and obtains a FoM of 98.31 fJ/conv.

Impact of parasitics on even symmetric split-capacitor arrays
A. Rodríguez-Pérez, M. Delgado-Restituto and F. Medeiro
Journal Paper · International Journal of Circuit Theory and Applications, vol. 41, no. 9, pp 972-987, 2013
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This paper analyzes the impact of parasitic capacitances in the performance of split capacitive-based digital-to-analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the main responsible for the nonlinear behavior of these arrays, particularly for low-to-medium resolution converters. In order to validate the analysis, two versions of a complete low-power, low-voltage successive-approximation register analog-to-digital converter (ADC), intended for a disposable multi-channel bio-medical monitoring system, have been fabricated in a 0.35um standard complementary metal-oxide-semiconductor technology. The only difference between these two prototypes is that in one of them, the capacitive array is surrounded by dummy capacitors, while in the other prototype is not. Hence, the former achieves better mismatch performance at the expense of increased parasitics. The experimental results demonstrate that the version without dummy capacitors obtains higher effective resolution than the ADC with dummies, the power consumption being essentially the same for both prototypes, namely: 130nW at 2kS/s from a 1-V supply. These results are in full agreement with the analysis reported in the paper and confirm the proposed sizing procedure. © 2012 John Wiley & Sons, Ltd.

An approach to the design of cascade sigma delta modulators for multistandard wireless transceivers
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · WSEAS Transactions on Circuits and Systems, vol. 4, no. 12, pp 1811-1818, 2005
resumen     

This paper discusses issues concerning the design of reconfigurable cascade sigma-delta modulators for multistandard wireless transceivers. The use of an expandible cascade modulator is considered as the starting point to boost reconfigurability at the architectural level. Then, a top-down methodology is proposed to obtain the cascade candidates that better fulfil the requirements of each standard with adaptive power consumption, taking into account the complexity of the reconfiguration at both architecture- and circuit-level. Several reconfiguration strategies are presented and validated by time-domain behavioural simulations.

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs
J.M. de la Rosa, S. Escalera, B. Pérez-Verdú, F. Medeiro, O. Guerra, R. del Río and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp 2246-2264, 2005
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This paper describes a 0.35-mu m CMOS chopper-stabilized switched-capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0.5, x 1, x 2, and x 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 degrees C to 175 degrees C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm(2) silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution Sigma Delta modulators.

High-level synthesis of switched-capacitor, switched-current and continuous-time sigma delta modulators using SIMULINK-based time-domain behavioral models
J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernández, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 9, pp 1795-1810, 2005
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This paper presents a high-level synthesis tool for Sigma Delta modulators (Sigma Delta Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for Sigma Delta M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Sigma Delta Ms using both discrete-time and continuous-time circuit techniques.

Guest editorial for January 2004 special issue
A. Rodríguez-Vázquez, F. Medeiro and O. Feely
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 3, pp 437-439, 2004
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Abstract not available

Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
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We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.

Analysis of error mechanisms in switched-current sigma-delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 175-201, 2004
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This paper presents a systematic analysis of the major switched-current ( SI) errors and their influence on the performance degradation of SigmaDelta Modulators (SigmaDeltaMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass SigmaDeltaM (2nd-LPSigmaDeltaM) and a 4th-order BandPass SigmaDeltaM (4th-BPSigmaDeltaM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPSigmaDeltaMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI SigmaDeltaMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 mum CMOS SI 4th-BPSigmaDeltaM silicon prototype validate our approach.

Practical study of idle tones in 2nd-order bandpass Sigma Delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Microelectronics Journal, vol. 33, no. 11, pp 1005-1009, 2002
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This paper studies the tonal behaviour of the quantization noise in 2nd-order bandpass SigmaDelta modulators. Closed-form expressions for the frequency of the idle tones are derived for different locations of the signal centre frequency. The analytical results are validated through experimental measurements taken from a 0.8 mum CMOS prototype realized using fully differential switched-current circuits. (C) 2002 Elsevier Science Ltd. All rights reserved.

Congresos


A 5-Megapixel 100-Frames-per-second 0.5erms Low Noise CMOS Image Sensor with Column-Parallel Two-Stage Oversampled Analog-to-Digital Converter
J.A. Segovia, F. Medeiro, A. González, A. Villegas and A. Rodríguez-Vázquez
Conference · International Image Sensor Workshop, 2017
resumen     

Abstract not avaliable

Design Considerations for A Low-Noise CMOS Image Sensor
A. González-Márquez, A. Charlet, A. Villegas, F. Jiménez-Garrido, F. Medeiro, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2015
resumen     

This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.

High-speed global shutter CMOS machine vision sensor with high dynamic range image acquisition and embedded intelligence
F. Jiménez-Garrido, J. Fernández-Pérez, C. Utrera, J.M. Muñoz, M.D. Pardo, A. Giulietti, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Conference · Sensors, Cameras, and Systems for Industrial and Scientific Applications XIII IMAGING 2012
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High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, etc. Many of these applications call also for large spatial resolution, high sensitivity and the ability to detect images with large intra-frame dynamic range. This paper reports a CIS intelligent digital image sensor with 5.2Mpixels which delivers 12-bit fully-corrected images at 250Fps. The new sensor embeds on-chip digital processing circuitry for a large variety of functions including: windowing; pixel binning; sub-sampling; combined windowing-binning-subsampling modes; fixed-pattern noise correction; fine gain and offset control; color processing, etc. These and other CIS functions are programmable through a simple four-wire serial port interface.

Impact of Parasitic Capacitances on the Performance of SAR ADCs based on Capacitive Arrays
A. Rodriguez-Pérez, J.A. Rodríguez-Rodríguez, F. Medeiro and M. Delgado-Restituto
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2010
resumen     

Abstract not avaliable

A low-power reconfigurable ADC for biomedical sensor interfaces
A. Rodríguez-Pérez, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · Biomedical Circuits and Systems Conference BIOCAS 2009
resumen     

This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC can be tuned to handle a large variety of biopotential signals, with digitally selectable resolution and input signal amplitude. It achieves 10.4-bit of effective resolution sampling at 56kS/s, with a power consumption below 3 mu W from a 1V voltage supply.

A low-voltage low-power successive approximation reconfigurable ADC based on SC techniques
A. Rodríguez-Pérez, M. Delgado-Restituto and F. Medeiro
Conference · Ph.D. Research in Microelectronics and Electronics PRIME 2009
resumen     

This paper presents a 12-bit low-voltage low-power Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC is highly reconfigurable, with digitally selectable resolution and input signal amplitude, and achieves 11.4-bit of effective resolution at 500kHz clock frequency, with a power consumption below 3 mu W from a 1V voltage supply.

An ultra-low power consumption 1-V, 10-bit succesive approximation ADC
A. Rodríguez-Pérez, M. Delgado-Restituto, J. Ruiz-Amaya and F. Medeiro
Conference · IEEE International Conference on Electronics, Circuits and Systems ICECS 2008
resumen     

An ultra-low power consumption 10-bit rail-to-rail input range succesive-approximation Analog-to-Digital Converter (ADC) for sensor network applications is presented. It is designed in a standard 0.13um CMOS process technology. The converter consists of a capacitor-based digital-to-analog converter, a two-stage voltage comparator, formed by a pre-amplifier and a dynamic-latch, a passive sample-and-hold circuit, a current reference generator and digital circuitry for switching and control. Post-layout simulations show that the ADC consumes less than 2uW at a conversion rate of 100kS/s from a 1V voltage supply. Proper operation is achieved down to a supply voltage of 0.8 V. © 2008 IEEE.

Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
resumen      pdf

This paper presents design considerations for cascade Sigma-Delta Modulators (Sigma Delta Ms) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1(L-2) expandible Sigma Delta M is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach.

Design Considerations for Multistandard Cascade ΣΔ Modulators
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
resumen      pdf

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.

An approach to the design of the design of multistandard ΣΔ modulators
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · WSEAS Int. Conf. on Electronics, Control and Signal Processing ICECS 2005
resumen     

This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture-and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach.

A CMOS High-Resolution Automotive Sensor A/D Interface Based on a 110-dB @ 40kS/s Programmable-Gain Cascade 2-1 Sigma-Delta Modulator with Embedded Design-for-Testability Strategies
J.M. de la Rosa, S. Escalera, O. Guerra, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
resumen     

Abstract not available

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 sigma delta modulator with programmable gain and programmable chopper stabilization
O. Guerra, S. Escalera, J.M. de la Rosa, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen     

This paper describes a 0.35 μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/ 2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40 degrees C, 175 degrees C). The modulator architecture has been selected after an exhaustive comparison among multiple Sigma Delta M topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.

Embedded desing-for-testability strategies to test high-resolution SD modulators
S. Escalera, A. Espin, O. Guerra, J.M. de la Rosa, F. Medeiro and B. Pérez-Verdú
Conference · Conference on VLSI Circuits and Systems II, 2005
resumen     

This paper describes the design-for-testability strategies integrated in a 0.35 mu m CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented. Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.

Architectures and design considerations for wireline sigma delta modulators beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Workshop on ADC Modelling and Testing IWADC 2005
resumen     

In this paper we discuss design considerations for sigma-delta modulators (&USigma;&UDelta; Ms) aimed at high-linearity highspeed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12-15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenaRío. We show that, after proper architecture selection, guided by a simple power estimation method, these &USigma;&UDelta; Ms are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μ m CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade &USigma;&UDelta; Ms to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results. © 2005 Elsevier Ltd. All rights reserved.

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time sigma delta modulators
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, E. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
resumen      pdf

This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of SigmaDelta Modulators (SigmaDeltaMs). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for SigmaDeltaM synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.

A 0.35 μm CMOS 17-bit@40 kS/s sensor A/D interface based on a programmable-gain cascade 2-1 sigma delta modulator
J.M. García-González, S. Escalera, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
resumen      pdf

This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35mum standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) SigmaDelta modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from muVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.

An alternative DFT methodology to test high-resolution sigma delta modulators
S. Escalera, J.M. García-González, O. Guerra, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2004
resumen      pdf

In this paper, a novel DfT methodology to test high-resolution SigmaDelta Modulators (SigmaDeltaM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.

An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma delta modulators in the MATLAB/SIMULINK environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
resumen      pdf

This paper presents a MATLAB toolbox for the automated high-level sizing of SigmaDelta Modulators (SigmaDeltaMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.)

SIMSIDES Toolbox: An Interactive Tool for the Behavioural Simulation of Discrete- and Continuous-time ΣΔ Modulators in the MATLAB/SIMULINK Environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, R. del Río, B. Moreno-Reina, B. Pérez-Verdú, R. Tortosa, R. Romay and A. Rodríguez-Vázquez
Conference · Design of Circuits and Integrated Systems Conf. DCIS 2003
resumen     

This paper presents an user-friendly tool, named SIMSIDES, for the time-domain simulation of ΣΔ modulators in the MATLAB/SIMULINK environment. The tool is able to simulate an arbitrary ΣΔ topology implemented by using discrete-time - switched-capacitor and switched-current - and continuous-time circuit techniques, considering the most important circuit parasitics. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions. The combination of high accuracy, short CPU-time and interoperability of different circuit models, make the tool into a valuable instrument to optimize the design of ΣΔ analog-to-digital converters.

Design and Implementation of a 0.35μm CMOS Programmable-Gain 2-1 Cascade ΣΔ Modulator for Automotive Sensors
J.M. García-González, S. Escalera, J.M. de la Rosa, F. Medeiro, R. del Río, O. Guerra, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2003
resumen     

Abstract not available

Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Forum on Specification & Design Languages FDL 2003
resumen     

Abstract not available

Design Considerations for ΣΔ Modulators Beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop IBERCHIP 2003
resumen     

In this paper we discuss design considerations for Sigma-Delta modulators (ΣΔM) aimed at high-linearity, high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range 12-15bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade multi-bit architec-tures in a low-voltage, deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are still promising candidates to achieve post-ADSL performances in coming CMOS processes.

Behavioural modelling and simulation of sigma delta modulators using hardware description languages
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2003
resumen     

Behavioural simulation is the common alternative to the costly electrical simulation of SigmaDelta modulators (EAMs). This paper explores the behavioural modelling and simulation of SigmaDeltaMs by using hardware description languages (HDLs) and commercial behavioural simulators,, as an alternative to the common special-purpose behavioural simulators. A library of building blocks, where a HDL has been used to model a complete set of circuit non-idealities influencing the performance of SigmaAMs, is introduced. Three alternatives for introducing SigmaDeltaM topologies have been implemented Experimental results of the simulation of a fourth-order 2-1-1 cascade multi-bit YAM are given.

Expandible high-order cascade Sigma Delta modulator with constant, reduced systematic loss of resolution
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Instrumentation and Measurement Technology Conference I2MTC 2003
resumen     

An arbitrary order sigma-delta modulator cascade architecture is presented with only 1-bit loss of resolution due to scaling issues, even with single-bit quantization. This loss is kept with a high overloading point, regardless of the order. Simulations reveal that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization.

Design considerations for an automotive sensor interface sigma delta modulator
F. Medeiro, J.M. de la Rosa, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
resumen      pdf

In this paper we discuss design considerations for a Sigma-Delta modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. This SigmaDeltaM contains a programmable-gain input interface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently implemented by proper architecture selection and ad hoc sampling and integration capacitor structures. Behavioral simulations of a 17bit 40kS/s modulators are included to illustrate the design considerations.

A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time sigma delta modulators
J. Moreno-Reina, J.M. de la Rosa, F. Medeiro, R. Romay, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
resumen      pdf

This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of SigmaDelta modulators implemented by using switched-capacitor, switched-current and continuous-time Circuits, considering the most important error mechanisms. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions-The outcome is a complete SIMULINK block library that allows interactive, fast and accurate simulation of an arbitrary SigmaDelta topology.

Accurate VHDL-based simulation of sigma delta modulators
R. Castro-López, F.V. Fernández, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
resumen     

Computational cost of transient simulation of SigmaDelta modulators (SigmaDeltaMs) at the electrical level is prohibitively high. Behavioral simulation techniques arise as a promising solution to this problem. This paper demonstrates that both, hardware description languages (HDLs) and commercial HDL simulators, constitute a valuable alternative to traditional special-purpose SigmaDelta behavioral simulators. In this sense, a library of HDL building blocks, modeling a complete set of circuit non-idealities which influence the performance of SigmaDeltaMs, is presented. With these blocks, SigmaDeltaM architectures can be described in two different ways, which are analyzed in detail. Experimental results are provided through several simulations of a fourth-order 2-1-1 cascade multi-bit SigmaDeltaM.

A sigma delta modulator for a programmable-gain, low-power, high-linearity automotive sensor interface
J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
resumen     

This paper describes the design and electrical implementation of a 0.351mum CMOS 17-bit@40kS/s Sigma-Delta Modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. First of all, the paper discusses the most important limiting factors and design considerations applicable to a high-resolution SigmaDeltaM for sensor interfaces. After an exhaustive comparison among multiple SigmaDeltaM architectures in terms of resolution, speed and power dissipation, a third-order (2-1) cascade SigmaDeltaM is chosen. For a better fitting to the characteristics of different sensor outputs, the SigmaDeltaM here includes a programmable set of gains (0.5, 1, 2, and 4). The gain programmability is implemented by a reconfigurable capacitor array of unitary capacitors. In order to relax the amplifier dynamics requirements for the different modulator gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. Behavioural simulations considering transistor-level circuit parasitics shows a Dynamic Range (DR.) over 105dB for all cases of the modulator gain.

A 79-dB 4.4MS/s ΣΔ Modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2002
resumen     

Abstract not available

Design of a broadband ΣΔ modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen     

Abstract not available

Generation of technology-portable flexible analog blocks
R. Castro-López, F.V. Fernández, M. Delgado-Restituto, F. Medeiro and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
resumen     

This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even to different technology processes. By careful integration of the tuning process of design parameters with layout generation, fully functional designs are generated in a few minutes of CPU time.

Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop on Advances in Analog Circuit Design AACD 2002
resumen     

This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-mum CMOS technology are given and illustrated through experimental results.

Libros


CMOS cascade sigma-delta modulators for sensors and telecom. Error analysis and practical design
R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez
Book · ACSP, 299 p, 2006
resumen      link      pdf

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures. The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks. The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors. CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.

CMOS Telecom Data Converters
A. Rodríguez-Vázquez, F. Medeiro-Hidalgo and E. Janssens (Eds.)
Book · 588 p, 2003
resumen      link      

CMOS Telecom Data Converters compiles the latest achievements regarding the design of high-speed and high-resolution data converters in deep submicron CMOS technologies. The four types of analog-to-digital converter architectures commonly found in this arena are covered, namely sigma-delta, pipeline, folding/interpolating and flash. For all these types, latest achievements regarding the solution of critical architectural and circuital issues are presented, and illustrated through IC prototypes with measured state-of-the-art performances. Some of these prototypes are conceived to be employed at the chipset of newest generation wireline modems (ADSL and ADSL+). Others are intended for wireless transceivers. Besides analog-to-digital converters, the book also covers other functions needed for communication systems, such as digital-to-analog converters, analog filters, programmable gain amplifiers, digital filters, and line drivers.

Capítulos de libros


Power efficient ADCs for biomedical signal acquisition
A. Rodríguez-Pérez, M. Delgado-Restituto and F. Medeiro
Book Chapter · Biomedical Engineering, Trends in Electronics, Communications and Software, pp 171-192, 2011
resumen      doi      pdf

Rapid technological developments in the last century have brought the field of biomedical engineering into a totally new realm. Breakthroughs in materials science, imaging, electronics and, more recently, the information age have improved our understanding of the human body. As a result, the field of biomedical engineering is thriving, with innovations that aim to improve the quality and reduce the cost of medical care. This book is the first in a series of three that will present recent trends in biomedical engineering, with a particular focus on applications in electronics and communications. More specifically: wireless monitoring, sensors, medical imaging and the management of medical information are covered, among other subjects. Summary of the book.

High-order cascade multi-bit ΣΔ modulators
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 307-343, 2003
resumen      doi      pdf

Motivated by the commercial success of the wireline communication products, mixed-signal designers are being pushed to integrate A/D and D/A interfaces featuring 12- to 16-bit effective resolution for signal bandwidths well in excess of 1MHz. These specifications must be achieved in a low-voltage scenario, making use of poor performance (and often badly characterized) devices, which decreases the 'analog speed' of deep-submicron CMOS processes.

Sigma-delta CMOS ADCs: An overview of the state-of-the-art
A. Rodríguez-Vázquez, F. Medeiro, J.M. de la Rosa, R. del Río, R. Tortosa and B. Pérez-Verdú
Book Chapter · CMOS Telecom Data Converters, pp 37-91, 2003
resumen      doi      

As stated in Chapter 1, analog-to-digital conversion involves a number of tasks, namely:
- Sampling the input signal at frequency f s, with prior anti-aliasing filtering and, in some cases, holding the sampled values.
- Quantizing the input sample values with N bits; i.e., mapping each continuous-valued input sample onto the closest discrete-valued level out of the (2ˆN - 1) discrete levels covering the input signal variation interval.
- Encoding the result in a digital representation.

CMOS comparators
R. Domínguez-Castro, M. Delgado-Restituto, A. Rodríguez-Vázquez, J.M. de la Rosa and F. Medeiro
Book Chapter · CMOS Telecom Data Converters, pp 149-182, 2003
resumen      doi      

abstract not available

Bandpass sigma-delta A/D converters: Fundamentals, architectures and circuits
J.M. de la Rosa, B. Pérez-Verdú, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
resumen      doi      pdf

The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs

Design methodologies for sigma-delta converters
F.V. Fernández, R. del Río, R. Castro-López, F. Medeiro and B. Pérez-Verdú
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
resumen      doi      

Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.

Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · Analog Circuit Design: Structured Mixed-Mode Design, Multi-Bit Sigma-Delta Converters, Short Range RF Circuits, pp 235-260, 2002
resumen      doi      

This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-um CMOS technology are given and illustrated through experimental results.

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