Encontrados resultados para:
Autor: Belén Pérez Verdú
Año: Desde 2002
Artículos de revistas
Compact CMOS active quenching/recharge circuit for SPAD arrays
I. Vornicu, R. Carmona-Galán, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper · International Journal of Circuit Theory and Applications, vol. 44, no. 4, pp 917-928, 2016
resumen
doi pdf
Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recherge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12 μm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break-down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post- layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse-width jitter is below 1.8 ns when dead time is set to 40 ns.
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
R. Carmona-Galán, Á. Zarándy, C. Rekeczky, P. Földesy, A. Rodríguez-Pérez, C. Domínguez-Matas, J. Fernández-Berni, G. Liñán-Cembrano, B. Pérez-Verdú, Z. Kárász, M. Suárez-Cambre, V. Brea-Sánchez, T. Roska, Á. Rodríguez-Vázquez
Journal Paper · Journal of Systems Architecture, vol. 59, no. 10 part A, pp 908-919, 2013
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This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15 μm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.
A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications
A. Morgado, R. del Río, J.M. de la Rosa, R. Castro-López and B. Pérez-Verdú
Journal Paper · Microelectronics Journal, vol. 41, no. 5, pp 277-290, 2010
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doi
This paper describes the design and experimental characterization of a 0.13 mu m CMOS switched-capacitor reconfigurable cascade Sigma Delta modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode EA prototype shows an overall performance that is competitive with the current state of the art.(1) (C) 2010 Elsevier Ltd. All rights reserved.
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey
J.M. de la Rosa, R. Castro-López, A. Morgado, E.C. Becerra Alvarez, R. del Río, F.V. Fernández and B. Pérez-Verdú
Journal Paper · Microelectronics Journal, vol. 40, no. 1, pp 156-176, 2009
resumen
doi
The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems. (C) 2008 Elsevier Ltd. All rights reserved.
Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers
R. Castro-López, A. Morgado, O. Guerra, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and F. Fernández
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp 227-241, 2009
resumen
doi
This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.
An approach to the design of cascade sigma delta modulators for multistandard wireless transceivers
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper · WSEAS Transactions on Circuits and Systems, vol. 4, no. 12, pp 1811-1818, 2005
resumen
This paper discusses issues concerning the design of reconfigurable cascade sigma-delta modulators for multistandard wireless transceivers. The use of an expandible cascade modulator is considered as the starting point to boost reconfigurability at the architectural level. Then, a top-down methodology is proposed to obtain the cascade candidates that better fulfil the requirements of each standard with adaptive power consumption, taking into account the complexity of the reconfiguration at both architecture- and circuit-level. Several reconfiguration strategies are presented and validated by time-domain behavioural simulations.
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs
J.M. de la Rosa, S. Escalera, B. Pérez-Verdú, F. Medeiro, O. Guerra, R. del Río and A. Rodríguez-Vázquez
Journal Paper · IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp 2246-2264, 2005
resumen
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This paper describes a 0.35-mu m CMOS chopper-stabilized switched-capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0.5, x 1, x 2, and x 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 degrees C to 175 degrees C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm(2) silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution Sigma Delta modulators.
High-level synthesis of switched-capacitor, switched-current and continuous-time sigma delta modulators using SIMULINK-based time-domain behavioral models
J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernández, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 9, pp 1795-1810, 2005
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This paper presents a high-level synthesis tool for Sigma Delta modulators (Sigma Delta Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for Sigma Delta M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Sigma Delta Ms using both discrete-time and continuous-time circuit techniques.
Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper · IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
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We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.
Analysis of error mechanisms in switched-current sigma-delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 175-201, 2004
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This paper presents a systematic analysis of the major switched-current ( SI) errors and their influence on the performance degradation of SigmaDelta Modulators (SigmaDeltaMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass SigmaDeltaM (2nd-LPSigmaDeltaM) and a 4th-order BandPass SigmaDeltaM (4th-BPSigmaDeltaM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPSigmaDeltaMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI SigmaDeltaMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 mum CMOS SI 4th-BPSigmaDeltaM silicon prototype validate our approach.
Practical study of idle tones in 2nd-order bandpass Sigma Delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper · Microelectronics Journal, vol. 33, no. 11, pp 1005-1009, 2002
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This paper studies the tonal behaviour of the quantization noise in 2nd-order bandpass SigmaDelta modulators. Closed-form expressions for the frequency of the idle tones are derived for different locations of the signal centre frequency. The analytical results are validated through experimental measurements taken from a 0.8 mum CMOS prototype realized using fully differential switched-current circuits. (C) 2002 Elsevier Science Ltd. All rights reserved.
Congresos
Experiencia de puesta en marcha y desarrollo de un Máster on-line en Microelectrónica
A.J. Acosta, A. Barriga, B. Pérez and J.L. Huertas
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
resumen
Desde octubre de 2008 la Universidad de Sevilla oferta el título oficial de ‘Máster Universitario en Microelectrónica, Diseño y Aplicaciones de Sistemas Micro/nanométricos’. Dicho máster tiene, como característica diferenciadora respecto a la práctica totalidad de cursos similares existentes, la peculiaridad de ser impartido on-line. En su momento de aparición fue una auténtica novedad, que supuso un extraordinario reto, tanto en su puesta en marcha como en su desarrollo día a día, ya que aúna las características y problemática de realizar a la vez docencia a distancia y de contenido técnico muy especializado. Esta comunicación describe las características y la experiencia de puesta en marcha y desarrollo de un título exitoso en esta área.
Using 3-D Technologes for Form Factor Improvement of Low-Power Vision Sensors
J. Fernández-Berni, S. Vargas, J.A. Leñero and B. Pérez-Verdú
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2014
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While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and control of data interchange. This additional circuitry enables data processing be realized concurrently with the acquisition of images which is instrumental to reduce the number of data needed to carry to information contained into images. This way, more efficient vision systems can be built at the cost of larger pixel pitch. Vertically-integrated 3D technologies enable to keep the advnatges of smart pixels while improving the form factor of smart pixels.
Form Factor Improvement of Smart-Pixels for Vision Sensors through 3-D Vertically-Integrated Technologies
A. Rodríguez-Vázquez, R. Carmona-Galán, J. Fernández Berni, S. Vargas, J.A. Leñero, M. Suárez, V. Brea and B. Pérez-Verdú
Conference · IEEE Latin American Symposium on Circuits and Systems LASCAS 2014
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While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and control of data interchange. This additional circuitry enables data processing be realized concurrently with the acquisition of images which is instrumental to reduce the number of data needed to carry to information contained into images. This way, more efficient vision systems can be built at the cost of larger pixel pitch. Vertically-integrated 3D technologies enable to keep the advnatges of smart pixels while improving the form factor of smart pixels.
CMOS SPADs Selection, Modeling and Characterization Towards Image Sensors Implementation
M. Moreno-García, O. Guerra, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Conference on Electronics, Circuits, and Systems ICECS 2012
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The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance.
Circuital and Architectural Challenges for the Design of PET Medical Imaging Systems using CMOS
A. Rodríguez-Vázquez, R. Carmona-Galán, G. Liñán, R. del Río and B. Pérez-Verdú
Conference · International Workshop on Biomedical Applications of Micro-PET, 2010
resumen
Abstract not available
Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2006
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This paper presents design considerations for cascade Sigma-Delta Modulators (Sigma Delta Ms) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1(L-2) expandible Sigma Delta M is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach.
Design Considerations for Multistandard Cascade ΣΔ Modulators
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2005
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This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.
An approach to the design of the design of multistandard ΣΔ modulators
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference · WSEAS Int. Conf. on Electronics, Control and Signal Processing ICECS 2005
resumen
This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture-and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach.
A CMOS High-Resolution Automotive Sensor A/D Interface Based on a 110-dB @ 40kS/s Programmable-Gain Cascade 2-1 Sigma-Delta Modulator with Embedded Design-for-Testability Strategies
J.M. de la Rosa, S. Escalera, O. Guerra, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
resumen
Abstract not available
Embedded desing-for-testability strategies to test high-resolution SD modulators
S. Escalera, A. Espin, O. Guerra, J.M. de la Rosa, F. Medeiro and B. Pérez-Verdú
Conference · Conference on VLSI Circuits and Systems II, 2005
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This paper describes the design-for-testability strategies integrated in a 0.35 mu m CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented. Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.
Architectures and design considerations for wireline sigma delta modulators beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Workshop on ADC Modelling and Testing IWADC 2005
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In this paper we discuss design considerations for sigma-delta modulators (&USigma;&UDelta; Ms) aimed at high-linearity highspeed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12-15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenaRío. We show that, after proper architecture selection, guided by a simple power estimation method, these &USigma;&UDelta; Ms are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μ m CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade &USigma;&UDelta; Ms to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results. © 2005 Elsevier Ltd. All rights reserved.
MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time sigma delta modulators
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, E. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2004
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This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of SigmaDelta Modulators (SigmaDeltaMs). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for SigmaDeltaM synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.
A 0.35 μm CMOS 17-bit@40 kS/s sensor A/D interface based on a programmable-gain cascade 2-1 sigma delta modulator
J.M. García-González, S. Escalera, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
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This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35mum standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) SigmaDelta modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from muVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.
An alternative DFT methodology to test high-resolution sigma delta modulators
S. Escalera, J.M. García-González, O. Guerra, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2004
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In this paper, a novel DfT methodology to test high-resolution SigmaDelta Modulators (SigmaDeltaM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma delta modulators in the MATLAB/SIMULINK environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · International Symposium on Circuits and Systems ISCAS 2004
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This paper presents a MATLAB toolbox for the automated high-level sizing of SigmaDelta Modulators (SigmaDeltaMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.)
SIMSIDES Toolbox: An Interactive Tool for the Behavioural Simulation of Discrete- and Continuous-time ΣΔ Modulators in the MATLAB/SIMULINK Environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, R. del Río, B. Moreno-Reina, B. Pérez-Verdú, R. Tortosa, R. Romay and A. Rodríguez-Vázquez
Conference · Design of Circuits and Integrated Systems Conf. DCIS 2003
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This paper presents an user-friendly tool, named SIMSIDES, for the time-domain simulation of ΣΔ modulators in the MATLAB/SIMULINK environment. The tool is able to simulate an arbitrary ΣΔ topology implemented by using discrete-time - switched-capacitor and switched-current - and continuous-time circuit techniques, considering the most important circuit parasitics. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions. The combination of high accuracy, short CPU-time and interoperability of different circuit models, make the tool into a valuable instrument to optimize the design of ΣΔ analog-to-digital converters.
Design and Implementation of a 0.35μm CMOS Programmable-Gain 2-1 Cascade ΣΔ Modulator for Automotive Sensors
J.M. García-González, S. Escalera, J.M. de la Rosa, F. Medeiro, R. del Río, O. Guerra, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2003
resumen
Abstract not available
Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Forum on Specification & Design Languages FDL 2003
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Abstract not available
Design Considerations for ΣΔ Modulators Beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop IBERCHIP 2003
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In this paper we discuss design considerations for Sigma-Delta modulators (ΣΔM) aimed at high-linearity, high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range 12-15bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade multi-bit architec-tures in a low-voltage, deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are still promising candidates to achieve post-ADSL performances in coming CMOS processes.
A 2.5-V CMOS wideband sigma-delta modulator
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE Instrumentation and Measurement Technology Conference I2MTC 2003
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A high-performance SigmaDelta modulator for wireline communication applications is presented It employs a 4th-order cascade multi-bit architecture that requires only 16 oversampling ratio, and has been implemented using fully-differential SC circuits in a 0.25-mum CMOS technology. Measurements show a dynamic range of 84dB operating at Z2MS/s output rate, and 79dB at 4.4MS/s. The whole prototype dissipates 65.8mW from a 2.5-V supply.
Expandible high-order cascade Sigma Delta modulator with constant, reduced systematic loss of resolution
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Instrumentation and Measurement Technology Conference I2MTC 2003
resumen
An arbitrary order sigma-delta modulator cascade architecture is presented with only 1-bit loss of resolution due to scaling issues, even with single-bit quantization. This loss is kept with a high overloading point, regardless of the order. Simulations reveal that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization.
Design considerations for an automotive sensor interface sigma delta modulator
F. Medeiro, J.M. de la Rosa, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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In this paper we discuss design considerations for a Sigma-Delta modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. This SigmaDeltaM contains a programmable-gain input interface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently implemented by proper architecture selection and ad hoc sampling and integration capacitor structures. Behavioral simulations of a 17bit 40kS/s modulators are included to illustrate the design considerations.
A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time sigma delta modulators
J. Moreno-Reina, J.M. de la Rosa, F. Medeiro, R. Romay, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2003
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This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of SigmaDelta modulators implemented by using switched-capacitor, switched-current and continuous-time Circuits, considering the most important error mechanisms. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions-The outcome is a complete SIMULINK block library that allows interactive, fast and accurate simulation of an arbitrary SigmaDelta topology.
A sigma delta modulator for a programmable-gain, low-power, high-linearity automotive sensor interface
J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference · Conference on VLSI Circuits and Systems 2003
resumen
This paper describes the design and electrical implementation of a 0.351mum CMOS 17-bit@40kS/s Sigma-Delta Modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. First of all, the paper discusses the most important limiting factors and design considerations applicable to a high-resolution SigmaDeltaM for sensor interfaces. After an exhaustive comparison among multiple SigmaDeltaM architectures in terms of resolution, speed and power dissipation, a third-order (2-1) cascade SigmaDeltaM is chosen. For a better fitting to the characteristics of different sensor outputs, the SigmaDeltaM here includes a programmable set of gains (0.5, 1, 2, and 4). The gain programmability is implemented by a reconfigurable capacitor array of unitary capacitors. In order to relax the amplifier dynamics requirements for the different modulator gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. Behavioural simulations considering transistor-level circuit parasitics shows a Dynamic Range (DR.) over 105dB for all cases of the modulator gain.
A 79-dB 4.4MS/s ΣΔ Modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2002
resumen
Abstract not available
Design of a broadband ΣΔ modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference · Design, Automation and Test in Europe Conference and Exhibition DATE 2002
resumen
Abstract not available
A 2.5-V sigma delta modulator in 0.25μm CMOS for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2002
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This paper presents a dual-quantization cascade SC SigmaDelta modulator intended for A/D conversion in ADSL applications. The modulator combines a low oversampling ratio with 3-bit resolution in the last stage, to achieve 14bit@4.4MS/s (16x) and 15bit@2.2MS/s (32x) with no need of correction/calibration mechanisms. It consumes 66mW from a single 2.5-V supply and has been implemented in 0.25-mum CMOS technology.
Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference · Workshop on Advances in Analog Circuit Design AACD 2002
resumen
This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-mum CMOS technology are given and illustrated through experimental results.
Libros
CMOS cascade sigma-delta modulators for sensors and telecom. Error analysis and practical design
R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez
Book · ACSP, 299 p, 2006
resumen
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CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures.
The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks.
The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors.
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.
Systematic design of CMOS switched-current bandpass sigma-delta modulators for digital communication chips
J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez (Eds.)
Book · 499 p, 2002
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Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips gives a systematic methodology for designing Sigma-Delta Modulators (Sigma-Delta Ms), specially those of the bandpass type, realized in digital CMOS technologies by using switched-current (SI) circuits. For this purpose, an analysis of SI error mechanisms as well as their influence on the performance of Sigma-Delta Ms is presented in a detailed and comprehensive style. On the one hand, the depth of such an analysis allows designers to get practical knowledge of the performance degradation of SI Sigma-Delta Ms through closed-form expressions that relate the modulator specifications to SI cell design parameters. On the other hand, the behavioural models derived from that study make it possible a fast and precise time-domain simulation of SI Sigma-Delta Ms, shown in the book through a simulator developed in MATLAB/SIMULINK. The architectures and circuit design methodologies presented in this book are demonstrated through two standard CMOS IC prototypes - the first silicon realizations of SI bandpass Sigma-Delta Ms - intended for AM digital radio receivers. The good performance comparison obtained with current state-of-the-art of switched-capacitor ICs demonstrates the viability of SI circuits for the realization of digital communication chips. Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips is organized such that it can be useful for a large audience: from novices in the field to experienced Sigma-Delta M designers. The comprehensive treatment of SI Sigma-Delta Ms given in this book will allow all of them to improve their productivity through the incorporation of circuit knowledge and CAD tools to optimize the design and to shorten the design cycle.
Capítulos de libros
Bandpass sigma-delta A/D converters: Fundamentals, architectures and circuits
J.M. de la Rosa, B. Pérez-Verdú, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
resumen
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The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs
Design methodologies for sigma-delta converters
F.V. Fernández, R. del Río, R. Castro-López, F. Medeiro and B. Pérez-Verdú
Book Chapter · CMOS Telecom Data Converters, pp 523-559, 2003
resumen
doi
Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.
Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter · Analog Circuit Design: Structured Mixed-Mode Design, Multi-Bit Sigma-Delta Converters, Short Range RF Circuits, pp 235-260, 2002
resumen
doi
This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-um CMOS technology are given and illustrated through experimental results.
Otras publicaciones
CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 2
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course · Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
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Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.
CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 1.b
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course · Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
resumen
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Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.
CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 1.a
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course · Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
resumen
pdf
Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.
