Hardware
This section contains a brief description of the hardware design, the authors, the status, an archive of the design and testbench used for debugging and verification.
Communication Interfaces (CI)
- ID: HW_CI_01
Name: APB slave, AHB master/slave, AXI master/slave, AXI-STREAM master/slave and AMBA_TEST_FRAMEWORK
Description: A VHDL library of most common AMBA master and slaves and a VHDL test framework with basic examples.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Independent; License: GNU; Associated: -
Download link: IMSE_AMBA_MASTER_SLAVE_INTERFACES
Associated Publications: * Fularz, M., Kraft, M., Kasinski, A., Acasandrei, L.: A hybrid system on chip solution for the detection and labeling of moving objects in video streams. Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), pp. 94–99 (2013).
Embedded Vision (EV)
- ID: HW_EV_01
Name: Local Binary Pattern (LBP) face detection system and LBP hardware accelerator IP
Description: A Local Binary Pattern (LBP) face detection embedded system based on Aeroflex Gaisler´s LEON3 Sparc V8 32 bit processor. This embedded system contains a custom LBP face detection hardware accelerator and runs on Xilinx ML505 development board. The software for detection and the support software tools for debugging is also provided. The entire system is described in VHDL and its portable to various FPGA and ASIC technologies.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Various; License: GNU; Associated: SW_EV_01
Download link: LBP_FACE_DETECTION_SYSTEM_AND_HW_ACCELERATOR
- ID: HW_EV_02
Name: Viola-Jones face detection system and Viola-Jones hardware accelerator IP
Description: A Viola-Jones face detection embedded system based on Aeroflex Gaisler´s LEON3 Sparc V8 32 bit processor. This embedded system contains a custom Viola-Jones face detection hardware accelerator and runs on Xilinx ML505 development board. The software for detection and the support software tools for debugging is also provided. The entire system is described in VHDL and its portable to various FPGA and ASIC technologies.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Various; License: GNU; Associated: SW_EV_02
Download link: VIOLA_JONES_FACE_DETECTION_SYSTEM_AND_HW_ACCELERATOR
Associated Publications: * Acasandrei, L., Barriga, A.: AMBA bus hardware accelerator IP for Viola–Jones face detection. IET Computers & Digital Techniques, vol. 7, no. 5, pp. 200–209 (September 2013). * Acasandrei, L., Barriga, A.: Implementación sobre FPGA de un sistema de detección de caras basado en LEON3. Proceedings of the XVIII International IBERCHIP Workshop, pp. 6-9 (2012). * Acasandrei, L., Barriga, A.: FPGA implementation of an embedded face detection system based on LEON3. International Conference on Image Processing, Computer Vision, and Pattern Recognition, Las Vegas (2012).
- ID: HW_EV_03
Name: HISTOGRAM Generator IP
Description: A configurable HISTOGRAM hardware generator. The histograms bins and the width of the input data are configurable. The histogram bins are calculated in realtime and saved into memory for a posterior read.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Independent; License: GNU; Associated: -
Download link: HISTOGRAM_GENERATOR_IP
Arithmetic Circuits (AC)
- ID: HW_AC_01
Name: Scalable Low Area Integer Multiplier Generator (SLAM) IP
Description: The scalable low area multiplier (SLAM) is a novel architecture targeting low power/area applications. It can generate integer signed/unsigned multipliers having operands with a data width between 8 and 64 bits.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Independent; License: GNU; Associated: -
Download link: SLAM_IP
- ID: HW_AC_02
Name: Nonrestoring Integer SQR ASIC Pipelined Generator IP
Description: The Nonrestoring Integer square root (SQR) Pipelined Generator targets the high speed, high throughput applications. It can generate integer square root circuits having the operand with a data width betwen 8 and 256 bits.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Independent; License: GNU; Associated: -
Download link: NONRESTORTING_PIPE_SQR_IP
- ID: HW_AC_03
Name: RADIX 4 sequential Integer SQR Generator IP
Description: The RADIX 4 sequential Integer Generator IP targets targeting low power/area applications. It can generate integer square root circuits having the operand with a data width between 16 and 256 bits.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Independent; License: GNU; Associated: -
Download link: RADIX_4_SQR_IP
VIDEO CODER/ENCODER (VC)
- ID: HW_VC_01
Name: BT656 (ITU656) VIDEO STREAM DECODER IP
Description: This AMBA bus compatible IP is used to decode video streams compressed with BT656 standard. This IP was implemented in embedded system containing LEON3 Sparc V8 processor connected to a Videology 21C405W camera. The input video is decoded in real time and each frame is saved to a user defined memory area. The download link contains the VHDL sources code of the BT656_IP, the embedded system containing the IP and the software drivers and software examples on how to use the IP.
Author/s: Laurentiu ACASANDREI ; Supervisor/s: Angel BARRIGA
Status: PROVEN ; Technology: Independent; License: GNU; Associated: -
Download link: BT656_DECODER_IP