Call for papers
2nd International Workshop on
Impact of Low-Power design on Test and Reliability - LPonTR'09
Seville, Spain, May 29, 2009
fringe to European Test Symposium 2009
The International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design methodologies of nanometre silicon systems on test and reliability. Power and thermal issues, leakage, process variations, susceptibility to environmental and operation-induced interference are physical constraints that drive the development of low-power, process-tolerant design techniques. However, these techniques generate a new set of test and reliability challenges, questing for an innovative set of methodologies and tools.
You are invited to participate in LPonTR’09. Papers are invited that address current trends, challenges and proposed solutions in the following areas (but are not limited to):
· Power and process variations aware design and test
· Challenges of Ultra Low-power design on test and reliability
· Design for Variability at different abstraction levels and its effect on testing
· Reliability issues in silicon products on bellow 45 nm technologies
· Delay testing for high-performance low-power products
· Signal integrity in test mode
· Test and performance of physical on-chip infrastructures (power grid, clock distribution nets, etc.)
· Dynamic BIST and scan design for LP, process tolerant products
· Test and reliability issues in the presence of leakage
· Defect modelling, fault simulation and ATPG for emerging failure modes
· Discriminating physical defects from noise and uncertainty
· Low-power, low-voltage DfT
· Analog and mixed-signal low-power design, test and DfT
· test of SoC with power and thermal management (e.g., DVS, multi-Vth)
· Test and reliability of highly dependable, redundant systems
· Asynchronous design and test
· EDA tools to support LP, process-tolerant design
· Statistical and parametric test
Submissions – The organising committee invites authors to submit extended abstracts in the above
areas. All submissions will be peer-reviewed and accepted abstracts will be published in the informal
proceedings of the workshop.
Presentations – A number of accepted papers will be chosen for a full oral presentation (15-20 min)
and, optionally, tool demonstration. The other accepted papers will be presented as a short oral (2
min) in addition to either a poster or interactive/demo presentation.
Journal Publications – The best contributions will be invited for publication as a full paper
in a special section on LPonTR’09 in the ASP Journal of Low Power Electronics (JOLPE) -
http://www.aspbs.com/jolpe/. All accepted papers will be considered regardless of the form
of presentation.
Formats – Format for extended abstracts: 2 pages, IEEE conference layout or latex8, font 10, two
columns, paper A4, no page numbering, in PDF file format. Approximate dimensions: left/right
margin 20mm, top/bottom margin 30mm, column separation 8mm, single line spacing.
Format for posters: up to A0-portrait. Format for demo-s: contact the chairs.
Communication – Please e-mail your manuscripts directly to a.bystrov@ncl.ac.uk
Key Dates:
• Submission deadline : March 2, 2009
• Notification of acceptance : April, 14, 2009
• Final manuscript (electronic format) : April, 27, 2009
More details on LPonTR can be found on the workshop web site at:
http://www.staff.ncl.ac.uk/a.bystrov/LPonTR/2009/LPonTR-09-CfP.pdf
Chair / Co-Chair:
Dr. Alex Bystrov, Newcastle University, Newcastle upon Tyne, U.K, Email: a.bystrov@ncl.ac.uk
Dr. Patrick Girard, LIRMM, Montpellier, France, Email: girard@lirmm.fr
Registration: