Summary
The Internet of Things
(IoT) is now widely recognized as the next step of disruptive digital
innovation. With IoT, any physical and virtual object can become connected to
other objects and to the internet, creating a fabric of connectivity between
things and between humans and things. However, the development of IoT in the
near future faces a lot of technological challenges that need to be addressed,
such as power/energy efficiency, reliability, security, and cost. Advanced CMOS
technologies are potential candidates for solutions in the short term to those
challenges, whereas beyond-CMOS devices are the answer for solutions in the
long term. Low voltage operation to reduce power consumption leads, among other
effects, to an increase in the impact of variations, including process (also
known as Time Zero Variations, TZV) and time-dependent variations (TDV).
Overcoming the variability challenge is a formidable effort requiring a
synergistic approach, combining methods at all abstraction levels of the
manufacturing process, covering from the technology/device levels up to the
circuit and system/application levels. Furthermore, whereas in some cases
variability will be object of struggle, prevention and mitigation, it can also
be a powerful ally to reach the longed-for system security. This project
progresses in this direction through
the development of design strategies for
low-power variability-aware and secure circuits based on state-of-the-art CMOS
and emerging beyond-CMOS technologies.
This main objective will
be approached from different perspectives and at different depths, depending on
the degree of maturity of the devices and technologies. The first perspective is the characterization
and modelling of TDV phenomena in advanced CMOS technologies, with special
emphasis on the combined effect of Bias Temperature Instability (BTI) and Hot
Carrier Injection (HCI) and on the impact of Random Telegraph Noise (RTN) for
low voltage operation. Additionally, time-zero variability (TZV) models for
beyond-CMOS devices such as steep-slope devices, suitable for low-voltage
operation, will be obtained. Second, the impact of variability in low power circuits will be analyzed
using the models previously developed. Moreover, variability-aware design
techniques will be exploited to study how far the impact of all considered
effects can be mitigated in advanced CMOS and beyond-CMOS circuits Finally, variability (TZV
and RTN) will be considered as an effect that can be exploited for the design
of secure cryptographic primitives such as PUFs and TRNGs. In this sense, the
implementation of TRNGs based on phase transition devices (PTD) based nano-oscillators will be
explored. Also, since distinctive features of
beyond-CMOS devices are suitable for the implementation of efficient
cryptographic circuits, the design of Differential Power Analysis (DPA)-resilient
cryptographic circuits using TFETs will be addressed.