Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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A Sub-µW Reconfigurable Front-End for Invasive Neural Recording that Exploits the Spectral Characteristics of the Wideband Neural Signal
J.L. Valtierra, M. Delgado-Restituto, R. Fiorelli and A. Rodriguez-Vazquez
Journal Paper - IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp 1426-1437, 2020
IEEE    DOI: 10.1109/TCSI.2020.2968087    ISSN: 1549-8328    » doi
This paper presents a sub- µW ac-coupled reconfigurable front-end for invasive wideband neural signal recording. The proposed topology embeds filtering capabilities enabling the selection of different frequency bands inside the neural signal spectrum. Power consumption is optimized by defining specific noise targets for each sub-band. These targets take into account the spectral characteristics of wideband neural signals: local field potentials (LFP) exhibit l/f(x) magnitude scaling while action potentials (AP) show uniform magnitude across frequency. Additionally, noise targets also consider electrode noise and the spectral distribution of noise sources in the circuit. An experimentally verified prototype designed in a standard 180 nm CMOS process draws 815 nW from a 1 V supply. The front-end is able to select among four different frequency bands (modes) up to 5 kHz. The measured input-referred spot-noise at 500 Hz in the LFP mode (1 Hz - 700 Hz) is 55 nV/root Hz while the integrated noise in the AP mode (200 Hz - 5 kHz) is 4.1 µVrms. The proposed front-end achieves sub-µW operation without penalizing other specifications such as input swing, common-mode or power-supply rejection ratios. It reduces the power consumption of neural front-ends with spectral selectivity by 6.1x and, compared with conventional wideband front-ends, it obtains a reduction of 2.5x.

Implementing Cryptographic Pairings on ARM dual-core Processors
R. Caiman, A. Cabrera and S. Sanchez-Solano
Journal Paper - IEEE Latin America Transactions, vol. 18, no. 2, pp 232-240, 2020
IEEE    DOI: 10.1109/TLA.2019.9082233    ISSN: 1548-0992    » doi
In this paper, we explore the parallelization capabilities of the ARM processing system embedded in a Zynq device for a software implementation of the optimal Ate pairing. First, the use of the NEON coprocessor was evaluated. It was found that on ARM v7 Cortex-A9 processors the computation of the optimal Ate pairing based on NEON does not perform better than an optimized ARM-assembly equivalent implementation. Therefore, we moved to explore the parallelization of pairing computation using a dual-core processing approach. By organizing operations of line evaluation and point arithmetic formulas to have little data dependency, it was possible to schedule independent operations to be perfomed simultaneously in separate cores of an ARM dual-core Cortex-A9 processor. The same principle was applied in the arithmetic procedures of the extension fields. In this way, our software is able to perform 25.6% and 6.6% faster than the best two implementations previously reported on ARM Cortex-A9 processors.

A comparative study of stacked-diode configurations operating in the photovoltaic region
R. Gómez-Merchán, D. Palomeque-Mangut, J.A. Leñero-Bardallo, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, first online, 2020
IEEE    DOI: 10.1109/JSEN.2020.2987393    ISSN: 1530-437X    » doi
This article presents a detailed comparative analysis of two possible stacked-diode configurations operating as solar cells. The performance of a single p-well - deep n-well diode is compared with the combination of such diode with a n-diff - pwell diode in parallel. Both configurations occupy the same area but offer different performance and, accordingly, they can have different application scopes. A test circuit to gauge the diodes performance and their spectral sensitivity has been integrated along with the two diode configurations in a 0.18 μm CMOS standard fabrication technology. The measured experimental results for the two diode configurations under study are validated with an analytical diode physical model.

On the use of causal feature selection in the context of machine-learning indirect test
M.J. Barragan, G. Leger, F. Cilici, E. Lauga-Larroze, S. Bourdel and S. Mir
Conference - Design Automation and Test in Europe DATE 2020
The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.

Feature selection and feature design for machine learning indirect test: a tutorial review
M.J. Barragan and G. Leger
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2020
Machine learning indirect test replaces costly specification measurements by simpler signatures and use modern learning algorithms to map these signatures to specifications. Defining a set of relevant signatures that appropriately captures the circuit performance degradation mechanisms is then a key point for enabling machine learning indirect test. In this tutorial we review some methodologies for selecting and designing such a set of information rich signatures.

Hybrid Phase Transition FET Devices for Logic Computation
M. Jiménez, J. Núñez and M.J. Avedillo
Journal Paper - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, first online, 2020
IEEE    DOI: 10.1109/JXCDC.2020.2993313    ISSN: 2329-9231    » doi
Hybrid Phase Transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON to OFF current ratio. In this paper, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ONOFF current tradeoffs are evaluated at circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, on the basis of this analysis, the paper proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained which were lower than those achieved with low standby power (LSTP) FinFETs and high performance (HP) FinFETs. The paper also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.

Improving the reliability of SRAM-based PUFs in the presence of aging
P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference - Design and Technology of Integrated Systems in Nanoscale Era DTIS 2019
The utilization of power-up values in SRAM cells for the generation of PUF responses has been widely studied. It is important that the cells used for this purpose are stable, i.e., the cells must have a strong tendency towards one of the two possible values (‘ ‘0 ’ or ‘1 ’). Some methods have been presented that aim at increasing the reliability of this type of PUFs by selecting the strongest cells among a set of them. However, they feature some drawbacks, either in terms of their practical feasibility or of their actual effectiveness selecting the strongest cells in different scenarios. In this work, the experimental results obtained for a new method to classify the cells according to their strength are presented and discussed. The technique overcomes some of the drawbacks that the previous methods present. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation, which translates into the construction of reliable SRAM-based PUFs.

Sun tracker sensor for attitude control of space navigation systems
A. de la Calle-Martos, R. Gómez-Merchán, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2020
We report a sun tracker sensor lor attitude conlrol 01 space navigation systems. The sensor exploits the concept 01 asynchronous operation previously devised by the authors lor those de vices. Asynchronous luminance sensors optimize sun trackers operation because only illuminated pixels are readout and can transmit data. This approach outperlorms classic Irame-based sun trackers in terms 01 bandwidth consumption, latency, and power consumption. The new sensor under study has been optimized lor operation and interaclion with other attitude control systems when it is embarked. The sensor power consumplion is quite reduced. To save power, its pixels enler automatically in standby mode after gauging illuminalion levels. The device operates with only 0.45V. The pixel matrix has been devised to optionally be direclly powered by energy harvesting syslems based on photovoltaic dio des connected lo a storage capacitor wilhout a DC-DC con verter.

Chaotic Image Encryption using Hopfield and Hindmarsh-Rose Neurons Implemented on FPGA
E. Tielo-Cuautle, J. Daniel Díaz-Muñoz, A.M. González-Zapata, R. Li, W.D. León-Salas, F.V. Fernández, O. Guillén-Fernández and I. Cruz-Vega
Journal Paper - Sensors, vol. 20, no. 5, article 1326, 2020
MDPI    DOI: 10.3390/s20051326    ISSN: 1424-8220    » doi
Chaotic systems implemented by artificial neural networks are good candidates for data encryption. In this manner, this paper introduces the cryptographic application of the Hopfield and the Hindmarsh-Rose neurons. The contribution is focused on finding suitable coefficient values of the neurons to generate robust random binary sequences that can be used in image encryption. This task is performed by evaluating the bifurcation diagrams from which one chooses appropriate coefficient values of the mathematical models that produce high positive Lyapunov exponent and Kaplan-Yorke dimension values, which are computed using TISEAN. The randomness of both the Hopfield and the Hindmarsh-Rose neurons is evaluated from chaotic time series data by performing National Institute of Standard and Technology (NIST) tests. The implementation of both neurons is done using field-programmable gate arrays whose architectures are used to develop an encryption system for RGB images. The success of the encryption system is confirmed by performing correlation, histogram, variance, entropy, and Number of Pixel Change Rate (NPCR) tests.

Synthesis of mm-Wave Wideband Receivers in 28nm CMOS Technology for Automotive Radar Applications
F. Passos, M. Chanca, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, first online, 2020
IEEE    DOI: 10.1109/TCAD.2020.2983363    ISSN: 0278-0070    » doi
A new strategy for millimeter-wave circuit and system synthesis, where the accuracy of electromagnetic simulations can be achieved in optimization-based design methodologies without sacrificing efficiency, is presented and tested within a real industrial project. This is done by properly partitioning the system, generating libraries of passive devices which are electromagnetically simulated prior to any circuit optimization, generating performance trade-offs at different hierarchical levels with multi-objective optimization algorithms and hierarchically composing lower level sub-blocks. With this proposed solution, an entire millimeter-wave system, from the passive component level up to the system level, has been designed and compared with the results obtained from a conventional design approach, demonstrating the outstanding capabilities of the methodology.

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