Publicaciones del IMSE

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Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4
M. Abernot, T. Gil, E. Kurylin, T. Hardelin, A. Magueresse,T. Gonos, M. Jiménez-Través, M.J. Avedillo de Juan and A. Todri-Sanial
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2022
resumen     

Neuromorphic computing aims to emulate biological neural functions to overcome the memory bottleneck challenges with the current Von Neumann computing paradigm by enabling efficient and low-power computations. In recent years, there has been a tremendous engineering effort to bring neuromorphic computing for processing at the edge. Oscillatory Neural Networks (ONNs) are braininspired neural networks made of oscillators to mimic neuronal brain waves, typically visible on Electroencephalograms (EEG). ONNs provide massive parallelism using coupled oscillators and low power computation using oscillator phase dynamics. In this paper, we present for the first time how to use ONNs to perform obstacle avoidance on a mobile robot. Digitally implemented ONNs on FPGA are used and configured for obstacle avoidance inside the industrial surveillance robot E4 from the company, A.I.Mergence. We show that ONNs can perform real-time obstacle avoidance based on the sensory data from proximity sensors embedded on the E4 robot. The highly parallel architecture of ONNs not only allows fast real-time computation for obstacle avoidance applications but also opens up a novel computing paradigm for edge AI to enable low power and real-time sensing to action computing.

Special Session on RF/5G Test
W.R. Eisenstadt, M. Roos, D. Morris, J.L. Gonzalez-Jimenez, C. Mounet, M.J. Barragan, G. Leger, F. Cilici, E. Lauga-Larroze, S. Mir, S. Bourdel, M. Margalef-Rovira, I. Alaji, H. Ghanem, G. Ducournau and C. Gaquiere
Conference · IEEE European Test Symposium ETS 2022
resumen     

Abstract not available

A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · Sensors, vol. 22, no. 17, article 6429, 2022
MDPI    ISSN: 1424-8220
resumen      doi      

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm(2). Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode-tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology's nominal supply, (2) residual charge-without passive discharging phase-was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

Hardware/Software Co-Design of a Circle Detection System based on Evolutionary Computing
L.F. Rojas-Munoz, H. Rostro-Gonzalez, C.H. Garcia-Capulin and S. Sanchez-Solano
Journal Paper · Electronics, vol. 11, no. 17, article 2686, 2022
MDPI    ISSN: 2079-9292
resumen      doi      

In recent years, the strategy of co-designing Hardware/Software (HW/SW) systems has been widely adopted to exploit the synergy between both approaches thanks to technological advances that have led to more powerful devices providing an increasingly better cost-benefit trade-off. This paper presents an HW/SW system for the detection of multiple circles in digital images based on a genetic algorithm. It is implemented on an Ultra96-v2 development board, which contains a Xilinx Zynq UltraScale+ MPSoC device and supports a Linux operating system that facilitates application development. The design is powered by developing an interactive computing environment by means of the Jupyter Notebook platform, in which different programming languages coexist. The specific advantages of each of these languages have been used to describe the hardware component that accelerates the evolutionary computation for circle detection (VHDL), to execute SW-HW interaction functions, as well as the pre- and post-processing of the images (ANSI-C) and to code, evaluate, and document the system execution process (Python). As a result, a computationally efficient application was obtained, with high accuracy in the detection of circles in synthetic and real images, and with a high degree of reconfigurability that provides the user with the necessary tools to incorporate it in a specific area of interest.

Addressing a New Class of Multi-Objective Passive Device Optimization for Radiofrequency Circuit Design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper · Electronics, vol. 11, no. 16, article 2624, 2022
MDPI    ISSN: 2079-9292
resumen      doi      

The design of radiofrequency circuits and systems lends itself to multi-objective optimization and the bottom-up composition of Pareto-optimal fronts. Conventional multi-objective optimization algorithms can effectively attain these fronts, which maximize or minimize a set of competing objective functions of interest. However, some of these real-life optimization problems reveal a non-conventional feature: there is one objective function that calls neither for minimization nor maximization. Instead, using the Pareto front demands this objective function to be swept across so that all its feasible values are available. Such a non-conventional feature, as shown here, emerges in the case of inductor optimization. The problem thus turns into a non-conventional one: determining how to find uniformly distributed feasible values of this function over the broadest possible range (typically unknown) while minimizing or maximizing the remaining competing objective functions. An NSGA-II-inspired algorithm is proposed that, based on the dynamic allocation of objective function slots and a modified dominance definition, can successfully return sets of solutions for inductor optimization problems with one sweeping objective. Furthermore, a mathematical benchmark function modeling this kind of problem is presented, which is also used to exhaustively test the proposed algorithm and obtain insight into its parameter settings.

Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs
P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper · IEEE Transactions on Electron Devices, first online, 2022
IEEE    ISSN: 0018-9383
resumen      doi      

The origin of some time-dependent variability phenomena in FET technologies has been attributed to the charge carrier trapping/detrapping activity of individual defects present in devices. Although some models have been presented to describe these phenomena from the so-called defect-centric perspective, limited attention has been paid to the complex process that goes from the experimental data of the phenomena up to the final construction of the model and all its components, specifically the one that pertains to the time constant distribution. This article presents a detailed strategy aimed at determining the defect time constant distribution, specifically tailored for small area devices, using data obtained from conventional characterization procedures.

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher
F.E. Potestad-Ordóñez, E. Tena-Sánchez, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and R. Chaves
Journal Paper · IEEE Access, vol. 10, pp 65548-65561, 2022
ISSN: 2169-3536
resumen      doi      

Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a significant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation.

Review of Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA
F.E. Potestad-Ordoñez, E. Tena-Sánchez, C. Fernández-García, V. Zúñiga-González, J.M. Mora Gutiérrez, C. Baena-Oliva, P. Parra-Fernández, A.J. Acosta-Jiménez and C.J. Jiménez-Fernández
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen     

In this paper, we present a review of the work [1]. In this work a complete setup to break ASIC implementations of standard Trivium stream cipher was presented. The setup allows to recover the secret keys combining the use of the active noninvasive technique attack of clock manipulation and Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.
[1] F.E. Potestad-Ordoñez, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernández, C.J. Jiménez-Fernández, "Breaking Trivium Stream Cipher Implemented in ASIC using Experimental Attacks and DFA". In Sensors, vol. 20, num. 6909, pp. 1-19, 2020.

Review of Gate-Level Hardware Countermeasure Comparison Against Power Analysis Attacks
E. Tena-Sánchez, F.E. Potestad-Ordoñez, V. Zúñiga-González, C. Fernández-García, J.M. Mora Gutiérrez, C.J. Jiménez-Fernández and A.J. Acosta-Jiménez
Conference · Jornadas Nacionales de Investigación en Ciberseguridad JNIC 2022
resumen     

In this paper, we present a review of the work [1]. The fast settlement of Privacy and Secure operations in the Internet of Things (IoT) is appealing the selection of mechanisms to achieve a higher level of security at the minimum cost and with reasonable performances. In recent years, dozens of proposals have been presented to design circuits resistant to Power Analysis attacks. In this paper a deep review of the state of the art of gate-level countermeasures against Power Analysis attacks has been done, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison.
[1] E. Tena-Sánchez, F.E. Potestad-Ordoñez, C.J. Jiménez-Fernández, A.J. Acosta and R. Chaves, "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks," Applied Sciences, 12(5), 2390, 2022.

Electronically Foveated Dynamic Vision Sensor
T. Serrano-Gotarredona, F. Faramarzi and B. Linares-Barranco
Conference · IEEE International Conference on Omni-Layer Intelligent Systems COINS 2022
resumen     

This paper proposed a vision system which implements a foveal mechanism to concentrate the attention and dynamically control the center and size of region of interest. The core of the system is an electronically-foveated dynamic vision sensor. An architecture and implementation of an electronically-foveated dynamic vision sensor is proposed. Simulation results demonstrating its operation are provided.
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