Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications
C. Frasser, P. Linares-Serrano, I.D. de los Rios, A. Moran, E.S. Skibinsky-Gitlin, J. Font-Rossello, V. Canals, M. Roca, T. Serrano-Gotarredona and J.L. Rossello
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, first online, 2022
IEEE ISSN: 2162-237X
Edge artificial intelligence (AI) is receiving a tremendous amount of interest from the machine learning community due to the ever-increasing popularization of the Internet of Things (IoT). Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical deep learning techniques such as convolutional neural networks (CNNs). In this work, we propose a power-and-area efficient architecture based on the exploitation of the correlation phenomenon in stochastic computing (SC) systems. The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by undesired correlation between signals, and the complexity of the stochastic maximum function implementation. To prove that our architecture meets the requirements of edge intelligence realization, we embed a fully parallel CNN in a single field-programmable gate array (FPGA) chip. The results obtained showed a better performance than traditional binary logic and other SC implementations. In addition, we performed a full VLSI synthesis of the proposed design, showing that it presents better overall characteristics than other recently published VLSI architectures.
The Influence of MPPT Algorithms in the Lifespan of the Capacitor Across the PV Array
A. Alcaide, R. Gomez-Merchan, E. Zafra, E.P. Martin, J.M. López-Rodriguez, J.I. Leon, S. Vazquez and L.G. Franquelo
Journal Paper · IEEE Access, vol. 10, pp 40945 - 40952, 2022
IEEE ISSN: 2169-3536
PV systems efficiency highly depends on the MPPT strategy to be implemented in the PV converter. Many MPPT methods on the literature are focused on improving the steady state and transient system performance extracting the maximum energy from the sun. In this paper, the impact of the MPPT methods in the PV converter is analyzed focusing the study on the capacitor across the PV array lifespan. The obtained results demonstrate that the low frequency PV voltage oscillations that are present in many MPPT methods have a large negative impact on this capacitor lifespan. Experimental and simulation results are presented in order to show that advanced MPPT methods, which avoid these low frequency oscillations, achieve higher capacitor lifespan values compared with the values obtained by applying well-known MPPT methods such as the perturb and observe or incremental conductance strategies.
Event Data Downscaling for Embedded Computer Vision
A. Gruel, J. Martinet, T. Serrano-Gotarredona and B. Linares-Barranco
Conference · International Conference on Computer Vision Theory and Applications VISAPP 2022
Event cameras (or silicon retinas) represent a new kind of sensor that measure pixel-wise changes in brightness and output asynchronous events accordingly. This novel technology allows for a sparse and energy-efficient recording and storage of visual information. While this type of data is sparse by definition, the event flow can be very high, up to 25M events per second, which requires significant processing resources to handle and therefore impedes embedded applications. Neuromorphic computer vision and event sensor based applications are receiving an increasing interest from the computer vision community (classification, detection, tracking, segmentation, etc.), especially for robotics or autonomous driving scenarios. Downscaling event data is an important feature in a system, especially if embedded, so as to be able to adjust the complexity of data to the available resources such as processing capability and power consumption. To the best of our knowledge, this works is the first attempt to formalize event data downscaling. In order to study the impact of spatial resolution downscaling, we compare several features of the resulting data, such as the total number of events, event density, information entropy, computation time and optical consistency as assessment criteria. Our code is available online at https://github.com/amygruel/EvVisu.
FeFETs for Phase Encoded Oscillatory based Computing
J. Núñez, M. Jiménez, B. Linares-Barranco and M.J. Avedillo
Conference · Design, Automation and Test in Europe DATE 2022
Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of Ferroelectric Field-Effect Transistor (FeFET) for such applications has recently been recognized, which is a step towards the physical realization given their ease of cointegration with commercial CMOS technologies. This paper investigates the design of oscillators using FeFETs and their potential for oscillator-based computing in which information is encoded in phase. As applications, we present the operation of FeFET coupled oscillators systems for graph coloring and Max-Cut problems, including subharmonic injection mechanism to discretize the phase in the second one.
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, J. Diaz-Fortuny, R. Castro, E. Roca and F.V. Fernandez
Conference · IEEE International Reliability Physics Symposium IRPS 2022
Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.
Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures
A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · IEEE International Conference on Microelectronic Test Structures ICMTS 2022
MemTorch: An Open-source Simulation Framework for Memristive Deep Learning Systems
C. Lammie, W. Xiang, B. Linares-Barranco and M.R. Azghadi
· Neurocomputing, vol. 485, pp.124-133, 2022
Memristive devices have shown great promise to facilitate the acceleration and improve the power efficiency of Deep Learning (DL) systems. Crossbar architectures constructed using these Resistive Random Access Memory (RRAM) devices can be used to efficiently implement various in-memory computing operations, such as Multiply Accumulate (MAC) and unrolled-convolutions, which are used extensively in Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs). However, memristive devices face concerns of aging and non-idealities, which limit the accuracy, reliability, and robustness of Memristive Deep Learning Systems (MDLSs), that should be considered prior to circuit-level realization. This Original Software Publication(OSP) presents MemTorch, an open-source1 framework for customized large-scale memristive Deep Learning (DL) simulations, with a refined focus on the co simulation of device non-idealities. MemTorch also facilitates co-modelling of key crossbar peripheral circuitry. MemTorch adopts a modernized software engineering methodology and integrates directly with the well-known PyTorch Machine Learning (ML) library.
Liquid State Machine on SpiNNaker for Spatio-Temporal Classification Tasks
A. Patino-Saucedo, H. Rostro-Gonzalez, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · Frontiers in Neuroscience, vol. 16, article 819063, 2022
FRONTIERS ISSN: 1662-453X
Liquid State Machines (LSMs) are computing reservoirs composed of recurrently connected Spiking Neural Networks which have attracted research interest for their modeling capacity of biological structures and as promising pattern recognition tools suitable for their implementation in neuromorphic processors, benefited from the modest use of computing resources in their training process. However, it has been difficult to optimize LSMs for solving complex tasks such as event-based computer vision and few implementations in large-scale neuromorphic processors have been attempted. In this work, we show that offline-trained LSMs implemented in the SpiNNaker neuromorphic processor are able to classify visual events, achieving state-of-the-art performance in the event-based N-MNIST dataset. The training of the readout layer is performed using a recent adaptation of back-propagation-through-time (BPTT) for SNNs, while the internal weights of the reservoir are kept static. Results show that mapping our LSM from a Deep Learning framework to SpiNNaker does not affect the performance of the classification task. Additionally, we show that weight quantization, which substantially reduces the memory footprint of the LSM, has a small impact on its performance.
Evaluation of a Vein Biometric Recognition System on an Ordinary Smartphone
P. López-González, I. Baturone, M. Hinojosa and R. Arjona
Journal Paper · Applied Sciences, vol. 12, no. 7, article 3522, 2022
MDPI ISSN: 2076-3417
Nowadays, biometrics based on vein patterns as a trait is a promising technique. Vein patterns satisfy universality, distinctiveness, permanence, performance, and protection against circumvention. However, collectability and acceptability are not completely satisfied. These two properties are directly related to acquisition methods. The acquisition of vein images is usually based on the absorption of near-infrared (NIR) light by the hemoglobin inside the veins, which is higher than in the surrounding tissues. Typically, specific devices are designed to improve the quality of the vein images. However, such devices increase collectability costs and reduce acceptability. This paper focuses on using commercial smartphones with ordinary cameras as potential devices to improve collectability and acceptability. In particular, we use smartphone applications (apps), mainly employed for medical purposes, to acquire images with the smartphone camera and improve the contrast of superficial veins, as if using infrared LEDs. A recognition system has been developed that employs the free IRVeinViewer App to acquire images from wrists and dorsal hands and a feature extraction algorithm based on SIFT (scale-invariant feature transform) with adequate pre- and post-processing stages. The recognition performance has been evaluated with a database composed of 1000 vein images associated to five samples from 20 wrists and 20 dorsal hands, acquired at different times of day, from people of different ages and genders, under five different environmental conditions: day outdoor, indoor with natural light, indoor with natural light and dark homogeneous background, indoor with artificial light, and darkness. The variability of the images acquired in different sessions and under different ambient conditions has a large influence on the recognition rates, such that our results are similar to other systems from the literature that employ specific smartphones and additional light sources. Since reported quality assessment algorithms do not help to reject poorly acquired images, we have evaluated a solution at enrollment and matching that acquires several images subsequently, computes their similarity, and accepts only the samples whose similarity is greater than a threshold. This improves the recognition, and it is practical since our implemented system in Android works in real-time and the usability of the acquisition app is high.
An Efficient TDC using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA
M. Parsakordasiabi, I. Vornicu, A. Rodriguez-Vazquez and R. Carmona-Galan
Journal Paper · IEEE Transactions on Instrumentation and Measurement, vol. 71, article 2000413, 2022
IEEE ISSN: 0018-9456
FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mode tapped-delay-line (TDL)-propagating 1's and 0's in alternating measurement cycles-architecture for a field-programmable gate array (FPGA)-based TDC that complies with the mentioned specifications. The dead-time of the proposed TDC is reduced to one system clock cycle by using a toggling input stage and a dual-mode counter-based encoder. To improve the TDC linearity, the TDL sampling sequence is tuned separately for each operating mode. The presented architecture employs a low-resources dual-mode combinatory encoder of one- and zero-counters to remove the bubbles and cover both operating modes. A dual-mode bin-width calibration has been carried out to improve the TDC performance in each mode. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. Experimental results have shown a differential nonlinearity (DNL) within [-0.71 1.05] least significant bit (LSB) and an integral nonlinearity (INL) within [-0.85 0.86] LSB for the propagation of 1's. DNL and INL are within [-0.73 1.06] LSB and [-1.17 0.04] LSB, respectively, for the propagation of 0's. The LSB size is 22.1 ps and the TDC precision is 22.35 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.