Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Securing Minutia Cylinder Codes for Fingerprints through Physically Unclonable Functions: An Exploratory Study
R. Arjona, M.A. Prada-Delgado, I. Baturone and A. Ross
Conference - International Conference on Biometrics ICB 2018
A number of personal devices, such as smartphones, have incorporated fingerprint recognition solutions for user authentication purposes. This work proposes a dual-factor fingerprint matching scheme based on P-MCCs (Protected Minutia Cylinder-Codes) generated from fingerprint images and PUFs (Physically Unclonable Functions) generated from device SRAMs (Static Random Access Memories). Combining the fingerprint identifier with the device identifier results in a secure template satisfying the discriminability, irreversibility, revocability, and unlinkability properties, which are strongly desired for data privacy and security. Experiments convey the benefits of the proposed dual-factor authentication mechanism in enhancing the security of personal devices that utilize biometric authentication schemes.

Dynamic range considerations for neural recording channels
M. Delgado-Restituto
Conference - IEEE CAS Singapore Chapter Workshop, 2018
Neural readout microelectronic interfaces are essential in implanted central nerve system prostheses aimed for brain-machine interfaces, the amelioration of disease effects, or the development of robotic mechanisms for the restitution/rehabilitation of abilities lost after injury or disease. Neural signals which can be recorded and used as biomarkers of the brain activity include local field potentials (LFPs) and action potentials (APs). They exhibit small amplitude (typically, below 1mV for LFPs and 100V for APs) and narrow band characteristics (0.5-200Hz for LFPs and 200Hz-7kHz for APs). A priori, these signals can be easily digitized with low-to-medium resolution ADCs, thus paving the way for neural prostheses with small area and power consumptions. However, along with the biomarkers, strong in band artifacts, which can be much larger that the signals of interest, may contaminate the recording or even preclude it altogether if the front-end saturates. Different causes can be at the origin of artifacts; for instance, they can be motion related or generated by electrical stimulations close to the recording sites. Coping with these large artifacts would demand for high dynamic range (of about 75dB) front-ends and data converters with large effective resolutions (beyond 13-14 bits). However, recent proposals for ADC resolution reduction techniques have demonstrated that modest ADCs can still be used for neural recording even in the presence of artifacts. This work reviews these proposals and also presents state-of-the-art techniques for the suppression of differential and common-mode artifacts from neural recordings.

Spiking Hough for Shape Recognition
P. Negri, T. Serrano-Gotarredona and B. Linares-Barranco
Book Chapter - Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, pp 425-432, 2018
SPRINGER    DOI: 10.1007/978-3-319-75193-1_51    ISBN: 978-3-319-75192-4    » doi
The paper implements a spiking neural model methodology inspired on the Hough Transform. On-line event-driven spikes from Dynamic Vision Sensors are evaluated to characterize and recognize the shape of Poker signs. The multi-class system, referred as Spiking Hough, shows the good performance on the public POKER-DVS dataset.

A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation
L.A. Camuñas-Mesa, Y.L. Domínguez-Cordero, A. Linares-Barranco, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 12, Article 63, 2018
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2018.00063    ISSN: 1662-4548    » doi
Convolutional Neural Networks (ConvNets) are a particular type of neural network often used for many applications like image recognition, video analysis or natural language processing. They are inspired by the human brain, following a specific organization of the connectivity pattern between layers of neurons known as receptive field. These networks have been traditionally implemented in software, but they are becoming more computationally expensive as they scale up, having limitations for real-time processing of high-speed stimuli. On the other hand, hardware implementations show difficulties to be used for different applications, due to their reduced flexibility. In this paper, we propose a fully configurable event-driven convolutional node with rate saturation mechanism that can be used to implement arbitrary ConvNets on FPGAs. This node includes a convolutional processing unit and a routing element which allows to build large 2D arrays where any multilayer structure can be implemented. The rate saturation mechanism emulates the refractory behavior in biological neurons, guaranteeing a minimum separation in time between consecutive events. A 4-layer ConvNet with 22 convolutional nodes trained for poker card symbol recognition has been implemented in a Spartan6 FPGA. This network has been tested with a stimulus where 40 poker cards were observed by a Dynamic Vision Sensor (DVS) in 1 s time. Different slow-down factors were applied to characterize the behavior of the system for high speed processing. For slow stimulus play-back, a 96% recognition rate is obtained with a power consumption of 0.85 mW. At maximum play-back speed, a traffic control mechanism downsamples the input stimulus, obtaining a recognition rate above 63% when less than 20% of the input events are processed, demonstrating the robustness of the network.

Practical Characterization of Cell-Electrode Electrical Models in Bio-Impedance Assays
J.A. Serrano, P. Pérez, A. Maldonado, M. Martín, A. Olmo, P. Daza, G. Huertas and A. Yúfera
Conference - International Conference on Biomedical Electronics and Devices BIODEVICES 2018
This paper presents the fitting process followed to adjust the parameters of the electrical model associated to a cell-electrode system in Electrical Cell-substrate Impedance Spectroscopy (ECIS) technique, to the experimental results from cell-culture assays. A new parameter matching procedure is proposed, under the basis of both, mismatching between electrodes and time-evolution observed in the system response, as consequence of electrode fabrication processes and electrochemical performance of electrode-solution interface, respectively. The obtained results agree with experimental performance, and enable the evaluation of the cell number in a culture, by using the electrical measurements observed at the oscillation parameters in the test circuits employed.

Monitoring Muscle Stem Cell Cultures with Impedance Spectroscopy
Y. Yuste, J.A. Serrano, A. Olmo, A. Maldonado-Jacobi, P. Pérez, G. Huertas, S. Pereira, F. de la Portilla and A. Yúfera
Conference - International Conference on Biomedical Electronics and Devices BIODEVICES 2018
The aim of this work is to present a new circuit for the real-time monitoring the processes of cellular growth and differentiation of skeletal myoblast cell cultures. An impedance spectroscopy Oscillation-Based technique is proposed for the test circuit, converting the biological system into a voltage oscillator, and avoiding the use of very high performance circuitry or equipment. This technique proved to be successful in the monitoring of cell cultures growth levels and could be useful for determining the degree of differentiation achieved, of practical implications in tissue engineering.

Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
S. Ahyoune, J. Sieiro, T. Carrasco, N. Vidal, J.M. López-Villegas, E. Roca and F.V. Fernández
Journal Paper - Integration, first online, 2018
ELSEVIER    DOI: 10.1016/j.vlsi.2018.02.006    ISSN: 0167-9260    » doi
In this work, a quasi-static implementation of the partial element equivalent circuit (PEEC) method for the analysis of planar radiofrequency (RF) and microwave (uW) components is proposed. The procedure is divided in three parts. First, an alternative PEEC formulation based on energy concepts is described. Second, a smart mesh generator is developed in order to provide an accurate solution at minimum computational costs, taking into account both geometry and device physics as metrics for the correct sizing of mesh elements. And third, a weighted combination of the 2D and 3D quasi-static Green's functions (GF) is proposed for extending the valid frequency range of the quasi-static approximation. It is shown that the 3D-GF is very accurate at low frequency, whereas the 2D-GF is more suitable at higher frequencies. Numerical examples are compared to experimental data for different passive components and technologies in a wide frequency range.

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Póvoa, A. Canelas, R. Castro-López, N. Horta and F.V. Fernández
Journal Paper - Integration, first online, 2018
ELSEVIER    DOI: 10.1016/j.vlsi.2018.02.005    ISSN: 0167-9260    » doi
In this paper a design strategy based on bottom-up design methodologies is used in order to systematically design a voltage controlled oscillator. The methodology uses two computer-aided design tools: AIDA, a multi-objective multi-constraint circuit optimization tool, and SIDe-O, a tool that characterizes and optimizes integrated inductors with high accuracy (around 1% when compared to electromagnetic simulations). By using such tools, the difficult trade-offs inherent to radio-frequency circuits can be explored efficiently and accurately. Furthermore, with the capability that AIDA has at considering process parameter variations during the optimization, the resulting methodology is able to obtain truly robust circuit designs.

Memristors fire away
B. Linares-Barranco
Journal Paper - Nature Electronics, vol. 1, no. 2, pp 100-101, 2018
NATURE    DOI: 10.1038/s41928-018-0028-x    ISSN: 2520-1131    » doi
Neuromorphic computing based on fully memristive neural networks could offer a scalable and lower-cost alternative to existing neural spiking chips based solely on CMOS technology.

VLSI Design of Trusted Virtual Sensors
M.C. Martínez-Rodríguez, M.A. Prada-Delgado, P. Brox and I. Baturone
Journal Paper - Sensors, vol. 18, no. 2, article 347, 2018
MDPI    DOI: 10.3390/s18020347    ISSN: 1424-8220    » doi
This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μs. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

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