Consejo Superior de Investigaciones Científicas · Universidad de Sevilla
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Noticias
Acoustic Noise Cancellation: Theory and Practice.
Bob Adams, Analog Devices Inc.
Towards an ultra low power photoplethysmography.
Javier Calpe, Analog Devices Inc..
26 Abril 2019
♦ Visitas al IMSE
IES Heliópolis.
21 Marzo 2019
♦ Defensa de Tesis Doctoral
Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.
Erica Tena Sánchez
11 Marzo 2019
♦ Seminario IMSE-Forum
Training programme of Project ACHIEVE-ITN on transferable skills oriented to PhD students. Seminars on Responsible Research and Innovation.
Open Science. Isabel Bernal, General Manager of Digital.CSIC.
Ethics in Scientific Research and Publication. Prof. Mª Ángeles Oviedo García, Dept. of Marketing and Market Research (University of Seville) and Mr. Nico Formanek, Dept. of Philosophy of Science and Technology of Computer Simulation (University of Sttutgart), and also the collaboration of Prof. Juan Manuel Durán through videoconference, TU Delft.
6 Marzo 2019

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Últimas publicaciones
Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization  »
Artificial Neural Networks (ANNs) show great performance in several data analysis tasks including visual and auditory applications. However, direct implementation of these algorithms without considering the sparsity of data requires high processing power, consume vast amounts of energy and suffer from scalability issues. Inspired by biology, one of the methods which can reduce power consumption and allow scalability in the implementation of neural networks is asynchronous processing and communication by means of action potentials, so-called spikes. In this work, we use the wellknown sigma-delta quantization method and introduce an easy and straightforward solution to convert an Artificial Neural Network to a Spiking Neural Network which can be implemented asynchronously in a neuromorphic platform. Briefly, we used asynchronous spikes to communicate the quantized output activations of the neurons. Despite the fact that our proposed mechanism is simple and applicable to a wide range of different ANNs, it outperforms the state-of-the-art implementations from the accuracy and energy consumption point of view. All source code for this project is available upon request for the academic purpose.

Conference - IEEE International Conference on Artificial Intelligence Circuits and Systems AICAS 2019
A. Yousefzadeh, S. Hosseini, P. Holanda, S. Leroux, T. Werner, T. Serrano-Gotarredona and B. Linares-Barranco, B. Dhoedt and P. Simoens
A Digital Neuromorphic Realization of the 2-D Wilson Neuron Model  »
This brief presents a piecewise linear approximation of the nonlinear Wilson (NW) neuron model for the realization of an efficient digital circuit implementation. The accuracy of the proposed piecewise Wilson (PW) model is examined by calculating time domain signal shaping errors. Furthermore, bifurcation analyses demonstrate that the approximation follows the same bifurcation pattern as the NW model. As a proof of concept, both models are hardware synthesized and implemented on field programmable gate arrays, demonstrating that the PW model has a range of neuronal behaviors similar to the NW model with considerably higher computational performance and a lower hardware overhead. This approach can be used in hardware-based large scale biological neural network simulations and behavioral studies. The mean normalized root mean square error and maximum absolute error of the PW model are 6.32% and 0.31%, respectively, as compared to the NW model.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 1, 2019 IEEE
DOI: 10.1109/TCSII.2018.2852598    ISSN: 1549-7747    » doi
M. Nouri, M. Hayati, T. Serrano-Gotarredona and D. Abbot
Compressive Imaging using RIP-compliant CMOS Imager Architecture and Landweber Reconstruction  »
In this paper we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in compressive sensing CMOS image sensors (CS-CIS) are recursive pseudo-random binary matrices. We have proved that the restricted isometry property (RIP) of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random numbers generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behaviour that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber (BCS-SPL) reconstruction algorithm. By means of single value decomposition (SVD) we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.

Journal Paper - IEEE Transactions on Circuits and Systems for Video Technology, first online, 2019 IEEE
DOI: 10.1109/TCSVT.2019.2892178    ISSN: 1051-8215    » doi
M. Trevisi, A. Akbari, M. Trocan, Á. Rodríguez-Vázquez and R. Carmona-Galán
Offset-calibration with Time-Domain Comparators using Inversion-mode Varactors  »
This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally-controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit SAR-ADC. The design, fabricated in a 0.18μm CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Brief, first online, 2019 IEEE
DOI: 10.1109/TCSII.2019.2904100    ISSN: 1549-7747    » doi
R. Fiorelli, M. Delgado-Restituto and A Rodríguez-Vázquez
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder  »
This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Journal Paper - International Journal of Circuit Theory and Applications, vol. 47, no. 3, pp 333-349, 2019 JOHN WILEY & SONS
DOI: 10.1002/cta.2594    ISSN: 0098-9886    » doi
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda

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