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Candidates sought for predoctoral contract (Formación de Personal Investigador-Research Personnel Training) associated with the HW-IDENTIoTY research project (Design of hardware solutions to manage people and things identities with trust, security and privacy in IoT ecosystem).
♦ Doctoral Thesis defense
Desarrollo y evaluación de arquitecturas lógicas basadas en nanopipeline.
Héctor J. Quintero Álvarez
July 17, 2018
Researchers at the IMSE-CNM Fabio Passos, Elisenda Roca, Rafael Castro and Francisco Fernández [et al.] have been recipient of the Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018) Best Paper Award.
July 5, 2018
♦ Doctoral Thesis defense
Design of Trusted Piecewise-Affine Controllers and Virtual Sensors into CMOS Integrated Circuits.
Macarena C. Martínez Rodríguez
June 25, 2018
Machine learning: when machines learn.
Luis A. Camuñas Mesa
May 17, 2018

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Recent publications
CMOS characterization and compact modelling for circuit reliability simulation  »
Abstract not avaliable

Conference - IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
J. Diaz Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Analysis of Body Bias and RTN-induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology  »
Abstract not avaliable

Conference - Int. Symposium on Power and Timing Modeling, Optimization and Simulation PATMOS 2018
E. Barajas, X. Aragones, D. Mateo, F. Moll, J. Martin-Martinez, R. Rodríguez, M. Portí, M. Nafria, R. Castro-López, E. Roca and F.V Fernández-Fernández
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs  »
This paper exposes the problematic issue of not considering device variability and layout parasitic effects in optimization-based design of radiofrequency integrated circuits. Therefore, in order to handle these issues, a new design methodology that performs an all-inclusive optimization is proposed, by taking into account the process variability, and, performing the complete layout automatically while performing an accurate parasitic extraction during the optimization for each candidate solution. Furthermore, the problematic inductor parasitics are also taken into account with EM-accuracy, by using a state-of-the-art surrogate modelling technique. The methodology was applied in the design and optimization of a low-noise amplifier, obtaining a set of extremely robust designs ready for fabrication.

Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Castro-López, R. Póvoa, A. Canelas, N. Horta and F.V. Fernández
Design considerations of an SRAM array for the statistical validation of time-dependent variability models  »
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs  »
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability but also the degradation due to time-dependent. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
A. Toro-Frías, P. Martín-Lloret, J. Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez

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Wednesday, 18 July 2018
Last update: 16.07.2018
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