While providing the same functionality, the various Deep Learning software frameworks available these days do not provide similar performance when running the same network model on a particular hardware platform. On the contrary, we show that the different coding techniques and underlying acceleration libraries have a great impact on the instantaneous throughput and CPU utilization when carrying out the same inference with Caffe, OpenCV, TensorFlow and Caffe2 on an ARM Cortex-A53 multi-core processor. Direct modelling of this dissimilar performance is not practical, mainly because of the complexity and rapid evolution of the toolchains. Alternatively, we examine how the hardware resources are distinctly exploited by the frameworks. We demonstrate that there is a strong correlation between inference performance - including power consumption - and critical parameters associated with memory usage and instruction flow control. This identified correlation is a preliminary step for the development of a simple empirical model. The objective is to facilitate selection and further performance tuning among the ever-growing zoo of deep neural networks and frameworks, as well as the exploration of new network architectures.

Conference - International Conference on Systems, Signals and Image Processing IWSSIP 2019

This special issue of the IEEE Transactions on Circuits and Systems - Part II: Express Briefs (TCAS-II) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS), held in Venice, Italy, on 29-30 August 2019. This is the second edition of this journal track symposium as part of the initiative of the IEEE Circuits and Systems Society (CASS), started in 2018. The symposium is focused on original works reporting hybrid, System-in-Package (SiP) or System-on-Chip (SoC) implementations of circuits and systems with state-of-the-art experimental results.

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 10, pp 1607-1607, 2019 IEEE
DOI: 10.1109/TCSII.2019.2935214    ISSN: 1549-7747    » doi

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal-Oxide-Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

Journal Paper - Materials, vol. 12, no. 7, article number 2745, 2019 MDPI AG
DOI: 10.3390/ma12172745    ISSN: 1996-1944    » doi

Blockchain technology can increase visibility in supply-chain transactions and lead to more accurate tracing of goods as well as provide evidence of whether a product is authentic or not. A shared, distributed ledger or blockchain alone, however, does not guarantee correct and trustworthy supply-chain traceability. We argue that blockchain technology (and any other digital traceability solution) must be enhanced with methods to "anchor" physical objects into information technology, Internet-of-Things and blockchain systems. Only when trust from the digital domain is extended to the physical domain can the movement of goods be accurately traced (e.g., for callbacks and provenance) and product authenticity determined. In this paper, we introduce the concept of crypto anchors, propose a classification and system architecture, and give implementation examples for different use cases and industries.

Journal Paper - IBM Journal of Research and Development, vol. 63, no. 2-3, article number 4, 2019 IBM CORP
DOI: 10.1147/JRD.2019.2900651    ISSN: 0018-8646    » doi

This paper studies the use of the body terminal as control voltage of ring oscillators implemented in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) processes, thus allowing a wider tuning range of the threshold voltage. This effect is exploited in this work to improve the linearity of Voltage-Controlled Ring Oscillators (VCROs) to be used as building blocks of Analog-to-Digital Converters (ADCs). An intuitive analysis of basic VCRO current-starved inverter cells is carried out in order to derive an approximate expression of the voltage-to-frequency characteristic. Electrical simulations in a 28-nm node are shown to get insight about the influence of main design parameters and applied to the design of VCRO-based Sigma-Delta (SD) ADCs up to the layout level, whose performance metrics demonstrate the benefits of the presented approach.

Conference - IEEE Midwest Symposium on Circuits and Systems MWSCAS 2019