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♦ Doctoral Thesis defense
Circuit design for biomedical laboratories based on bioimpedance measurement.
Pablo Peréz García
July 15, 2019
Bridging ICT and Medical Technologies for Smart Disease Diagnosis.
Myung Hoon Sunwoo, Ultra-small-sized Diagnostic and Smart Devices (uDSD) Research Center.
June 28, 2019  ·  10:00h.
The company Digilent Inc, in collaboration with the Seville Institute of Microelectronics and the Escuela Politécnica Superior of the Universidad de Sevilla will give the following workshops in June.
- Accelerate real-time high definition video processing designs with Digilent Zybo Z7, a Zynq-7000 AP SoC Platform and Xilinx Vivado HLS.
- Hands-on experimentation using Digilent Analog Discovery 2. Complete analog & digital circuits in or out of the lab.
June 17-18, 2019
♦ Mac Van Valkenburg Award 2019
Dr. Ángel Rodríguez Vázquez, researcher at the IMSE-CNM and professor at the Universidad de Sevilla, has been recipient of the Mac Van Valkenburg Award for fundamental contributions to mixed-signal chip architectures for smart imaging, vision and 2-D data processing. The award is based on the quality and significance of contribution, and continuity of technical leadership.. The awards ceremony will take place in the ISCAS 2019 Conference on May 28, 2019.

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Recent publications
Phase Synchronization Operator for on-chip Brain Functional Connectivity Computation  »
This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters and adders. The processor, fabricated in a 0.18μm CMOS process, only occupies and consumes 15nW from a 0.5V supply voltage at a signal input rate of 1024S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.

Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2019 IEEE
DOI: 10.1109/TBCAS.2019.2931799    ISSN: 1932-4545    » doi
M. Delgado-Restituto, J.B. Romaine and A. Rodriguez-Vazquez
Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs  »
The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due to their simplicity, a way to reduce the area occupied by the integrated electronics is the use of passive quenching circuits (PQCs) instead of active (AQCs) or mixed (MQCs) ones. However, the recharge phase in PQCs is slower, so the device can be retriggered before this phase ends. This paper studies the phenomena of afterpulsing and retriggering, depending on the characteristics of the SPADs and the working conditions. In order to do that, a test chip containing SPADs of different size has been characterized in several operating environments. A mathematical model has been proposed for fitting afterpulsing phenomenon. It is shown that retriggering can be also described in terms of this model, suggesting that it is linked to carriers trapped in the shallow levels of the semiconductor and that should be taken into account when considering the total amount of afterpulsing events.

Journal Paper - IEEE Sensor Journal, vol. 19, no. 14, pp 5700-5709, 2019 IEEE
DOI: 10.1109/JSEN.2019.2903937    ISSN: 1530-437X    » doi
M. Moreno-Garcia, L. Pancheri, M. Perenzonr, R. del Rio, O. Guerra-Vinuesa and A. Rodriguez-Vazquez
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC)  »
This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of papers selected from those presented at the 48th ESSCIRC Conference, held at Technische Universität Dresden, Dresden, Germany, during September 3-6, 2018.

Journal Paper - IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp 1827-1829, 2019 IEEE
DOI: 10.1109/JSSC.2019.2919403    ISSN: 0018-9200    » doi
A. Rodriguez-Vazquez, K. Sengupta and S. Rusu
Yield recovery of mm-wave power amplifiers using variable decoupling cells and one-shot statistical calibration  »
Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
F. Cilici, M.J. Barragan, S. Mir, E. Lauga-Larroze, S. Bourdel and G. Leger
A sub-μVRMS chopper front-end for ECOG recording  »
This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μVrms, with a noise floor below 50 nV/Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.

Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
N. Pérez-Prieto, J.L. Valtierra, M. Delgado-Restituto and A. Rodríguez-Vázquez

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Monday, 19 August 2019
Last update: 10.07.2019
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