In this paper, we analyze heterogeneous performance exhibited by some popular deep learning software frameworks for visual inference on a resource-constrained hardware platform. Benchmarking of Caffe, OpenCV, TensorFlow, and Caffe2 is performed on the same set of convolutional neural networks in terms of instantaneous throughput, power consumption, memory footprint, and CPU utilization. To understand the resulting dissimilar behavior, we thoroughly examine how the resources in the processor are differently exploited by these frameworks. We demonstrate that a strong correlation exists between hardware events occurring in the processor and inference performance. The proposed hardware-aware analysis aims to find limitations and bottlenecks emerging from the joint interaction of frameworks and networks on a particular CPU-based platform. This provides insight into introducing suitable modifications in both types of components to enhance their global performance. It also facilitates the selection of frameworks and networks among a large diversity of these components available these days for visual understanding.

Journal Paper - International Journal of Electrical and Computer Engineering Systems, vol. 11, no. 1, pp 1-11, 2020 FERIT
DOI: 10.32985/ijeces.11.1.1    ISSN: 1847-6996    » doi

This book describes a new design methodology that allows optimization-based synthesis of RF systems in a hierarchical multilevel approach, in which the system is designed in a bottom-up fashion, from the device level up to the (sub)system level. At each level of the design hierarchy, the authors discuss methods that increase the design robustness and increase the accuracy and efficiency of the simulations. The methodology described enables circuit sizing and layout in a complete and automated integrated manner, achieving optimized designs in significantly less time than with traditional approaches.
- Describes an efficient and accurate methodology to design automatically RF systems, with guaranteed accuracy from the device to the system level.
- Discusses analytical and machine learning techniques for modelling integrated inductors and uses such models in synthesis approaches.
- Compares synthesis strategies for RF circuits based on bottom-up versus flat approaches.
- Discusses layout-aware bottom-up design methodologies for RF circuits.
- Discusses variability-aware bottom-up design methodologies for RF circuits.
- Describes multilevel bottom-up design methodologies from the device up to the system level.

Book - 204 p, 2020 SPRINGER

ISBN: 978-30-3047-246-7    » link

Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope, and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account that problems associated with the inverse current of their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.

Journal Paper - IEEE Transactions on Nanotechnology, vol. 19, pp 500-507, 2020 IEEE
DOI: 10.1109/TNANO.2020.3004941    ISSN: 1536-125X    » doi

This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.

Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 3, pp 606-619,2020 IEEE
DOI: 10.1109/TBCAS.2020.2987389    ISSN: 1932-4545    » doi

This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration with negligible impact on the analog section. It reuses some of the capacitors in the array to also com-pensate the comparison offset, preventing redundancy interval saturation during the error measurement phase. The effec-tiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit split-CDAC SAR ADC case study.

Conference - IEEE International New Circuits and Systems Conference NEWCAS 2020