Spanish National Research Council · University of Seville
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♦ Call for Introduction to Research 2020 Scholarships
Call for proposals to 250 Introduction to Research scholarships for university students. General information and list of the research works offered for its realization at Seville Institute of Microelectronics.
General information »
Project list offered at the IMSE-CNM »
Deadline for submission: From March 9th to April 9th, both inclusive.
♦ Visits to the IMSE
Adharaz - Altasierra School.
February 21, 2020
Sixth grade students from the Colegio Público Huerta del Carmen in Seville have visited our center to interview the IMSE-CNM researcher Elisenda Roca, within the Wisibilízalas Contest, whose main objective is to give visibility to women working in the ICT field.
February 20, 2020
The IMSE-CNM researcher and professor at the Universidad de Sevilla Gloria Huertas, gives a talk entitled 'From the electron to the chip', within the program of activities of the XXX Spanish Olympiad of Physics .
Aula Magna Room of the Faculty of Physics (Seville)
February 7, 2020

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The World of Chips

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Recent publications
Demo: A system for image acquisition and processing operating in the visible and the IR bands  »
This demo displays an autonomous image acquisition and processing system that operates simultaneously with two image sensors either in the visible and the Long Wave Infrared Band (LWIR), inside the Infrared (IR) band. The entire system is controlled a Raspberry Pi board that allows to easily program image processing algorithms to process the images acquired with each sensor. It is a competitive alternative to conventional commercial closed systems with infrared cameras. The proposed imaging system can be easily adapted to different operation scenarios by adding new peripherals, sensors and full custom image processing algorithms.

Conference - International Conference on Distributed Smart Cameras ICDSC 2020
J.A. Lenero-Bardallo, J. Bernabeu-Wittel, J. Ceballos-Caceres and A. Rodriguez-Vazquez
Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage- Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs  »
This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks - such as switches, simple-stage transconductors and Voltage-Controlled Ring Oscillators (VCROs). Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor-level simulations of two VCRO-based ΣΔ modulators designed in a 28-nm FD-SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques.

Journal Paper - IEEE Transactions on Circuits and Systems I: Regular Papers, first online, 2020 IEEE
DOI: 10.1109/TCSI.2020.2978926    ISSN: 1549-8328    » doi
J. Ahmadi-Farsani, V. Zúñiga-González, T. Serrano-Gotarredona, B. Linares-Barranco and J.M. de la Rosa
Design and analysis of secure emerging crypto-hardware using HyperFET devices  »
The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications.

Journal Paper - IEEE Transactions on Emerging Topics in Computing, first online, 2020 IEEE
DOI: 10.1109/TETC.2020.2977735    ISSN: 2168-6750    » doi
I.M. Delgado Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Ready-to-Fabricate RF Circuit Synthesis using a Layout- and Variability-Aware Optimization-based Methodology  »
In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout-and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype.

Journal Paper - IEEE Access, first online, 2020 IEEE
DOI: 10.1109/ACCESS.2020.2980211    ISSN: 2169-3536    » doi
F. Passos, E. Roca, R. Martins, N. Lourenço, S. Ahyoune, J. Sieiro, R. Castro-Lopez, N. Horta and F.V. Fernandez
ASIC design and power characterization of standard and low power multi-radix Trivium  »
We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also described the mechanism for measuring power consumption in each Trivium implemented in the ASIC prototype. The clock tree of the ciphers has been designed in such a way that the clock signal of each Trivium can be cut independently. The experimental setup uses the Agilent 93000 testing system. The results show that the higher radix versions have a lower operating frequency and that the lower radix low-power versions have a very high power reduction. However, the Trivium radix-16 versions generate 16 bit/clock cycle so the measurements conclude that the MPLP version is the one with the lowest power consumption per bit (0.69 pJ/bit at 50 MHz.).

Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, first online, 2020 IEEE
DOI: 10.1109/TCSII.2020.2969242    ISSN: 1549-7747    » doi
J.M. Mora, C.J. Jiménez and M. Valencia

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Last update: 12.03.2020

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