SPIRS consortium
The results of the SPIRS project place Sevilla as a key in the development of security tools for ICT systems

The facilities of the Instituto de Microelectrónica de Sevilla, a joint research center of the Consejo Superior de Investigaciones Científicas CSIC) and the Universidad de Sevilla (US), host this June 1st the mid-term review of the SPIRS project (Secure Platform For ICT Systems Rooted at the Silicon Manufacturing Process).
June 1, 2023


Mas+Cara iniciative prize
Mas+Cara: Biometric recognition solutions with privacy and post-quantum security

On May 18, 2023, the Mas+Cara initiative won the 1st Prize of the XVIII US Entrepreneurship Ideas Contest, an initiative promoted by PDI (Teaching and Research Staff).
May 23, 2023


Microelectronics PERTE Commissioner visit
Visit of the Microelectronics PERTE Commissioner to the Instituto de Microelectrónica de Sevilla (IMSE-CNM)

The special commissioner of the Strategic Project for the Recovery and Economic Transformation of Microelectronics and Semiconductors, better known as PERTE CHIP, Mr. Jaime Martorell, visited the Instituto de Microelectrónica de Sevilla (IMSE-CNM), joint center of the Consejo Superior de Investigaciones Científicas (CSIC) and the Universidad de Sevilla.
May 18, 2023


First PTI Digital Science day
First PTI Digital Science day

The first assembly of the PTI Digital Science will take place on May 10, 2023 where all the participants of the platform will meet together with the companies and public administrations of interest in the auditorium of the Centro de Ciencias Humanas y Sociales (CCHS , CSIC) in Madrid.


European Commission selects QUBIP project
European Commission has selected the QUBIP project

European Commission has selected the QUBIP project to be funded in the HORIZON-CL3-2022-CS-01 call for Cluster 3 of the Horizon Europe program devoted to Civil Security for Society.
March 29, 2023


MSCA Postdoctoral Felloships 2022 selects SQPRIM project
The prestigious MSCA Postdoctoral Fellowships 2022 program has selected the SQPRIM project

The prestigious MSCA Postdoctoral Fellowships 2022 program has selected the SQPRIM project presented by Dr. David Martín Sánchez under the supervision of Dr. Piedad Brox Jiménez.
March 28, 2023



New Director of the IMSE-CNM

IMSE researcher Teresa Serrano Gotarredona has been appointed as the new Director of the Instituto de Microelectrónica de Sevilla.


Education at IMSE

- Doctoral Studies
- Master Studies
- Degree Studies
- Final Degree Projects
- Internships


Recent publications

Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 7, no.2, article 29, 2023
MDPI    ISSN: 2410-387X
abstract      doi      

The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30-45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 23, no. 8, article 4070, 2023
MDPI    ISSN: 1424-8220
abstract      doi      

The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.


A Pipelining-Based Heterogeneous Scheduling and Energy-Throughput Optimization Scheme for CNNs Leveraging Apache TVM
D. Velasco-Montero, B. Goossens, J. Fernández-Berni, Á. Rodríguez-Vázquez and W. Philips
Journal Paper · IEEE Access, 2023
IEEE    ISSN: 2169-3536
abstract      doi      

Extracting information of interest from continuous video streams is a strongly demanded computer vision task. For the realization of this task at the edge using the current de-facto standard approach, i.e., deep learning, it is critical to optimize key performance metrics such as throughput and energy consumption according to prescribed application requirements. This allows achieving timely decision-making while extending the battery lifetime as much as possible. In this context, we propose a method to boost neural-network performance based on a co-execution strategy that exploits hardware heterogeneity on edge platforms. The enabling tool is Apache TVM, a highly efficient machine-learning compiler compatible with a diversity of hardware back-ends. The proposed approach solves the problem of network partitioning and distributes the workloads to make concurrent use of all the processors available on the board following a pipeline scheme. We conducted experiments on various popular CNNs compiled with TVM on the Jetson TX2 platform. The experimental results based on measurements show a significant improvement in throughput with respect to a single-processor execution, ranging from 14% to 150% over all tested networks. Power-efficient configurations were also identified, accomplishing energy reductions above 10%.

Band-Pass Sigma-Delta Modulation: The Path towards RF-to-Digital Conversion in Software-Defined Radio
J.M. de la Rosa
Journal Paper · Chips, vol. 2 no. 1, articles 44-69, 2023
MDPI    ISSN: 2674-0729
abstract      doi      

This paper reviews the state of the art on bandpass sigma-delta modulators (BP-sigma-deltaMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-sigma-deltaM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.


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What we do

Our main area of specialization is the design of CMOS analog and mixed-signal integrated circuits and their use in different application contexts such as wireless communications, data conversion, smart imagers & vision sensors, biomedical devices, cybersecurity, neuromorphic computing and space technologies.

The IMSE-CNM staff consists of approximately one hundred people, including scientists and support personnel. IMSE-CNM employees are involved in advancing scientific knowledge, designing high level scientific-technical solutions and in technology transfer.


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