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PVT-robust CMOS programmable chaotic oscillator: Synchronization of two 7-scroll attractors
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, C. Sanchez-Lopez and F.V. Fernandez-Fernandez
Journal Paper - Electronics, vol. 7, no. 10, article 252, 2018
MDPI    DOI: 10.3390/electronics7100252    ISSN: 2079-9292    » doi
[abstract]
Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2-7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μm CMOS technology. Post-layout and process-voltage-temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master-slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

FPGA design example for maximum operating frequency measurements
C.J. Fernandez, P.P. Fernandez, C.B. Oliva, M.V. Barrero and F.E. Potestad-Ordoñez
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
[abstract]
The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it is presented with a low complexity, it is not possible to do it in a single practice session. This paper presents, as a demonstrator, the design at RT level and its implementation in FPGA of a digital system that uses the Trivium flow cipher and on which measurements of maximum operating frequency are made. This circuit is designed in three laboratory sessions of about two hours each.

Distance measurement as a practical example of FPGA design
C.J. Fernandez, P.P. Fernandez, C.B. Oliva, M.V. Barrero and F.E. Potestad-Ordoñez
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
[abstract]
Digital design learning at the RT level requires practical examples and as learning progresses, the examples need to become more complex. FPGAs and development boards offer a very suitable platform for the implementation of these designs. However, classroom practice sessions usually last two hours, which does not allow the complexity of the designs be high enough. For this reason, interesting designs that can be made in several sessions are required In this paper, the construction of a distance measuring system is presented as a demonstrator. For this purpose, a distance measurement module based on ultrasound is available and the results are displayed in 7-segment displays on a Nexys4 board.

On-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camera
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galan and A. Rodríguez-Vázquez
Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018
DOI: 10.1145/3243394.3243705    » doi
[abstract]
This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image recognition on deep neural networks. Both the hardware configuration and the network model can be changed any time on the fly. Up to 24 hardware-model combinations are possible, enabling dynamic reconfiguration according to prescribed application requirements.

On practical issues for stochastic STDP hardware with 1-bit synaptic weights
A. Yousefzadeh, E. Stromatias, M. Soto, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 12, article 665, 2018
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2018.00665    ISSN: 1662-4548    » doi
[abstract]
In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

A comparison of automated RF circuit design methodologies: online vs. offline passive component design
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Journal Paper - IEEE Transactions on Very Large Scale Integration Systems, vol. 26, no. 11, pp 2386-2394, 2018
IEEE    DOI: 10.1109/TVLSI.2018.2859827    ISSN: 1063-8210    » doi
[abstract]
In this paper, surrogate modeling techniques are applied for passive component modeling. These techniques are exploited to develop and compare two alternative strategies for automated radio-frequency circuit design. The first one is a traditional approach where passive components are designed during the optimization stage. The second one, inspired on bottom-up circuit design methodologies, builds passive component Pareto-optimal fronts (POFs) prior to any circuit optimization. Afterward, these POFs are used as an optimized library from where the passive components are selected. This paper exploits the advantages of evolutionary computation algorithms in order to efficiently explore the circuit design space, and the accuracy and efficiency of surrogate models to model passive components.

Optimum Network/Framework Selection from High-Level Specifications in Embedded Deep Learning Vision Applications
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - Lecture Notes in Computer Science LNCS, vol. 11182, pp 369-379, 2018
SPRINGER    DOI: 10.1007/978-3-030-01449-0_31    ISSN: 0302-9743    » doi
[abstract]
This paper benchmarks 16 combinations of popular Deep Neural Networks and Deep Learning frameworks on an embedded platform. A Figure of Merit based on high-level specifications is introduced. By sweeping the relative weight of accuracy, throughput and power consumption on global performance, we demonstrate that only a reduced set of the analyzed combinations must actually be considered for real deployment. We also report the optimum network/framework selection for all possible application scenarios defined in those terms, i.e. weighted balance of the aforementioned parameters. Our approach can be extended to other networks, frameworks and performance parameters, thus supporting system-level design decisions in the ever-changing ecosystem of Deep Learning technology.

Trusted Cameras on Mobile Devices Based on SRAM Physically Unclonable Functions
R. Arjona, M.A. Prada-Delgado, J. Arcenegui and I. Baturone
Journal Paper - Sensors, vol. 18, no. 10, art, 3352, 2018
MDPI    DOI: 10.3390/s18103352    ISSN: 1424-8220    » doi
[abstract]
Nowadays, there is an increasing number of cameras placed on mobile devices connected to the Internet. Since these cameras acquire and process sensitive and vulnerable data in applications such as surveillance or monitoring, security is essential to avoid cyberattacks. However, cameras on mobile devices have constraints in size, computation and power consumption, so that lightweight security techniques should be considered. Camera identification techniques guarantee the origin of the data. Among the camera identification techniques, Physically Unclonable Functions (PUFs) allow generating unique, distinctive and unpredictable identifiers from the hardware of a device. PUFs are also very suitable to obfuscate secret keys (by binding them to the hardware of the device) and generate random sequences (employed as nonces). In this work, we propose a trusted camera based on PUFs and standard cryptographic algorithms. In addition, a protocol is proposed to protect the communication with the trusted camera, which satisfies authentication, confidentiality, integrity and freshness in the data communication. This is particularly interesting to carry out camera control actions and firmware updates. PUFs from Static Random Access Memories (SRAMs) are selected because cameras typically include SRAMs in its hardware. Therefore, additional hardware is not required and security techniques can be implemented at low cost. Experimental results are shown to prove how the proposed solution can be implemented with the SRAM of commercial Bluetooth Low Energy (BLE) chips included in the communication module of the camera. A proof of concept shows that the proposed solution can be implemented in low-cost cameras.

Guest Editorial Special Issue on the 2018 ISICAS: A CAS Journal Track Symposium
J.M. de la Rosa, E. Bonizzoni and F. Maloberti
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 10, pp 1289-1289, 2018
IEEE    DOI: 10.1109/TCSII.2018.2862988    ISSN: 1549-7747     » doi
[abstract]
This special issue of the IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS), held in Taormina, Italy, on 2-3 September 2018. This is the first edition of this symposium and a new initiative of the IEEE Circuits and Systems Society (CASS), which includes a selection of original works in very diverse areas of integrated circuits and systems, describing integrated implementations with experimental results. In contrast to conventional symposia and conferences, ISICAS is a Journal Track Symposium which does not produce proceedings. Instead, the works presented at the conference are published in two journal special issues. One of them is the issue that you are holding and the other one is a special issue of the IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I). The technical program of the conference is therefore made up of those papers which has been accepted for publication in these special issues of TCAS-I and TCAS-II.

Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper - IEEE Electron Device Letters, first online, 2018
IEEE    DOI: 10.1109/LED.2018.2871855    ISSN: 0741-3106    » doi
[abstract]
Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.

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