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Optimal Localist and Distributed Coding of Spatiotemporal Spike Patterns Through STDP and Coincidence Detection
T. Masquelier and S.R. Kheradpisheh
Journal Paper - Frontiers in Neuroscience, vol. 12, Article 74, 2018
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fncom.2018.00074    ISSN: 1662-4548    » doi
[abstract]
Repeating spatiotemporal spike patterns exist and carry information. Here we investigated how a single spiking neuron can optimally respond to one given pattern (localist coding), or to either one of several patterns (distributed coding, i.e., the neuron's response is ambiguous but the identity of the pattern could be inferred from the response of multiple neurons), but not to random inputs. To do so, we extended a theory developed in a previous paper (Masquelier, 2017), which was limited to localist coding. More specifically, we computed analytically the signal-to-noise ratio (SNR) of a multi-pattern-detector neuron, using a threshold-free leaky integrate-and-fire (LIF) neuron model with non-plastic unitary synapses and homogeneous Poisson inputs. Surprisingly, when increasing the number of patterns, the SNR decreases slowly, and remains acceptable for several tens of independent patterns. In addition, we investigated whether spike-timing-dependent plasticity (STDP) could enable a neuron to reach the theoretical optimal SNR. To this aim, we simulated a LIF equipped with STDP, and repeatedly exposed it to multiple input spike patterns, embedded in equally dense Poisson spike trains. The LIF progressively became selective to every repeating pattern with no supervision, and stopped discharging during the Poisson spike trains. Furthermore, tuning certain STDP parameters, the resulting pattern detectors were optimal. Tens of independent patterns could be learned by a single neuron using a low adaptive threshold, in contrast with previous studies, in which higher thresholds led to localist coding only. Taken together these results suggest that coincidence detection and STDP are powerful mechanisms, fully compatible with distributed coding. Yet we acknowledge that our theory is limited to single neurons, and thus also applies to feed-forward networks, but not to recurrent ones.

Guest editorial special issue on computational image sensors and smart camera hardware
J. Fernández-Berni, R. Carmona-Galán, G. Sicard and A. Dupret
Journal Paper - International Journal of Circuit Theory and Applications, first online, 2018
JOHN WILEY & SONS    DOI: 10.1002/cta.2551    ISSN: 0098-9886    » doi
[abstract]
Recent advances in both software and hardware technologies are enabling the emergence of vision as a key sensorial modality in various application scenarios. Concerning hardware, all of the components along the signal chain play a significant role when it comes to implementing smart vision-enabled systems. At the front end, new circuit structures for sensing, processing, and signal conditioning are adding functionalities in CMOS imagers beyond the mere generation of 2-D intensity maps. Moreover, the development of vertical integration technologies is facilitating monolithic realizations of visual sensors where the incorporation of computational capabilities has no impact at all on image quality. Typically, the outcome of the front-end device in a smart camera will be a preprocessed flow of information ready for further efficient analysis. At this point, specific ICs known as vision processing units can be inserted to accelerate the processing flow according to the targeted application. On the other hand, reconfigurability is a valuable asset in the ever-changing field of vision. FPGAs leverage cutting-edge digital technologies to offer flexible hardware for exploration of different memory arrangements, data flows, and processing parallelization. It is precisely parallelization for which GPUs constitute an interesting alternative in smart cameras when massive pixel-level operation is required. This is the case of state-of-the-art vision algorithms based on convolutional neural networks. At higher level, DSPs and multicore CPUs make software development notably easier at the cost of losing hardware specificity. Overall, this special issue aims at covering some of the latest research works in the vast ecosystem of hardware for artificial vision.

Fast luminance measurement method for asynchronous spiking pixels
J.A. Leñero-Bardallo and F.J. García-Pacheco
Journal Paper - Electronics Letters, vol. 54, no. 8, pp 492-494, 2018
IET    DOI: 10.1049/el.2017.3834    ISSN: 0013-5194    » doi
[abstract]
A new method to obtain a continuous and fast measurement of light intensity is presented. It is targeted for Integrate and Fire pixels that pulse with a frequency proportional to illumination. The procedure is intended to speed up the pixel readout of low illuminated pixels. It does not require synchronisation of different digital signals, being compatible with continuous pixel operation. The fundamentals of this method are described. Experimental results validating the theory are provided.

Methodology to improve the model of series inductance in CMOS integrated inductors
E.F. Gutierrez-Frias, L.A. García-Lugo, E.C. Becerra-Alvarez, J.J. Raygoza-Panduro, J.M. de la Rosa and E.B. Ortega-Rosales
Journal Paper - Journal of Electrical Engineering, vol. 69, no. 3, pp 250-254, 2018
HANS PUBLISHERS    ISSN: 1335-3632    
[abstract]
This paper presents a systematic optimization methodology to achieve an accurate estimation of series inductance of inductors implemented in standard CMOS technologies. Proposed method is based on an optimization procedure which aims to obtain adjustment factors associated to main physical inductor characteristics, allowing to estimate more accurate series inductance values that can be used in design stage. Experimental measurements of diverse square inductor geometries are shown and compared with previous approaches in order to demonstrate and validate presented approach.

Remote Cell Growth Sensing using Self-Sustained Bio-Oscillations
P. Pérez, G. Huertas, A. Olmo, A. Maldonado-Jacobi, J. Serrano, M. Martín, P. Daza and A. Yúfera
Journal Paper - Sensors, vol. 18, no. 8, art. 2550, 2018
MDPI    DOI: 10.3390/s18082550    ISSN: 1424-8220    » doi
[abstract]
A smart sensor system for cell culture real-time supervision is proposed, allowing for a significant reduction in human effort applied to this type of assay. The approach converts the cell culture under test into a suitable "biological" oscillator. The system enables the remote acquisition and management of the "biological" oscillation signals through a secure web interface. The indirectly observed biological properties are cell growth and cell number, which are straightforwardly related to the measured bio-oscillation signal parameters, i.e., frequency and amplitude. The sensor extracts the information without complex circuitry for acquisition and measurement, taking advantage of the microcontroller features. A discrete prototype for sensing and remote monitoring is presented along with the experimental results obtained from the performed measurements, achieving the expected performance and outcomes.

Applications of event-based image sensors -Review and analysis
J.A. Leñero-Bardallo, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - International Journal of Circuit Theory and Applications, first online, 2018
JOHN WILEY & SONS    DOI: 10.1002/cta.2546    ISSN: 0098-9886    » doi
[abstract]
The spread of event-driven asynchronous vision sensors during the last years has increased significantly the industrial interest and the application scenarios for them. This article reviews the main fields of application that event-based image sensors have found during the last 20 years. We focus in the description of applications where such devices can outperform conventional frame-based sensors. The practical functions of the three main families of asynchronous event-based sensors are analyzed. The article also studies what are the factors that increase nowadays the demand of sensors that minimize the power and bandwidth consumption. Moreover, the technological factors that have facilitated the development of asynchronous sensors are discussed.

Sigma-Delta Converters: Practical Design Guide, 2nd Edition
J.M. de la Rosa
Book - 568 p, 2018
WILEY-IEEE PRESS    ISBN: 978-1-119-27576-3    » link
[abstract]
Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), ΣΔMs cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications.
Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators -from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art ΣΔMs. It makes more emphasis on two key points, which were not treated so deeply in the first edition:
- It includes a more detailed explanation of ΣΔMs implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations.
- It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of ΣΔ converters.
Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style.

A 0.9-V 100-μW Feedforward Adder-Less Inverter-based MASH ΔΣ Modulator with 91-dB Dynamic Range and 20-kHz Bandwidth
M. Honarparvar, J.M. de la Rosa and M. Sawan
Conference - International Symposium on Integrated Circuits and Systems ISICAS 2018
[abstract]
A 0.9-V ΔΣ modulator integrated into a 0.18-μm 2 CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (multistage noise shaping) architecture based on an adder-less feedforward structure is proposed. The proposed modulator has a unity signal transfer function in both stages of the modulator in order to reduce the integrator´s output swings. To mitigate the failure of slow process corner in the weak inversion as well as to further diminish the power consumption of the presented modulator, a fully differential self- and bulk-biased inverter based operational transconductance amplifier is proposed. Experimental results are shown to demonstrate the efficiency of the proposed ΔΣ converter, showing state-of-the-art performance, by featuring 88.7-dB signal-to-noise ratio, 86.4-dB signal-to-noise plus distortion ratio, and 91-dB dynamic range within a signal bandwidth of 20 kHz, with a power dissipation of 103.4 μW when the circuit is clocked at 5.12 MHz.

Optimum Network/Framework Selection from High-Level Specifications in Embedded Deep Learning Vision Applications
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Advanced Concepts for Intelligent Vision Systems ACIVS 2018
[abstract]
This paper benchmarks 16 combinations of popular Deep Neural Networks and Deep Learning frameworks on an embedded platform. A Figure of Merit based on high-level specifications is introduced. By sweeping the relative weight of accuracy, throughput and power consumption on global performance, we demonstrate that only a reduced set of the analyzed combinations must actually be considered for real deployment. We also report the optimum network/framework selection for all possible application scenarios defined in those terms, i.e. weighted balance of the aforementioned parameters. Our approach can be extended to other networks, frameworks and performance parameters, thus supporting system-level design decisions in the ever-changing ecosystem of Deep Learning technology.

SIS20: A CMOS ASIC for Solar Irradiance Sensors in Mars Surface
D. Vázquez, J. Ceballos and S. Espejo
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
[abstract]
This paper reports the design and characterization of the ASIC SIS20, planned for an instrument aimed to measure Solar Irradiance on the surface of Mars. It has been designed using the AMS0.35u CMOS technology and with the rad-hard digital library developed at IMSE (Spain). The ASIC is intended for flying with the ExoMars2020 mission.

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