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CMOS characterization and compact modelling for circuit reliability simulation
J. Diaz Fortuny, J. Martin-Martinez, R. Rodriguez, M. Nafria, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference - IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
[abstract]
Abstract not avaliable

Analysis of Body Bias and RTN-induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology
E. Barajas, X. Aragones, D. Mateo, F. Moll, J. Martin-Martinez, R. Rodríguez, M. Portí, M. Nafria, R. Castro-López, E. Roca and F.V Fernández-Fernández
Conference - Int. Symposium on Power and Timing Modeling, Optimization and Simulation PATMOS 2018
[abstract]
Abstract not avaliable

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs
F. Passos, R. Martins, N. Lourenço, E. Roca, R. Castro-López, R. Póvoa, A. Canelas, N. Horta and F.V. Fernández
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
This paper exposes the problematic issue of not considering device variability and layout parasitic effects in optimization-based design of radiofrequency integrated circuits. Therefore, in order to handle these issues, a new design methodology that performs an all-inclusive optimization is proposed, by taking into account the process variability, and, performing the complete layout automatically while performing an accurate parasitic extraction during the optimization for each candidate solution. Furthermore, the problematic inductor parasitics are also taken into account with EM-accuracy, by using a state-of-the-art surrogate modelling technique. The methodology was applied in the design and optimization of a low-noise amplifier, obtaining a set of extremely robust designs ready for fabrication.

Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs
A. Toro-Frías, P. Martín-Lloret, J. Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability but also the degradation due to time-dependent. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low.

A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation
J. Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-Lopez, J. Martin-Martinez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by timedependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of aging device effects for reliability circuit

Automated massive RTN characterization using a transistor array chip
P. Saraza-Canflanca, J. Diaz-Fortuny, A. Toro-Frias, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
In this work, a CMOS transistor array for the massive measurement of random telegraph noise (RTN), together with a dedicated experimental setup, is presented. The array chip, called ENDURANCE, allows the massive characterization of the RTN parameters needed for a complete understanding of the phenomenon. Additionally, some experimental results are presented that demonstrate the convenience of the setup.

On the analysis and detection of flames with an asynchronous spiking image sensor
J.A. Leñero-Bardallo, J.M. Guerrero-Rodríguez, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, first online, 2018
ELSEVIER    DOI: 10.1109/JSEN.2018.2851063    ISSN: 1530-437X    » doi
[abstract]
We have investigated the capabilities of a custom asynchronous spiking image sensor operating in the Near Infrared (NIR) band to study flame radiation emissions, monitor their transient activity, and detect their presence. Asynchronous sensors have inherent capabilities, i.e. good temporal resolution, high dynamic range, and low data redundancy. This makes them competitive against Infrared (IR) cameras and CMOS frame-based NIR imagers. In the article, we analyze, discuss and compare the experimental data measured with our sensor against results obtained with conventional devices. A set of measurements have been taken to study the flame emission levels and their transient variations. Moreover, a flame detection algorithm, adapted to our sensor asynchronous outputs, has been developed. Results show that asynchronous spiking sensors have an excellent potential for flame analysis and monitoring.

Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Periniolla, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Microelectronic Engineering, first online, 2018
ELSEVIER    DOI: 10.1016/j.mee.2018.06.011    ISSN: 0167-9317    » doi
[abstract]
Neuromorphic RRAM circuits typically need currents of several mA when many binary memristive devices are activated at the same time. This is due to the low resistance state of these devices, which increases the power consumption and limits the scalability. To overcome this limitation, it is vital to investigate how to minimize the amplitude of the read-out inference pulses sent through the crossbar lines. However, the amplitude of such inference voltage pulses will become limited by the offset voltage of read-out circuits. This paper presents a three-stage calibration circuit to compensate for offset voltage in the wordlines of a memristor-array read-out system. The proposed calibration scheme is based on adjusting the bulk voltage of one of the input differential pair MOSFETs by means of a switchable cascade of resistor ladders. This renders the possibility to obtain calibration voltage steps less than 0.1mV by cascading a few number of stages, whose results are only limited by mismatch, temperature, electrical noise and other fabrication defects. The system is built using HfO2-based binary memristive synaptic devices on top of a 130-nm CMOS technology. Layout-extracted simulations considering technology corners, PVT variations and electrical noise are shown to validate the presented calibration scheme.

Active Perception with Dynamic Vision Sensors. Minimum Saccades with Optimum Recognition
A. Yousefzadeh, G. Orchard, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, first online, 2018
IEEE    DOI: 10.1109/TBCAS.2018.2834428    ISSN: 1932-4545    » doi
[abstract]
Vision processing with dynamic vision sensors (DVSs) is becoming increasingly popular. This type of a bio-inspired vision sensor does not record static images. The DVS pixel activity relies on the changes in light intensity. In this paper, we introduce a platform for the object recognition with a DVS in which the sensor is installed on a moving pan-tilt unit in a closed loop with a recognition neural network. This neural network is trained to recognize objects observed by a DVS, while the pan-tilt unit is moved to emulate micro-saccades. We show that performing more saccades in different directions can result in having more information about the object, and therefore, more accurate object recognition is possible. However, in high-performance and low-latency platforms, performing additional saccades adds latency and power consumption. Here, we show that the number of saccades can be reduced while keeping the same recognition accuracy by performing intelligent saccadic movements, in a closed action-perception smart loop. We propose an algorithm for smart saccadic movement decisions that can reduce the number of necessary saccades to half, on average, for a predefined accuracy on the N-MNIST dataset. Additionally, we show that by replacing this control algorithm with an artificial neural network that learns to control the saccades, we can also reduce to half the average number of saccades needed for the N-MNIST recognition.

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