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Performance Assessment of Deep Learning Frameworks through Metrics of CPU Hardware Exploitation on an Embedded Platform
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - International Journal of Electrical and Computer Engineering Systems, vol. 11, no. 1, pp 1-11, 2020
FERIT    DOI: 10.32985/ijeces.11.1.1    ISSN: 1847-6996    » doi
[abstract]
In this paper, we analyze heterogeneous performance exhibited by some popular deep learning software frameworks for visual inference on a resource-constrained hardware platform. Benchmarking of Caffe, OpenCV, TensorFlow, and Caffe2 is performed on the same set of convolutional neural networks in terms of instantaneous throughput, power consumption, memory footprint, and CPU utilization. To understand the resulting dissimilar behavior, we thoroughly examine how the resources in the processor are differently exploited by these frameworks. We demonstrate that a strong correlation exists between hardware events occurring in the processor and inference performance. The proposed hardware-aware analysis aims to find limitations and bottlenecks emerging from the joint interaction of frameworks and networks on a particular CPU-based platform. This provides insight into introducing suitable modifications in both types of components to enhance their global performance. It also facilitates the selection of frameworks and networks among a large diversity of these components available these days for visual understanding.

Automated Hierarchical Synthesis of Radio-Frequency Integrated Circuits and Systems. A Systematic and Multilevel Approach
F. Passos, E. Roca, R. Castro-López and F.V. Fernández
Book - 204 p, 2020
SPRINGER    ISBN: 978-30-3047-246-7    » link
[abstract]
This book describes a new design methodology that allows optimization-based synthesis of RF systems in a hierarchical multilevel approach, in which the system is designed in a bottom-up fashion, from the device level up to the (sub)system level. At each level of the design hierarchy, the authors discuss methods that increase the design robustness and increase the accuracy and efficiency of the simulations. The methodology described enables circuit sizing and layout in a complete and automated integrated manner, achieving optimized designs in significantly less time than with traditional approaches.
- Describes an efficient and accurate methodology to design automatically RF systems, with guaranteed accuracy from the device to the system level.
- Discusses analytical and machine learning techniques for modelling integrated inductors and uses such models in synthesis approaches.
- Compares synthesis strategies for RF circuits based on bottom-up versus flat approaches.
- Discusses layout-aware bottom-up design methodologies for RF circuits.
- Discusses variability-aware bottom-up design methodologies for RF circuits.
- Describes multilevel bottom-up design methodologies from the device up to the system level.

Approaching the Design of Energy Recovery Logic Circuits using Tunnel Transistors
J. Núñez and J.M. Avedillo
Journal Paper - IEEE Transactions on Nanotechnology, vol. 19, pp 500-507, 2020
IEEE    DOI: 10.1109/TNANO.2020.3004941    ISSN: 1536-125X    » doi
[abstract]
Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope, and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account that problems associated with the inverse current of their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.

Charge-Redistribution Based Quadratic Operators for Neural Feature Extraction
R. Fiorelli, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 3, pp 606-619,2020
IEEE    DOI: 10.1109/TBCAS.2020.2987389    ISSN: 1932-4545    » doi
[abstract]
This paper presents a SAR converter based mixed-signal multiplier for the feature extraction of neural signals using quadratic operators. After a thorough analysis of design principles and circuit-level aspects, the proposed architecture is explored for the implementation of two quadratic operators often used for the characterization of neural activity, the moving average energy (MAE) operator and the nonlinear energy operator (NEO). Programmable chips for both operators have been implemented in a HV-180 nm CMOS process. Experimental results confirm their suitability for energy computation and action potential detection and the accomplished area×power performance is compared to prior art. The MAE and NEO prototypes, at a sampling rate of 30kS/s, consume 116 nW and 178 nW, respectively, and digitize both the input neural signal and the operator outcome, with no need for digital multipliers.

Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy
A. Lopez-Angulo, A. Gines and E. Peralias
Conference - IEEE International New Circuits and Systems Conference NEWCAS 2020
[abstract]
This work introduces a digital technique to measure and correct the mismatch between capacitors in SAR ADCs with split capacitor-based DAC (CDAC), including the bridge capacitor impairments. The method takes advantage of redundancy for calibration with negligible impact on the analog section. It reuses some of the capacitors in the array to also com-pensate the comparison offset, preventing redundancy interval saturation during the error measurement phase. The effec-tiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit split-CDAC SAR ADC case study.

Non-linear calibration of pipeline ADCs using a histogram-based estimation of the redundant INL
A. Gines, G. Leger and E. Peralias
Conference - IEEE International New Circuits and Systems Conference NEWCAS 2020
[abstract]
This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT-based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.

On the importance of bias-dependent charge injection for SET evaluation in AMS Circuits
V. Gutierrez and G. Leger
Conference - IEEE International New Circuits and Systems Conference NEWCAS 2020
[abstract]
Single Event Transients have become a serious issue in safety-critical applications of Analog and Mixed-Signal (AMS) circuits. Therefore, an evaluation must be carried out in order to diagnose the critical nodes but also to get an idea of the global sensitivity of the circuit, as a proxy to its experimental cross-section. In this work we evaluate two different top-down approaches considering or not the biasing of the impacted transistor to compute the injected charge. Performing an exhaustive evaluation campaign on a high performance buffer as a case of study, it will be shown that the error committed by the charge difference is greater than the one committed by simulating with the simple schematic without layout parasitics. However, the correlation between both approaches is high, so the critical nodes appear in the same order.

Electrical modeling of the growth and differentiation of skeletal myoblasts cell cultures for tissue engineering
A. Olmo, Y. Yuste, J.A. Serrano, A. Maldonado-Jacobi, P. Pérez, G. Huertas, S, Pereira, A. Yufera and F. de la Portilla
Journal Paper - Sensors, vol. 20, no. 11, article 3152, 2020
MDPI    DOI: 10.3390/s20113152    ISSN: 1424-8220    » doi
[abstract]
In tissue engineering, of utmost importance is the control of tissue formation, in order to form tissue constructs of clinical relevance. In this work, we present the use of an impedance spectroscopy technique for the real-time measurement of the dielectric properties of skeletal myoblast cell cultures. The processes involved in the growth and differentiation of these cell cultures in skeletal muscle are studied. A circuit based on the oscillation-based test technique was used, avoiding the use of high-performance circuitry or external input signals. The effect of electrical pulse stimulation applied to cell cultures was also studied. The technique proved useful for monitoring in real-time the processes of cell growth and estimating the fill factor of muscular stem cells. Impedance spectroscopy was also useful to study the real-time monitoring of cell differentiation, obtaining different oscillation amplitude levels for differentiated and undifferentiated cell cultures. Finally, an electrical model was implemented to better understand the physical properties of the cell culture and control the tissue formation process.

On the usage of machine-learning techniques for the accurate modeling of integrated inductors for RF applications
F. Passos, E. Roca, R. Castro-Lopez and F.V. Fernandez
Book Chapter - Modelling Methodologies in Analogue Integrated Circuit Design, pp 155-178, 2020
IET    DOI: 10.1049/PBCS051E_ch7    ISBN: 978-1-7856-1696-9    » doi
[abstract]
This chapter describes an inductor modeling strategy based on machine-learning techniques. The model developed is based on Kriging functions and uses a novel modeling technique based on a two-step strategy, which is able to obtain an extremely accurate model with less than 1% error when compared to electromagnetic (EM) simulations. Due to its extreme accuracy and efficiency, the model can be used in inductor synthesis processes using single- or multi-objective optimization algorithms in order to obtain a single design or a Pareto-optimal front. Also, the model can describe the inductor behavior in frequency and therefore can also be used in circuit design using modern electrical simulators. This chapter discusses both applications (inductor synthesis and circuit design), performing several singleand multi-objective inductor optimizations, using different inductor topologies and operating frequencies. Furthermore, the model is also used in order to accurately model inductors during the design of a voltage-controlled oscillator (VCO) and a low-noise amplifier (LNA).

Modeling of variability and reliability in analog circuits
J. Martin-Martinez, J. Diaz-Fortuny, A. Toro-Frias, P. Martin-Lloret, P. Saraza-Canflanca, R. Castro-Lopez, R. Rodriguez, E. Roca, F.V. Fernandez and M. Nafria
Book Chapter - Modelling Methodologies in Analogue Integrated Circuit Design, pp 179-206, 2020
IET    DOI: 10.1049/PBCS051E_ch8    ISBN: 978-1-7856-1696-9    » doi
[abstract]
This chapter is divided into four sections. In Section 8.1, the probabilistic defect occupancy (PDO) model, a physics-based compact model, is introduced, which can be easily implemented into circuit simulators. Section 8.2 describes a purposely designed IC which contains suitable test structures, together with a full instrumentation system for the massive characterization of TZV and TDV in CMOS transistors, from which aging of the technology under study can be statistically evaluated. Section 8.3 is devoted to a smart methodology, which allows extracting the statistical distributions of the main physical parameters related to TDV from the measurements performed with the instrumentation system. Finally, Section 8.4 describes CASE, a new reliability simulation tool that accounts for TZV and TDV in analog circuits, covering important aspects, such as the device degradation evaluation, by means of stochastic modeling and the link between the device biasing and its degradation. As an example, the shifts of the performance of a Miller operational amplifier related to the device TDV is evaluated using CASE. Finally, in Section 8.5 the main conclusions are summarized.

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