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Phase Transition Device for Phase Storing
M.J. Avedillo, J.M. Quintana and J. Núñez
Journal Paper - IEEE Transactions on Nanotechnology, vol. 19, pp 107-112, 2020
IEEE    DOI: 10.1109/TNANO.2020.2965243    ISSN: 1536-125X    » doi
[abstract]
Nano-oscillators based on phase transitions materials (PTM) are being explored for the implementation of different non-conventional computing paradigms. This paper describes the capability of such autonomous non-linear oscillators to store phase-encoded information. A latch based in sub-harmonic injection locking using an oscillator composed of a PTM device and a transistor is described. Resistive coupling is used to inject both a required synchronization signal and the input to be stored. Operation of the proposed latch implementation, the embedding of functionality into the latch and its application to frequency division are illustrated and validated by simulation.

Incoming Editorial
J.M. de la Rosa
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no.1, pp 1-3, 2020
IEEE    DOI: 10.1109/TCSII.2019.2956327    ISSN: 1549-7747    » doi
[abstract]
Dear Readers, It is a great honor and privilege for me to start my two-year term of duty as Editor-in-Chief (EiC) of IEEE Transactions on Circuits and Systems - Part II: Express Briefs (TCAS-II) and I am very thankful to the IEEE Circuits and Systems Society (CASS) for giving me this opportunity. During the last four years, I have been very fortunate to work as Deputy Editor-in-Chief (DEiC) of TCAS-II together with Professor C.K. Michael Tse, who has set the bar very high for me! I would like to begin this first issue of TCAS-II in 2020 by expressing my most sincere and warm gratitude to Professor Tse for his great job, dedication, and guidance during all this time working together. I learned a lot from him. Thank you so much, Michael!

Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits
F. Cilici, G. Leger, M.J. Barragan, S. Mir, E. Lauga-Larroze and S. Bourdel
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Millimeter-wave circuits in current nanometric technologies are especially sensitive to process variations, which can seriously degrade the device behavior and reduce fabrication yield. To tackle this issue, conservative designs and large design margins are widely used solutions. Another approach consists in introducing variable elements, also called tuning knobs, to allow post-fabrication tuning. One-shot statistical calibration techniques take advantage of advanced machine learning regression tools to propose a set of tuning knobs values that enhance the circuit performance based on simple measurements. Training the regression models require a huge amount of data covering the device performances, the effect of the tuning knobs and the simple measurements that guide the regression. In this work, we propose an efficient method for generating such a data set that reduces noticeably the size of the required training set for an accurate calibration.

Voice-Controlled Assistance Device for Victims of Gender-Based Violence
M.A. Dominguez, D. Palomeque, J.M. Carrillo, J.M. Valverde, J.F. Duque, B. Perez and R. Perez-Aloe
Conference - Multidisciplinary International Conference of Research Applied to Defense and Security MICRADS 2019
[abstract]
One of the biggest problems that society is currently facing is violence against women. In recent years, tangible progress in protecting and saving the lives of female victims of intimate partner/family-related homicide has not been made, so targeted responses are clearly needed. In this work, an electronic device to help victims of gender-based violence who live with their aggressor has been designed. The system is built on Bluetooth Low Energy technology allowing a wireless communication between device and mobile phone with a low power consumption. The device is controlled by three different commands and is capable of sending messages through a mobile phone to a Control Center. Depending on the nature of the received messages, the Control Center will take the appropriate measures to assist the victim. The design has been made paying special attention to a reduced size so that the device can easily be camouflaged in any accessory of the victim's jewelry, thus going unperceived to the possible aggressor.

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing
N. Lourenco, E. Afacan, R. Martins, F. Passos, A. Canelas, R. Povoa, N. Horta and G. Dundar
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
In this paper, the use of machine learning techniques to repurpose already available Pareto optimal fronts of analog integrated circuit blocks for new contexts (loads, supply voltage, etc.) is explored. Data from previously sized circuits is used to train models that predict both circuit performance under the new context and the corresponding device sizes. A two-model chain is proposed, where, in the first layer, a multivariate polynomial regression estimates the performance tradeoffs. The output of this performance model is then used as input of an artificial neural network that predicts the device sizing that corresponds to that performance. Moreover, the models are trained with optimized sizing solutions, leading almost instantly to predicted solutions that are near optimal for the new context. The proposed methodology was integrated into a new framework and tested against a real circuit topology, with promising results. The model was able to predict wider and, in some cases, better, performance tradeoff, when compared to independent optimization runs for the same context, despite requiring 400 times fewer circuit simulations.

Self-Testing Analog Spiking Neuron Circuit
S.A. El-Sayed, L.A. Camunas-Mesa, B. Linares-Barranco and H.G. Stratigopoulos
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35μm CMOS technology.

An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks
P. Martin-Lloret, J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
This paper presents an integrated circuit (IC) array whose purpose is to observe, quantify and characterize the impact of time-dependent variability effects, like aging, in several widely used digital and analog circuit blocks. With the increasing interest that this kind of mechanism has attracted in the last years, for its potential impact in the reliability of ultra-scaled integrated circuits, it is only relevant that appropriate measures are taken to find out how it can be included (and thus mitigated) in the design process of such integrated circuits. And, while substantial literature exists that covers the device level, time-dependent variability at circuit level has not been as equally studied. This work complements our previous efforts in providing a holistic approach to Reliability-Aware Design: from statistical characterization and modeling at device-level, to simulation, and into optimization-based design with reliability considerations, the array presented here provides one more step towards a thorough and accurate understanding of how time-dependent variability works at the circuit level.

Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity
A. Yousefzadeh, M.A. Khoei, S. Hoseini, P. Holanda, S. Leroux, O. Moreira, J. Tapson, B. Dhoedt, P. Simoens, T. Serrano-Gotarredona, B. Linares-Barranco
Journal Paper - IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 4, pp 668-678, 2019
IEEE    DOI: 10.1109/JETCAS.2019.2951121    ISSN: 2156-3357    » doi
[abstract]
Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike the most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) is the key to its excellence in this domain. In this work, we show how asynchronous processing with state-full neurons allows exploitation of the existing sparsity in natural signals. This paper explains three different types of sparsity and proposes an inference algorithm which exploits all types of sparsities in the execution of already trained networks. Our experiments in three different applications (Handwritten digit recognition, Autonomous Steering and Hand-Gesture recognition) show that this model of inference reduces the number of required operations for sparse input data by a factor of one to two orders of magnitudes. Additionally, due to fully asynchronous processing this type of inference can be run on fully distributed and scalable neuromorphic hardware platforms.

Evaluation of Implanted Stent Occlusion Status Based on Neointimal Tissue Bioimpedance Simulations
J.M. Portillo-Anaya, P. Perez, A. Olmo, G. Huertas and A. Yufera
Journal Paper - Journal of Sensors, vol. 2019, article 7167186, 2019
HINDAWI    DOI: 10.1155/2019/7167186    ISSN: 1687-725X    » doi
[abstract]
This paper describes the characterization of the light hole, also known as the lumen, in implanted stents affected by restenosis processes using bioimpedance (BI) as a biomarker. The presented approach will enable real-time monitoring of lumens in implanted stents. The basis of the work hereby reported is the fact that neointimal tissues involved in restenosis can be detected and measured through their impedance properties, namely, conductivity and permittivity. To exploit these properties, a 4-electrode setup for BI measurement is proposed. This setup allows study of the influence of the various tissues involved in restenosis fat, muscle, fibre, and endothelium, together with the blood, on the BI value at several frequencies. In addition, BI simulation tests were performed using the electric physics module available in COMSOL Multiphysics®. Interestingly, fat constitutes the most influential layer on the value of impedance (measured in kΩ/μm-magnitude change per micrometre of lumen occlusion). A case study using a standard stent is also presented. In this study, where the involved tissues and blood were simultaneously considered, we conducted an analysis for stable and vulnerable plaques in restenosis test situations. In this regard, the proposed method is useful to test the stent obstruction and detect potential dangerous cases due to nonstable fat accumulation.

Adaptive defect simulation flow for Defect-oriented Test evaluation
V. Gutierrez and G. Leger
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
For AMS-RF circuits, functional test is usually considered the best way to test a circuit. By construction, it should detect any fault (i.e. performance loss) and consequently it does not require a-priori validation. However, defect-oriented strategies require an evaluation of the test quality prior to their implementation. This implies resorting to computationally intensive defect simulation campaigns. In this work, we propose an adaptive defect simulation loop that evaluates at each step the defect coverage and the fault escape rate of the test under validation and determines the best way to employ the computational power as a function of the test target metrics. That is to say, if it is better to simulate the performance setup to update the fault escape metric or, conversely, to simulate the proposed test setup to update the defect coverage metric.

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