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Does the use of nest materials in a ground-nesting bird result from a compromise between the risk of egg overheating and camouflage?
J. Gómez, G. Liñán-Cembrano, C. Ramo, M. Castro, A. Pérez-Hurtado and J.A. Amat
Journal Paper - Biology Open, bio.042648, first online, 2019
THE COMPANY OF BIOLOGISTS    DOI: 10.1242/bio.042648    ISSN: 2046-6390    » doi
[abstract]
Many studies addressing the use of nest materials by animals have focused on only one factor to explain its function. However, the consideration of more than one factor could explain the apparently maladaptive choice of nest materials that makes the nests conspicuous to predators. We experimentally tested whether there is a trade-off in the use of nest materials between the risks of egg predation versus protection from overheating. We studied the ground-nesting Kentish plover, Charadrius alexandrinus, in southern Spain. We added materials differing in their thermal properties and coloration to the nests, thus affecting rates of egg heating and nest temperature and camouflage. Before these manipulations, adults selected materials that were lighter than the microhabitat, probably to buffer the risk of egg overheating. However, the adults did not keep the lightest experimental materials, probably because they reduced camouflage, and this could make the nests to be even more easily detectable by predators. In all nests, adults removed most of the experimental materials independently of their properties, so that egg camouflage returned to the original situation within a week of the experimental treatments. Although the thermal environment may affect the choice of nest materials by the plovers, the ambient temperatures were not too high at our study site as to determine the acceptance of the lightest experimental materials.

Article Data-Analytics Modeling of Electrical Impedance Measurements for Cell Culture Monitoring
E. García, P. Pérez, A. Olmo, R. Díaz, G. Huertas and A. Yúfera
Journal Paper - Sensors, vol. 19, no. 21, art. 4639, 2019
MDPI    DOI: 10.3390/s19214639    ISSN: 1424-8220    » doi
[abstract]
High-throughput data analysis challenges in laboratory automation and lab-on-a-chip devices´ applications are continuously increasing. In cell culture monitoring, specifically, the electrical cell-substrate impedance sensing technique (ECIS), has been extensively used for a wide variety of applications. One of the main drawbacks of ECIS is the need for implementing complex electrical models to decode the electrical performance of the full system composed by the electrodes, medium, and cells. In this work we present a new approach for the analysis of data and the prediction of a specific biological parameter, the fill-factor of a cell culture, based on a polynomial regression, data-analytic model. The method was successfully applied to a specific ECIS circuit and two different cell cultures, N2A (a mouse neuroblastoma cell line) and myoblasts. The data-analytic modeling approach can be used in the decoding of electrical impedance measurements of different cell lines, provided a representative volume of data from the cell culture growth is available, sorting out the difficulties traditionally found in the implementation of electrical models. This can be of particular importance for the design of control algorithms for cell cultures in tissue engineering protocols, and labs-on-a-chip and wearable devices applications.

A Neuromorphic Digital Circuit for Neuronal Information Encoding using Astrocytic Calcium Oscillations
F. Faramarzi, F. Azad, M. Amiri and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 13, article 998, 2019
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2019.00998    ISSN: 1662-4548    » doi
[abstract]
Neurophysiological observations are clarifying how astrocytes can actively participate in information processing and how they can encode information through frequency and amplitude modulation of intracellular Ca2+ signals. Consequently, hardware realization of astrocytes is important for developing the next generation of bio-inspired computing systems. In this paper, astrocytic calcium oscillations and neuronal firing dynamics are presented by De Pittà and IF (Integrated & Fire) models, respectively. Considering highly nonlinear equations of the astrocyte model, linear approximation and single constant multiplication (SCM) techniques are employed for efficient hardware execution while maintaining the dynamic of the original models. This low-cost hardware architecture for the astrocyte model is able to show the essential features of different types of Ca2+ modulation such as amplitude modulation (AM), frequency modulation (FM), or both modes (AFM). To show good agreement between the results of original models simulated in MATLAB and the proposed digital circuits executed on FPGA, quantitative, and qualitative analyses including phase plane are done. This new neuromorphic circuit of astrocyte is able to successfully demonstrate AM/FM/AFM calcium signaling in its real operation on FPGA and has applications in self-repairing systems. It also can be employed as a subsystem for linking biological cells to artificial neuronal networks using astrocytic calcium oscillations in future research.

A High TCMRR, Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation
J.L. Valtierra, R. Fiorelli, N. Pérez-Prieto, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference - IEEE Biomedical Circuits and Systems Conference BioCAS 2019
[abstract]
This paper describes a multichannel bidirectional front-end for true closed-loop neuromodulation. Stimulation artefacts are reduced via a 4-channel H-bridge current source sharing stimulators to minimize residual charge drops in the electrodes. The 4-channel sensing front-end is capable of multichannel sensing in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR drop due to electrode mismatch. Experimental verification of a prototype fabricated in 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 μW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.

A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression
N. Pérez-Prieto, R. Fiorelli, J.L. Valtierra, P. Pérez-García, M. Delgado-Restituto and A. Rodríguez-Vázquez
Conference - IEEE Biomedical Circuits and Systems Conference BioCAS 2019
[abstract]
This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. In order to reduce interface area, a 32-channel multiplexer is implemented on circuit input. Furthermore, a spatial delta encoding is proposed to compress the signal range. A differential artifact compression algorithm is implemented to avoid saturation in the signal path, thus enabling reconstruct or suppressing artifacts in digital domain. The proposed design has been implemented using 0.18 μm TSMC technology. Experimental results shows a power consumption per channel of 1.0 μW, an input referred noise of 1.1 μVrms regarding the bandwidth of interest and a dynamic range of 91 dB.

Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology
I. Vornicu, F. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - European Solid-State Device Research Conference ESSDERC 2019
[abstract]
Photon detection at longer wavelengths is much desired for LiDAR applications. Silicon photodiodes with deeper junctions and larger multiplication regions are more sensitive to near-IR photons. This paper presents the complete electro-optical characterization of a P-well/Deep N-well single photon avalanche diode integrated in 110nm CIS technology. Devices with various sizes, shapes and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is of 18V. The proposed structure has 0.4Hz/um2 dark count rate, 0.5% afterpulsing, 188ps FWHM (total) jitter and around 10% photon detection probability at 850nm wavelength. All figures have been measured at 3V excess voltage.

Evaluation of Architectures for FPGA-Implementation of High-Resolution TDCs
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2019
[abstract]
Time-to-digital converters (TDCs) are a central component in systems based on time-delay assessment. The principal characteristics to be sought for in a TDC are high resolution, long time range, linearity and low power consumption. Besides, field-programmable gate arrays (FPGAs) represent an interesting option to explore fully-digital TDC architectures, because of their flexibility, shorter development time and lower implementation cost than ASICs. They are reconfigurable and usually built on the finest silicon technologies. The purpose of this work is to identify the different architectures that lead to high-resolution TDCs on FPGA, and to compare them in terms of the appropriate figures of merit. The most extended method to cover a long time interval while preserving a high time resolution is to combine a coarse counter with a fine time interpolator. Two techniques have been widely used to implement the interpolator, namely a tapped delay line (TDL) and a multiple-phase clock interpolator. Exploiting fast carry chains present in most modern FPGAs, sub-clock-period resolution have been achieved, down to tens of picoseconds. Other important aspects of the TDC design are the thermometer-to-binary encoder, the minimization of the clock skew, the analysis of the influence of voltage and temperature changes and bin-width calibration. Accordingly, we report an analysis of the different TDC architectures on FPGA based on their performance characteristics.

Towards a Simplified Procedure for CNN Performance Prediction on Embedded Platforms
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2019
[abstract]
Vision is arguably the technical field benefiting the most from the renaissance of artificial intelligence in the last few years. In particular, the convergence of massive datasets for training, boosted computational power, and enhanced machine learning techniques has given rise to highly accurate vision algorithms -even outperforming humans in certain tasks- based on convolutional neural networks (CNNs). The potential of these algorithms has attracted attention from many parties, both in academia and industry, spurring the development of a myriad of hardware platforms and software frameworks. The challenge now is how to efficiently leverage and integrate this variety of components in practical realizations, taking also into account that CNN models keep evolving at a rapid pace. With this scenario in mind, we have been working on a simplified procedure to predict the performance of CNNs running on embedded platforms in terms of throughput and power consumption. The objective is to facilitate the evaluation of the aforementioned components and CNN models prior to actually implementing them, thereby speeding up the deployment of optimal solutions. In this talk, we will describe key aspects of the proposed procedure. Specifically, we will elaborate on SweepNet, a deep neural network tailored for meaningful per-layer characterization. The performance models extracted from SweepNet for a hardware platform allow to accurately predict layer by layer the execution time and energy consumption of any other CNN running on that platform.

On the Balanced Allocation of Convolutional Neural Network Models on FPGAs
A. Muñío-Gracia, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2019
[abstract]
Deep Learning (DL) algorithms have demonstrated their competence in accurately extracting information from data, especially in the field of computer vision. DL has emerged as an end-to-end approach based on learned multi-level scene representations. A number of open-source frameworks have been created to describe convolutional neural network (CNN) models -a class of the deep neural networks (DNNs) that support DL. Their computational complexity prompts for hardware acceleration. The challenge in the design of hardware accelerators for CNNs is providing a sustained throughput with low power consumption. In order to test our architectural proposals, we will be employing FPGAs. They are reconfigurable, efficient, and have adjustable precision. FPGAs permit architectural exploration with shorter development time and lower cost than ASICs. This work introduces an scalable, frameworkagnostic, architecture whose behavior self-adapts to the selected CNN configuration. A design space analysis is performed for some state-of-the-art CNNs, namely VGG-16, Tiny DarkNet, and SqueezeNet. The objective is a balanced allocation of resources. For this, tiling parameterization will be optimized attending to decisive performance criteria such as the number of memory accesses, data movement policy and throughput.

On the Correlation of CNN Performance and Hardware Metrics for Visual Inference on a Low-Cost CPU-based Platform
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - International Conference on Systems, Signals and Image Processing IWSSIP 2019
[abstract]
While providing the same functionality, the various Deep Learning software frameworks available these days do not provide similar performance when running the same network model on a particular hardware platform. On the contrary, we show that the different coding techniques and underlying acceleration libraries have a great impact on the instantaneous throughput and CPU utilization when carrying out the same inference with Caffe, OpenCV, TensorFlow and Caffe2 on an ARM Cortex-A53 multi-core processor. Direct modelling of this dissimilar performance is not practical, mainly because of the complexity and rapid evolution of the toolchains. Alternatively, we examine how the hardware resources are distinctly exploited by the frameworks. We demonstrate that there is a strong correlation between inference performance - including power consumption - and critical parameters associated with memory usage and instruction flow control. This identified correlation is a preliminary step for the development of a simple empirical model. The objective is to facilitate selection and further performance tuning among the ever-growing zoo of deep neural networks and frameworks, as well as the exploration of new network architectures.

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