Recent publications
An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization
J. Núñez and R. Fiorelli
Journal Paper · Sensors 2026, 26, 3268
MDPI ISSN: 1424-8220
abstract
doi
This work presents an FPGA-based edge-event timing front-end for time-resolved sensing and event-driven measurement scenarios. The proposed design is intended as a detector-independent timing subsystem whose architectural choices are motivated by constraints that are common in single-photon avalanche diode (SPAD)-based and other asynchronous time-resolved sensing workflows, including event trustworthiness, dead-time sensitivity, and constrained downstream readout. Rather than treating the implementation as an isolated interpolation macro, this work evaluates it as an experimentally observable timing subsystem that combines carry-chain-based fine interpolation, coarse-fine timestamp formation, explicit event-quality assessment, dead-time-aware handling, and lightweight host-visible export. The experimental validation is organized around two complementary modes. An internal ILA-based mode is used to verify coherent front-end behavior under MHz-range short-pulse excitation, while a UART-based campaign identifies practical host-visible operating regions through baseline, repeatability, pulse-width, safe-versus-aggressive, and intermediate frequency-sweep experiments. The results identify a safe export-compatible operating point, a more exploratory high-rate regime, and an experimentally interpretable transition between them that, while not strictly monotonic in all metrics, does not exhibit catastrophic degradation across the explored frequency range. Taken together, the measurements indicate that the proposed architecture is best understood not as a best-case standalone time-to-digital (TDC) benchmark but as an experimentally characterized timing front-end whose practical behavior can be interpreted across complementary internal and export-visible operating regimes.
Simulated VO2 Neuron With Embedded HfO2 Memristive Synapse
J. Núñez and R. Fiorelli
Journal Paper · IEEE Electron Device Letters, vol. 47, no. 5, pp. 1025-1028, May 2026
IEEE ISSN: 1558-0563
abstract
doi
We present a neuromorphic circuit cell that integrates a volatile VO2 neuron with a non-volatile HfO2 memristive synapse, enabling autonomous local plasticity in a compact, CMOS-compatible building block. Unlike conventional neuromorphic implementations where neurons and synapses are separated and coordinated by peripheral circuitry, the HfO2 memristor is embedded directly in the leak path of a VO2 integrate-and-fire neuron. As a result, the neuron's spike dynamics directly modulate the synaptic conductance, which in turn reshapes neuronal excitability. Using experimentally calibrated Verilog-A models and electrical simulations, we demonstrate stable firing-rate adaptation, long-term conductance evolution driven by neuronal activity, and compatibility with standard 1T1R programming schemes. This unified neuron-synapse cell forms a device-circuit primitive where volatile and non-volatile dynamics are co-designed at the cell level, enabling scalable local plasticity without peripheral control circuitry.
Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation
P. Ortega-Castro, E. Camacho-Ruiz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Journal Paper · IEEE Open Journal of the Solid-State Circuits Society (Early Access)
IEEE ISSN: 2644-1349
abstract
doi
In increasingly interconnected systems, security has become a critical concern. In this context, delay-based Physical Unclonable Functions (PUFs), such as Ring Oscillator (RO) PUFs, have emerged as key hardware security primitives by providing unique, unpredictable, and reliable responses, addressing security challenges related to key storage and device authentication. To ensure robustness, RO-PUF designs traditionally resort to analog-driven implementation flows, which suffer from high design overhead and limit scalability across technology nodes. We present a configurable RO-PUF design integrated following a standard-cell-based, fully digital semi-custom-design methodology, significantly reducing design effort while enabling portability across planar CMOS technologies. The proposed architecture integrates fully on-chip Helper Data Algorithm (HDA) combined with a lightweight Error Correction Code (ECC) to support key generation, obfuscation, and recovery. Furthermore, it was fabricated in TSMC 65 nm technology and extensively characterized across diverse operating conditions, including process, voltage, and temperature (PVT) variations, achieving state-of-the-art metrics.
Assessment of an FPGA Implementation of a Hybrid PUF Based on a Configurable Transient Effect Ring Oscillator and Ring Oscillator (TERORO-PUF)
A. Casado-Galán, J. Núñez, E. Tena-Sánchez, F.E. Potestad-Ordóñez and A.J. Acosta-Jiménez
Journal Paper · Electronics, vol. 15, no. 3, article 661, 2026
MDPI ISSN: 2079-9292
abstract
doi
In the current situation of the Internet of Things (IoT) with its billions of interconnected devices, security in this low-resource environment is paramount. A Physical Unclonable Function (PUF) is a very useful cryptographic primitive which allows us to extract unique information from a particular device in a non-reproducible way. This allows us to use a PUF in cryptography for authentication or secret-key generation. Ring Oscillators (ROs) and Transient Effect Ring Oscillators (TEROs) are oscillating structures used in both FPGAs and ASICs to build PUFs. In this paper we present an FPGA implementation of a PUF based on what we call the ’’TERORO’’ cell (TERO + RO), which is a hybrid structure that allows us to use the different functionalities of both RO and TERO in a single building block. We assess all the possible methods of extracting bits of information from the PUF based on TERORO cells. Finally, we tested the circuit and presented experimental results in terms of its uniqueness, uniformity, and reliability. In RO-counter mode, we obtain 49.74%
uniqueness, 54.66%
uniformity, and 97.81%
reliability across devices, while TERO-based XOR mixing achieves 52.83%
uniformity, 45.79%
uniqueness, and 93.15%
reliability. The FPGA footprint is 142 LUTs, 36 registers, and 82 slices.
Enhancing the performance of HfO2-based memristors with a thin Al2O3 layer: a comparative study
M. Shooshtari, T. Serrano Gotarredona and B. Linares-Barranco
Journal Paper · Journal of Physics D: Applied Physics, vol. 58, no. 45, 2025
IOP Science
abstract
doi
The resistive switching behavior of memristors is pivotal for advancing next-generation non-volatile memory and neuromorphic computing devices. In this study, we investigate the impact of incorporating a thin Al2O3 interfacial layer into HfO2-based memristors by fabricating and comparing two device architectures: W/HfO2/Ti/TiN and W/Al2O3/HfO2/Ti/TiN. The Al2O3 layer significantly influences device behavior by altering the electric field distribution and suppressing oxygen vacancy diffusion, leading to more confined and stable filament formation. While the dual-layer structure exhibits higher forming voltages due to increased dlectric thickness and the insulating properties of Al2O3, it also demonstrates improved switching uniformity, reduced resistance variability, and enhanced cycle-to-cycle endurance. Variability, quantified as resistance state variation over repeated cycles, was notably improved in the Al2O3-based device, with resistance fluctuations reduced by nearly 50% compared to the single-layer HfO2 device. These results highlight the role of interfacial engineering in improving memristor stability and reliability, offering valuable design strategies for future memory and neuromorphic computing systems.
A Side-Channel Protected and High-Performance Hardware Implementation for EdDSA25519
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · IEEE Access Vol 13
IEEE ISSN: 2169-3536
abstract
doi
This paper presents a high-performance and secure hardware implementation of the Edwards-Curve Digital Signature Algorithm (EdDSA25519). Using the fixed-base signed multi-comb and the k-ary algorithms for scalar multiplication, the proposed design achieves 307%, 253%, and 48% faster performance in key generation, signature generation, and signature verification, respectively, compared to the fastest previous hardware implementation in the state-of-the-art. When compared to the software-based OpenSSL implementation, our design demonstrates timing performance improvements ranging from 1000% to 2200%. Additionally, we integrate robust Side-Channel Attack (SCA) countermeasures and validate their effectiveness through Test Vector Leakage Assessment (TVLA). The results demonstrate increased resistance to Simple Power Analysis (SPA) and Differential Power Analysis (DPA), offering a hardware-based secure solution for modern cryptographic applications.
Workload Compression Techniques to Scale Defect-Centric BTI Models to the Circuit Level
A. Santana-Andreo, V.M. van Santen, R. Castro-López, E. Roca, H. Amrouch and F.V. Fernández
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers (Early Access), 2025
IEEE ISSN: 1549-8328
abstract
doi
Bias Temperature Instability (BTI) poses a significant challenge in ensuring the reliability of digital systems, affecting the delay of digital logic gates, which ultimately can lead into timing failures. Sophisticated defect-centric models have been developed and successfully calibrated against empirical data to forecast the impacts of BTI at the device level. However, their application to large-scale digital circuits operating under realistic workloads over typical system lifetimes is limited because of the computational complexity of defect-centric models. To make the application of aging models in that context feasible, a useful technique is to compress the transistor workloads into simplified and hence manageable representative workloads. While fast in terms of execution speed, previous techniques struggle with accuracy when predicting aging degradation, and can reach a very high average error in threshold voltage increase prediction. In this work, we review the compression techniques described in the literature and propose two novel approaches that surpass existing ones in terms of accuracy, which is demonstrated for a complex digital design used as benchmark. Specifically, our best compression technique matches the predictions obtained through the reference uncompressed workloads, introducing negligible error, and maintains low execution times to efficiently and accurately scale defect-centric models to the circuit level.
TVLA assessment and proposed countemeasures on the hardware implementation of EdDSA25519
P. Navarro-Torrero, E. Camacho-Ruiz, M.C. Martinez-Rodriguez and P. Brox
Conference · Demo in the University Fait at DATE (Design, Automation and Test in Europe Conference) 2025, Marzo 31-Abril 2, 2025 (https://www.date-conference.com)
abstract
Abstract not available
VLSI Integration of a Physical Unclonable Function as identifier and key generator
P. Ortega-Castro, M.C. Martinez-Rodriguez and P. Brox
Conference · Demo in the University Fait at DATE (Design, Automation and Test in Europe Conference) 2025, Marzo 31-Abril 2, 2025 (https://www.date-conference.com)
abstract
Abstract not available
Security assessment methodology for RISC-V cores
A. Karmakar, P. Navarro-Tornero, E. Camacho-Ruiz, M.C. Martinez-Rodriguez and P. Brox
Conference · RISC-V Summit Europe 2025, Mayo 12-15, 2025
abstract
Abstract not available
