Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems
E. Camacho-Ruiz, M.C. Martínez-Rodríguez, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 7, no.2, article 29, 2023
MDPI ISSN: 2410-387X
The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30-45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.
On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Sensors, vol. 23, no. 8, article 4070, 2023
MDPI ISSN: 1424-8220
The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.
A Pipelining-Based Heterogeneous Scheduling and Energy-Throughput Optimization Scheme for CNNs Leveraging Apache TVM
D. Velasco-Montero, B. Goossens, J. Fernández-Berni, Á. Rodríguez-Vázquez and W. Philips
Journal Paper · IEEE Access, 2023
IEEE ISSN: 2169-3536
Extracting information of interest from continuous video streams is a strongly demanded computer vision task. For the realization of this task at the edge using the current de-facto standard approach, i.e., deep learning, it is critical to optimize key performance metrics such as throughput and energy consumption according to prescribed application requirements. This allows achieving timely decision-making while extending the battery lifetime as much as possible. In this context, we propose a method to boost neural-network performance based on a co-execution strategy that exploits hardware heterogeneity on edge platforms. The enabling tool is Apache TVM, a highly efficient machine-learning compiler compatible with a diversity of hardware back-ends. The proposed approach solves the problem of network partitioning and distributes the workloads to make concurrent use of all the processors available on the board following a pipeline scheme. We conducted experiments on various popular CNNs compiled with TVM on the Jetson TX2 platform. The experimental results based on measurements show a significant improvement in throughput with respect to a single-processor execution, ranging from 14% to 150% over all tested networks. Power-efficient configurations were also identified, accomplishing energy reductions above 10%.
Band-Pass Sigma-Delta Modulation: The Path towards RF-to-Digital Conversion in Software-Defined Radio
J.M. de la Rosa
Journal Paper · Chips, vol. 2 no. 1, articles 44-69, 2023
MDPI ISSN: 2674-0729
This paper reviews the state of the art on bandpass sigma-delta modulators (BP-sigma-deltaMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-sigma-deltaM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.
Ultra-High-Resistance Pseudo-Resistors with Small Variations in a Wide Symmetrical Input Voltage Swing
F. Karami-Horestani and J.M. de la Rosa
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE ISSN: 1549-7747
This paper presents a new strategy and circuit configuration composed of serially-connected PMOS devices operating in the subthreshold region for implementing ultra-highvalue resistors required in very low-frequency active-RC filters and bio-amplifiers. Depending on the application, signal bandwidth for instance in bio-amplifiers may vary from a few mHz up to a maximum of 10 kHz. Three different resistor structures are proposed to achieve ultra-high resistance. While ranging in the order of several TY, the proposed ultra-high-resistance pseudoresistors occupy a small on-chip silicon area, which is one of the main issues in the design of analog front-end circuits in ultra-low power implantable biomedical microsystems. In addition, these ultra-high-value resistors lead to the use of a small capacitance to create a very small cut-off frequency. Therefore, the large area to implement capacitances is also considerably reduced. The proposed resistor structures have very small variations about 7% and 12% in a wide input voltage range (-0.5 V +0.5 V), thus significantly improving the total harmonic distortion of bioamplifiers and the analog front-end of the system. Simulation results of different circuits designed in a 180nm CMOS technology, are shown to demonstrate the advantages of the proposed ultra-high-resistance pseudo-resistors.
A self-powered asynchronous image sensor with independent in-pixel harvesting and sensing operations
R. Gomez-Merchan, J.A. Leñero-Bardallo and A. Rodríguez-Vázquez
Conference · IS&T International Symposium on Electronic Imaging 2023
A self-powered asynchronous sensor with a novel pixel architecture is presented. Pixels are autonomous and can harvest or sense energy independently. During the image acquisition, pixels toggle to a harvesting operation mode once they have sensed their local illumination level. With the proposed pixel architecture, most illuminated pixels provide an early contribution to power the sensor, while low-illuminated ones spend more time sensing their local illumination. Thus, the equivalent frame rate is higher than the one offered by conventional self-powered sensors that harvest and sense illumination in independent phases. The proposed sensor uses a Time-to-First-Spike readout that allows trading between image quality and data and bandwidth consumption. The device has HDR operation with a dynamic range of 80 dB. Pixel power consumption is only 70 pW. The article describes the sensors and pixel’s architectures in detail. Experimental results are provided and discussed. Sensor specifications are benchmarked against the art.
CMOS Front End for Interfacing Spin-Hall Nano-Oscillators for Neuromorphic Computing in the GHz Range
R. Fiorelli, E. Peralias, R. Mendez-Romero, M. Rajabali, A. Kumar, M. Zahedinejad, J. Akerman, F. Moradi, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper · Electronics, vol. 12, no. 1, article 230, 2023
MDPI ISSN: 2079-9292
Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4-20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 mu V even for an impedance as large as 300 ohm and a noise figure of 5.3 dB(300 ohm). A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.
PACOSYT: A Passive Component Synthesis Tool based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs
F. Passos, N. Lourenço, E. Roca, R. Martins, R. Castro-López, N. Horta and F.V. Fernández
Journal Paper · IEEE Journal of Microwaves, first online, 2023
IEEE ISSN: 2692-8388
In this paper, the application of regression-based supervised machine learning (ML) methods to the modeling of integrated inductors and transformers is examined. Different ML techniques are used and compared to improve accuracy. However, it is demonstrated that none of the ML techniques considered provided good results unless a smart modeling strategy, tailored to the specific design problem, is used. Taking advantage of these modeling strategies, high accuracy can be obtained when compared to full-wave electromagnetic (EM) simulations (less than 2% error) and experimental measurements (less than 5% error). The most accurate model, obtained by the appropriate combination of an ML technique and modeling strategy, has been integrated into a tool called PACOSYT. The tool uses optimization algorithms to allow the designer to obtain an inductor/transformer with optimal performances in just seconds while keeping the accuracy of EM simulations. Furthermore, the tool provides the passive component S parameter description file for seamless use in circuit simulations. The tool can be used standalone or integrated with design frameworks, like Cadence Virtuoso or AIDASoft, a framework for circuit optimization. To illustrate the different usages of the tool, several passive devices are synthesized, and hundreds of millimeter-wave power amplifiers are synthesized using AIDASoft together with PACOSYT. The tool has been developed using open-source Python frameworks and does not use any closed-source licenses. PACOSYT, which also allows other designers to create their models for different technologies, is made publicly available.
Effect of Device Mismatches in Differential Oscillatory Neural Networks
J. Shamsi, M.J. Avedillo, B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper · IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 2, pp 872-883, 2023
IEEE ISSN: 1549-8328
Analog implementation of Oscillatory Neural Networks (ONNs) has the potential to implement fast and ultra-low-power computing capabilities. One of the drawbacks of analog implementation is component mismatches which cause desynchronization and instability in ONNs. Emerging devices like memristors and VO2are particularly prone to variations. In this paper, we study the effect of component mismatches on the performance of differential ONNs (DONNs). Mismatches were considered in two main blocks: differential oscillatory neurons and synaptic circuits. To measure DONN tolerance to mismatches in each block, performance was evaluated with mismatches being present separately in each block. Memristor-bridge circuits with four memristors were used as the synaptic circuits. The differential oscillatory neurons were based on VO2-devices. The simulation results showed that DONN performance was more vulnerable to mismatches in the components of the differential oscillatory neurons than to mismatches in the synaptic circuits. DONNs were found to tolerate up to 20% mismatches in the memristance of the synaptic circuits. However, mismatches in the differential oscillatory neurons resulted in non-uniformity of the natural frequencies, causing desynchronization and instability. Simulations showed that 0.5% relative standard deviation (RSD) in natural frequencies can reduce DONN performance dramatically. In addition, sensitivity analyses showed that the high threshold voltage of VO2-devices is the most sensitive parameter for frequency non-uniformity and desynchronization.
The diverse meteorology of Jezero crater over the first 250 sols of Perseverance on Mars
J.A. Rodriguez-Manfredi, M. de la Torre Juarez, A. Sanchez-Lavega, R. Hueso, G. Martinez, M.T. Lemmon, C.E. Newman, A. Munguira, M. Hieta, L.K. Tamppari, J. Polkko, D. Toledo, E. Sebastian, M.D. Smith, I. Jaakonaho, M. Genzer, A. de Vicente-Retortillo, D. Viudez-Moreiras, M. Ramos, A. Saiz-Lopez, A. Lepinette, M. Wolff, R.J. Sullivan, J. Gomez-Elvira, V. Apestigue, P.G. Conrad, T. Del Rio-Gaztelurrutia, N. Murdoch, I. Arruego, D. Banfield, J. Boland, A.J. Brown, J. Ceballos, M. Dominguez-Pumar, S. Espejo, A.G. Fairén, R. Ferrandiz, E. Fischer, M. Garcia-Villadangos, S. Gimenez, F. Gomez-Gomez, S.D. Guzewich, A.-M. Harri, J.J. Jimenez, V. Jimenez, T. Makinen, M. Marin, C. Martin, J. Martin-Soler, A. Molina, L. Mora-Sotomayor, S. Navarro, V. Peinado, I. Perez-Grande, J. Pla-Garcia, M. Postigo, O. Prieto-Ballesteros, S.C.R. Rafkin, M.I. Richardson, J. Romeral, C. Romero, H. Savijärvi, J. T. Schofield, J. Torres, R. Urqui, S. Zurita & the MEDA team
Journal Paper · Nature Geoscience, 2023
NATURE ISSN: 1752-0894
NASA’s Perseverance rover’s Mars Environmental Dynamics Analyzer is collecting data at Jezero crater, characterizing the physical processes in the lowest layer of the Martian atmosphere. Here we present measurements from the instrument’s first 250 sols of operation, revealing a spatially and temporally variable meteorology at Jezero. We find that temperature measurements at four heights capture the response of the atmospheric surface layer to multiple phenomena. We observe the transition from a stable night-time thermal inversion to a daytime, highly turbulent convective regime, with large vertical thermal gradients. Measurement of multiple daily optical depths suggests aerosol concentrations are higher in the morning than in the afternoon. Measured wind patterns are driven mainly by local topography, with a small contribution from regional winds. Daily and seasonal variability of relative humidity shows a complex hydrologic cycle. These observations suggest that changes in some local surface properties, such as surface albedo and thermal inertia, play an influential role. On a larger scale, surface pressure measurements show typical signatures of gravity waves and baroclinic eddies in a part of the seasonal cycle previously characterized as low wave activity. These observations, both combined and simultaneous, unveil the diversity of processes driving change on today’s Martian surface at Jezero crater.