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On the Correlation of CNN Performance and Hardware Metrics for Visual Inference on a Low-Cost CPU-based Platform
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - International Conference on Systems, Signals and Image Processing IWSSIP 2019
[abstract]
While providing the same functionality, the various Deep Learning software frameworks available these days do not provide similar performance when running the same network model on a particular hardware platform. On the contrary, we show that the different coding techniques and underlying acceleration libraries have a great impact on the instantaneous throughput and CPU utilization when carrying out the same inference with Caffe, OpenCV, TensorFlow and Caffe2 on an ARM Cortex-A53 multi-core processor. Direct modelling of this dissimilar performance is not practical, mainly because of the complexity and rapid evolution of the toolchains. Alternatively, we examine how the hardware resources are distinctly exploited by the frameworks. We demonstrate that there is a strong correlation between inference performance - including power consumption - and critical parameters associated with memory usage and instruction flow control. This identified correlation is a preliminary step for the development of a simple empirical model. The objective is to facilitate selection and further performance tuning among the ever-growing zoo of deep neural networks and frameworks, as well as the exploration of new network architectures.

Guest Editorial Special Issue on the 2019 ISICAS: A CAS Journal Track Symposium
J.M. de la Rosa, E. Bonizzoni and F. Maloberti
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 10, pp 1607-1607, 2019
IEEE    DOI: 10.1109/TCSII.2019.2935214    ISSN: 1549-7747    » doi
[abstract]
This special issue of the IEEE Transactions on Circuits and Systems - Part II: Express Briefs (TCAS-II) includes papers presented at the International Symposium on Integrated Circuits and Systems (ISICAS), held in Venice, Italy, on 29-30 August 2019. This is the second edition of this journal track symposium as part of the initiative of the IEEE Circuits and Systems Society (CASS), started in 2018. The symposium is focused on original works reporting hybrid, System-in-Package (SiP) or System-on-Chip (SoC) implementations of circuits and systems with state-of-the-art experimental results.

Neuromorphic spiking neural networks and their memristor-CMOS hardware implementations
L.A. Camuñas-Mesa, B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper - Materials, vol. 12, no. 7, article number 2745, 2019
MDPI AG    DOI: 10.3390/ma12172745    ISSN: 1996-1944    » doi
[abstract]
Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal-Oxide-Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

Crypto anchors
V.S.K. Balagurusamy, C. Cabral, S. Coomaraswamy, E. Delamarche, D.N. Dillenberger, G. Dittmann, D. Friedman, O. Gokce, N. Hinds, J. Jelitto, A. Kind, A.D. Kumar, F. Libsch, J.W. Ligman, S. Munetoh, C. Narayanaswami, A. Narendra, A. Paidimarri, M.A. Prada-Delgado, J. Rayfield, C. Subramanian and R. Vaculin
Journal Paper - IBM Journal of Research and Development, vol. 63, no. 2-3, article number 4, 2019
IBM CORP    DOI: 10.1147/JRD.2019.2900651    ISSN: 0018-8646    » doi
[abstract]
Blockchain technology can increase visibility in supply-chain transactions and lead to more accurate tracing of goods as well as provide evidence of whether a product is authentic or not. A shared, distributed ledger or blockchain alone, however, does not guarantee correct and trustworthy supply-chain traceability. We argue that blockchain technology (and any other digital traceability solution) must be enhanced with methods to "anchor" physical objects into information technology, Internet-of-Things and blockchain systems. Only when trust from the digital domain is extended to the physical domain can the movement of goods be accurately traced (e.g., for callbacks and provenance) and product authenticity determined. In this paper, we introduce the concept of crypto anchors, propose a classification and system architecture, and give implementation examples for different use cases and industries.

Analysis of Linearity in FD-SOI Body-Input Voltage Controlled Ring Oscillators - Application to ADCs
J. Ahmadi-Farsani and J.M. de la Rosa
Conference - IEEE Midwest Symposium on Circuits and Systems MWSCAS 2019
[abstract]
This paper studies the use of the body terminal as control voltage of ring oscillators implemented in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) processes, thus allowing a wider tuning range of the threshold voltage. This effect is exploited in this work to improve the linearity of Voltage-Controlled Ring Oscillators (VCROs) to be used as building blocks of Analog-to-Digital Converters (ADCs). An intuitive analysis of basic VCRO current-starved inverter cells is carried out in order to derive an approximate expression of the voltage-to-frequency characteristic. Electrical simulations in a 28-nm node are shown to get insight about the influence of main design parameters and applied to the design of VCRO-based Sigma-Delta (SD) ADCs up to the layout level, whose performance metrics demonstrate the benefits of the presented approach.

Synthesis of mm-Wave circuits using EM-simulated passive structure libraries
F. Passos, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Millimeter-wave circuit design is extremely complex and time-consuming. One of the reasons is the dependence on electromagnetic simulators used to accurately predict the performance of the high amount of passive structures that compose such circuits. Also, achieving optimal performances is not trivial in the millimeter-wave regime. Although synthesis methodologies can aid the designer to achieve optimal circuit performances, the usage of electromagnetic simulators is prohibitive in such methodologies due to efficiency issues. In this work, a new synthesis methodology is presented where the accuracy of electromagnetic simulations can be included without losing efficiency.

Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Reliability in CMOS-based integrated circuits has always been a critical concern. In today′s ultra-scaled technologies, a time-varying kind of variability has raised that, on top of the well-known time-zero variability, threatens to shorten the lifetime of integrated circuits, both analog and digital. Effects like Bias Temperature Instability and Hot Carriers Injection need to be studied, characterized and modeled to include, and, thus, mitigate, their impact in the design of CMOS integrated circuits. This paper presents an array-based integrated circuit whose purpose is precisely that: to observe, quantify and characterize the impact of timedependent variability effects in a specific kind of circuits: Ring Oscillators.

Learning weights with STDP to build prototype images for classification
A. Vasudevan, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Design and Technology of Integrated Systems in Nanoscale Era DTIS 2019
[abstract]
The combination of Spike Timing Dependent Plasticity (STDP) and latency coding used in a spiking neural network has been shown to learn hierarchical features. In this paper we propose a new way to classify images using an SVM. Prototype images are built from the weights learned in an unsupervised manner using STDP. The prototype images are cross correlated with the input image and the peak of the cross correlation with each prototype image is used as additional features for an SVM. The network, demonstrated on the MNIST data set, achieves 99.15% testing accuracy which is the best reported accuracy for a SNN with unsupervised training.

TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Time-Dependent Variability has attracted increasing interest in the last years. In particular, phenomena such as Bias Temperature Instability, Hot Carrier Injection and Random Telegraph Noise can have a large impact on circuit reliability, and must be therefore characterized and modeled. For technologies in the nanometer range, these phenomena reveal a stochastic behavior and must be characterized in a massive manner, with enormous amounts of data being generated in each measurement. In this work, a novel tool with a user-friendly interface, which allows the robust and fullyautomated parameter extraction for RTN, BTI and HCI experiments, is presented.

Characterization of Implanted Stents through Neointimal Tissue Bioimpedance Simulations
J.M. Portillo-Anaya, P. Pérez, G. Huertas, A. Olmo, J.A. Serrano, A. Maldonado-Jacobi and A. Yúfera
Conference - International Conference of the IEEE Engineering in Medicine and Biology Society EMBC2019
[abstract]
This work describes how is possible the definition of the light hole or lumen in implanted stents affected by restenosis processes using the BioImpedance (BI) as biomarker. The main approach is based on the fact that neointimal tissues implied in restenosis can be detected and measured thanks to their respective conductivity and dielectric properties. For this goal, it is proposed a four-electrode setup for bioimpedance measurement. The influence of the several involved tissues in restenosis: fat, muscle, fiber, endothelium and blood, have been studied at several frequencies, validating the setup and illustrating the sensitivity of each one. Finally, a real example using a standard stent, has been analyzed for stable and vulnerable plaques in restenosis test cases, demonstrating that the proposed method is useful for the stent obstruction test. Bioimpedance simulation test has been performed using the electric physics module in COMSOL Multiphysics®.

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