IMSE Publications

Recent publications


A Quantum-Resistant Face Template Protection Scheme using Kyber and Saber Public Key Encryption Algorithms
R. Roman, R. Arjona, P. Lopez-Gonzalez, I. Baturone, A. Bromme, N. Damer, M. Gomez-Barrero, K. Raja, C. Rathgeb, A.F. Sequeira, M. Todisco and A. Uhl
Conference · Conference of the Biometrics-Special-Interest-Group BIOSIG 2022
abstract     

Considered sensitive information by the ISO/IEC 24745, biometric data should be stored and used in a protected way. If not, privacy and security of end-users can be compromised. Also, the advent of quantum computers demands quantum-resistant solutions. This work proposes the use of Kyber and Saber public key encryption (PKE) algorithms together with homomorphic encryption (HE) in a face recognition system. Kyber and Saber, both based on lattice cryptography, were two finalists of the third round of NIST post-quantum cryptography standardization process. After the third round was completed, Kyber was selected as the PKE algorithm to be standardized. Experimental results show that recognition performance of the non-protected face recognition system is preserved with the protection, achieving smaller sizes of protected templates and keys, and shorter execution times than other HE schemes reported in literature that employ lattices. The parameter sets considered achieve security levels of 128, 192 and 256 bits.

Teaching based on proposed by students designs: a case study
C.J. Jimenez-Fernandez, C. Baena-Oliva, P. Parra-Fernandez, M. Valencia-Barrero, F.E. Potestad-Ordoñez, E. Tena-Sanchez and A. Gallardo-Soto
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2022
abstract     

Learning digital design at RT level is enhanced by practical, lab-based tasks. These tasks, if chosen appropriately, can be highly motivating. The fact that the proposal is attractive to students is an important incentive. Working with FPGAs and development boards is a very suitable tool for carrying out designs of varying complexity. This paper presents an experience developed in the Advanced Digital Design course (4th year of the Degree) consisting of a design on FPGA proposed by the students themselves based on some common specifications, such as the use of a matrix of 8x8 LEDs and that the design has to interact with some external element.

Methodology and comparison of evaluation methods in electronic laboratories
E. Tena-Sanchez, F.E. Potestad-Ordonez, J.I. Guerrero-Alonso, D.F. Larios-Marin and J. Luque-Rodriguez
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2022
abstract     

There are different methodologies for the evaluation of the experimental development of students in university technical schools. Specifically, in electronic laboratories, the evaluation of the acquired competencies is not a simple task due to the large number of factors involved. In this work, an evaluation methodology is proposed consisting of voluntary laboratory sessions and a final exam. On the other hand, this methodology is compared with the previous one consisting of compulsory laboratory sessions, the evaluation of theoretical studies prior to the laboratory session, and continuous evaluation through the submission of practical reports during each session. In addition to the objective data on the number of fail/pass, we will present the impressions of both students and teachers who applied this methodology, as well as the most significant changes observed both in the attitude of the students and in the workload of both students and teachers.

ICs tester design and its effect on application in electronics laboratories
F.E. Potestad-Ordonez, C.J. Jimenez-Fernandez, A. Gallardo-Soto, M. Valencia-Barrero, C. Baena-Oliva, P. Parra-Fernandez and E. Tena-Sanchez
Conference · Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2022
abstract     

One of the best methods to help students assimilate the theoretical concepts about electronic circuits is to perform laboratory sessions with real components. Therefore, the use of integrated circuits in electronics laboratory sessions and exams is very common. Since the electronic training of the students is very different, it is frequent that the devices break and become useless after a bad connection or manipulation. This paper presents the design of an integrated circuit tester, specifically the 741 and 74LS00. The effect observed on the attitude of the students after using the device (functionality check performed with the student there), before the practical sessions and laboratory exams, will be presented, and the different impressions from the point of view of the teachers will be analyzed.

A high-voltage floating level shifter for a multi-stage charge-pump in a standard 1.8 V/3.3 V CMOS process
D. Palomeque-Mangut, A. Rodriguez-Vazquez and M. Delgado-Restituto
Journal Paper · AEU - International Journal of Electronics and Communications, vol. 156, article 154389, 2022
ELSEVIER    ISSN: 1434-8411
abstract      doi      

This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA.

Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems
M.C. Martínez-Rodríguez, L.F. Rojas-Muñoz, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 6, no.4, article 51, 2022
MDPI    ISSN: 2410-387X
abstract      doi      

The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.

Implementación hardware de un algoritmo ligero de cifrado
C. Fernández-García, V. Zúñiga-Ginzález, A. Casado-Galán, E. Tena-Sácnhez, F.E. Potestad-Ordóñez and C.J. Jiménez-Fernández
Conference · IX Jornadas de I+D+i & 1st International Workshop on STEM
abstract     

Abstract not available

Desarrollo de setup experimental para la realización de cartografía EM en sistemas criptográficos
A. Casado-Galán, V. Zúñiga-González, F.E. Potestad-Ordóñez, C. Fernández-García, C.J. Jiménez- Fernández and E. Tena-Sácnhez
Conference · IX Jornadas de I+D+i & 1st International Workshop on STEM
abstract     

El objetivo de la criptografía es garantizar la confidencialidad, integridad y disponibilidad de la información. En los dispositivos electrónicos, protegemos la información por medio de algoritmos criptográficos. Estos transforman la secuencia mediante operaciones matemáticas en diversas iteraciones haciendo que la información sea, con la potencia computacional de la que disponemos actualmente, imposible de recuperar sin conocer una determinada clave. Si bien teóricamente estos algoritmos son seguros, la implementación en circuitos electrónicos abre la puerta a vulnerabilidades que se pueden explotar para obtener información sobre el mensaje cifrado. Midiendo, por ejemplo, la emisión electromagnética (EM) de un circuito con instrumental apropiado para ello y tenemos un modelo matemático de este lo suficientemente preciso, podemos hackear el dispositivo y obtener la clave o mensaje cifrado. Este trabajo se centra en el desarrollo experimental de un setup de medida para realizar la cartografía EM de los sistemas criptográficos. Esto permite determinar los puntos de máxima emisión de información atacable. El setup experimental propuesto está totalmente automatizado desde un PC, donde con una mesa XY y el posicionamiento fijo de la sonda EM se puede barrer el área completa del dispositivo bajo test y capturar la emisión EM en cada punto.

Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4
M. Abernot, T. Gil, E. Kurylin, T. Hardelin, A. Magueresse,T. Gonos, M. Jiménez-Través, M.J. Avedillo de Juan and A. Todri-Sanial
Conference · IEEE International Joint Conference on Neural Networks IJCNN 2022
abstract     

Neuromorphic computing aims to emulate biological neural functions to overcome the memory bottleneck challenges with the current Von Neumann computing paradigm by enabling efficient and low-power computations. In recent years, there has been a tremendous engineering effort to bring neuromorphic computing for processing at the edge. Oscillatory Neural Networks (ONNs) are braininspired neural networks made of oscillators to mimic neuronal brain waves, typically visible on Electroencephalograms (EEG). ONNs provide massive parallelism using coupled oscillators and low power computation using oscillator phase dynamics. In this paper, we present for the first time how to use ONNs to perform obstacle avoidance on a mobile robot. Digitally implemented ONNs on FPGA are used and configured for obstacle avoidance inside the industrial surveillance robot E4 from the company, A.I.Mergence. We show that ONNs can perform real-time obstacle avoidance based on the sensory data from proximity sensors embedded on the E4 robot. The highly parallel architecture of ONNs not only allows fast real-time computation for obstacle avoidance applications but also opens up a novel computing paradigm for edge AI to enable low power and real-time sensing to action computing.

Special Session on RF/5G Test
W.R. Eisenstadt, M. Roos, D. Morris, J.L. Gonzalez-Jimenez, C. Mounet, M.J. Barragan, G. Leger, F. Cilici, E. Lauga-Larroze, S. Mir, S. Bourdel, M. Margalef-Rovira, I. Alaji, H. Ghanem, G. Ducournau and C. Gaquiere
Conference · IEEE European Test Symposium ETS 2022
abstract     

Abstract not available
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