Journals
1. A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria, F.V. Fernandez, Microelectronic Engineering, vol. 215, 111004, 2019.
DOI: 10.1016/j.mee.2019.111004
2. A Smart Noise- and RTN-Removal Method for Parameter Extraction of CMOS Aging Compact Models
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez, M. Nafria, Solid-State Electronics, vol. 159, pp. 99-105, 2019.
DOI: 10.1016/j.sse.2019.03.045
3. Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop
R. Martins, N. Lourenço, F. Passos, R. Povoa, A. Canelas, E. Roca, R. Castro-López, J. Sieiro, F.V. Fernández, N. Horta, IEEE Trans. on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, vol. 38(6), pp.989-1002, 2019.
DOI: 10.1109/TCAD.2018.2834394
4. A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits
F. Passos, R. González-Echevarría, E. Roca, R. Castro-López, F.V. Fernández, Soft Computing, vol. 23(13), PP.4911-4925, 2019.
DOI: 10.1007/s00500-018-3150-9
5. A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI and HCI
J. Diaz-Fortuny, J. Martin-Martinez, R. Rodriguez, R. Castro-Lopez, E. Roca, X. Aragonés, E. Baraja, D. Mateo, F.V. Fernandez and M. Nafria, IEEE Journal of Solid State Circuits, vol. 54(2), pp. 476-488, 2019.
DOI: 10.1109/JSSC.2018.2881923
6. Power and Speed Evaluation of Hyper-FET Circuits
J. Núñez, M.J. Avedillo, IEEE Access, vol. 7, pp 6724-6732, 2019.
DOI: 10.1109/ACCESS.2018.2889016
International Conferences
1. An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks
P. Martin-Lloret, J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
2. Synthesis of mm-Wave circuits using EM-simulated passive structure libraries
F. Passos, E. Roca, R. Castro-Lopez, N. Horta and F.V. Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
3. Experimental Characterization of Time-Dependent Variability in Ring Oscillators
J. Nuñez, E. Roca, R. Castro-Lopez, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
4. TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019.
5. Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez. Proc. Design Automation and Test in Europe DATE 2019.
6. New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez. Proc. Design Automation and Test in Europe DATE 2019.
7. A new time efficient methodology for the massive characterization of RTN in CMOS devices
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria. Proc. IEEE International Reliability Physics Symposium IRPS 2019.
8. Device circuit co-design of HyperFET transistors
J. Núñez, M. Jiménez and M.J. Avedillo. Proc. Conference on Design of Circuits and Integrated Systems DCIS 2019.
9. Device Circuit Co-Design of HyperFET Transistors
J. Núñez and M.J. Avedillo. Proc. International Forum on Information Systems and Technologies INFOS 2019.