Encontrados resultados para:
Autor: Manuel Jiménez Través
Año: Desde 2002
Artículos de revistas
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
A. Todri-Sanial, S. Carapezzi, C. Delacour, M. Abernot, T. Gil, Elisabetta Corti, S.F. Karg, J. Nüñez, M. Jiménez, M.J. Avedillo and B. Linares-Barranco
Journal Paper · IEEE Transactions on Neural Networks and Learning Systems, first online, 2021
Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and energy-efficient systems. Oscillatory neural networks (ONNs) are an alternative approach in emulating biological functions of the human brain and are suitable for solving large and complex associative problems. In this work, we investigate the dynamics of coupled oscillators to implement such ONNs. By harnessing the complex dynamics of coupled oscillatory systems, we forge a novel computation model--information is encoded in the phase of oscillations. Coupled interconnected oscillators can exhibit various behaviors due to the strength of the coupling. In this article, we present a novel method based on subharmonic injection locking (SHIL) for controlling the oscillatory states of coupled oscillators that allow them to lock in frequency with distinct phase differences. Circuit-level simulation results indicate SHIL effectiveness and its applicability to large-scale oscillatory networks for pattern recognition.
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
M. Abernot, T. Gil, M. Jiménez, J. Núñez, M.J. Avellido, B. Linares-Barranco, T. Gonos, T. Hardelin and A. Todri-Sanial
Journal Paper · Frontiers in Neuroscience, vol. 15, article 713054, 2021
Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called ‘data deluge gap ’). This has resulted in investigating novel computing paradigms and design approaches at all levels from materials to system-level implementations and applications. An alternative computing approach based on artificial neural networks uses oscillators to compute or Oscillatory Neural Networks (ONNs). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. Here, we address a fundamental problem: can we efficiently perform artificial intelligence applications with ONNs? We present a digital ONN implementation to show a proof-of-concept of the ONN approach of ‘computing-in-phase’ for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5 × 3 and 10 × 6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.
Insights into the Dynamics of Coupled VO2 Oscillators for ONNs
J. Núñez, J.M. Quintana, M.J. Avedillo, M. Jiménez, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper · IEEE Transactions on Circuits and Systems II: Express Briefs, first online, 2021
The collective behavior of many coupled oscillator systems is currently being explored for the implementation of different non-conventional computing paradigms. In particular, VO2 based nano-oscillators have been proposed to implement oscillatory neural networks that can serve as associative memories, useful in pattern recognition applications. Although the dynamics of a pair of coupled oscillators have already been extensively analyzed, in this paper, the topic is addressed more practically. Firstly, for the application mentioned above, each oscillator needs to be initialized in a given phase to represent the input pattern. We demonstrate the impact of this initialization mechanism on the final phase relationship of the oscillators. Secondly, such oscillatory networks are based on frequency synchronization, in which the impact of variability is critical. We carried out a comprehensive mathematical analysis of a pair of coupled oscillators taking into account both issues, which is a first step towards the design of the oscillatory neural networks for associative memory applications.
Oscillatory Neural Networks using VO2 based Phase Encoded Logic
J. Núñez, M.J. Avedillo, M. Jiménez, J.M. Quintana, A. Todri-Sanial, E. Corti, S. Karg and B. Linares-Barranco
Journal Paper · Frontiers in Neuroscience, vol. 15, article 655823, 2021
Nano-oscillators based on phase-transition materials are being explored for the implementation of different non-conventional computing paradigms. In particular, vanadium dioxide (VO 2) devices are used to design autonomous non-linear oscillators from which oscillatory neural networks (ONNs) can be developed. In this work, we propose a new architecture for ONNs in which sub-harmonic injection locking (SHIL) is exploited to ensure that the phase information encoded in each neuron can only take two values. In this sense, the implementation of ONNs from neurons that inherently encode information with two-phase values has advantages in terms of robustness and tolerance to variability present in VO2 devices. Unlike conventional interconnection schemes, in which the sign of the weights is coded in the value of the resistances, in our proposal the negative (positive) weights are coded using static inverting (non-inverting) logic at the output of the oscillator. The operation of the proposed architecture is shown for pattern recognition applications.
Hybrid Phase Transition FET Devices for Logic Computation
M. Jiménez, J. Núñez and M.J. Avedillo
Journal Paper · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp 1-8, 2020
Hybrid Phase Transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON to OFF current ratio. In this paper, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ONOFF current tradeoffs are evaluated at circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, on the basis of this analysis, the paper proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained which were lower than those achieved with low standby power (LSTP) FinFETs and high performance (HP) FinFETs. The paper also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.
Phase Transition FETs for Improved Dynamic Logic Gates
M.J. Avedillo, M. Jiménez and J. Núñez
Journal Paper · IEEE Electron Device Letters, vol. 39, no. 11, pp 1776-1779, 2018
Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and a boost in the ION/IOFF ratio and, thus, to solve power and energy limitations of CMOS technologies. In addition to the replacement of the transistors in conventional static CMOS logic circuits, the distinguishing features of Phase Change FETs can be exploited in other application domains or can be useful for solving specific design challenges. In this paper, we take advantage of them to implement a smart dynamic gate in which undesirable contention currents are reduced, leading to speed advantage without power penalties.
An Approach to the Device-Circuit Co-Design of HyperFET Circuits
M. Jiménez, J. Núñez and M.J. Avedillo
Conference · IEEE International Symposium on Circuits and Systems ISCAS 2020
In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 32% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 400 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power savings and suggest guidance both at device and circuit level to take full advantage of these devices.
Device circuit co-design of HyperFET transistors
J. Núñez, M. Jiménez and M.J. Avedillo
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2019
In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 50% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 80 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power advantages from the supply voltage reduction permitted by HyperFETs, and suggest guidance both at device and circuit level to take full advantage of these devices.
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
H.J. Quintero, M. Jimenez, M.J. Avedillo and J. Núñez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.
No hay resultados
Capítulos de libros
No hay resultados
No hay resultados