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Autor: Héctor Carrasco López
Año: Desde 2002

Artículos de revistas


A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs
A. Santana-Andreo, P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Integration, vol. 85, pp 1-9, 2022
resumen      doi      

PUFs based on the power-up values of an array of SRAM cells are a popular solution to provide secure and low-cost key generation suitable for IoT devices. However, SRAM cells do not always power up to the same value due to external factors like noise, temperature, or aging. This results in a decrease of reliability for the SRAM PUF, an issue generally solved by employing complex Error Correction Codes (ECCs). However, ECCs significantly increase the cost of the complete system. A way to alleviate this issue is the use of bit selection methods, which increase the reliability of the SRAM PUF by using only the power-up values of the most reliable cells (i.e., the SRAM cells that consistently power up to the same value). In this work, the reduction in ECC complexity through a bit selection method based on the Data Retention Voltage metric is demonstrated.

Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Microelectronics Reliability, vol. 118, article 114049, 2021
resumen      doi      pdf

The utilization of power-up values in SRAM cells to generate PUF responses for chip identification is a subject of intense study. The cells used for this purpose must be stable, i.e., the cell should always power-up to the same value (either ‘0’ or ‘1’). Otherwise, they would not be suitable for the identification. Some methods have been presented that aim at increasing the reliability of SRAM PUFs by identifying the strongest cells, i.e., the cells that more consistently power-up to the same value. However, these methods present some drawbacks, in terms of either their practical realization or their actual effectiveness in selecting the strongest cells at different scenarios, such as temperature variations or when the circuits have suffered aging-related degradation. In this work, the experimental results obtained for a new method to classify the cells according to their power-up strength are presented and discussed. The method overcomes some of the drawbacks in previously reported methods. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation and temperature variations, which ultimately translates into the construction of reliable SRAM-based PUFs.

Congresos


A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, J. Diaz-Fortuny, R. Castro, E. Roca and F.V. Fernandez
Conference · IEEE International Reliability Physics Symposium IRPS 2022
resumen     

Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.

Improving the reliability of SRAM-based PUFs under varying conditions
P. Sarazá-Canflanca, H. Carrasco-López, P. Brox, R. Castro-López, E. Roca and F.V. Fernández
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2020
resumen     

Abstract not available

Improving the reliability of SRAM-based PUFs in the presence of aging
P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Design and Technology of Integrated Systems in Nanoscale Era DTIS 2020
resumen     

The utilization of power-up values in SRAM cells for the generation of PUF responses has been widely studied. It is important that the cells used for this purpose are stable, i.e., the cells must have a strong tendency towards one of the two possible values (‘ ‘0 ’ or ‘1 ’). Some methods have been presented that aim at increasing the reliability of this type of PUFs by selecting the strongest cells among a set of them. However, they feature some drawbacks, either in terms of their practical feasibility or of their actual effectiveness selecting the strongest cells in different scenarios. In this work, the experimental results obtained for a new method to classify the cells according to their strength are presented and discussed. The technique overcomes some of the drawbacks that the previous methods present. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation, which translates into the construction of reliable SRAM-based PUFs.

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