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Publicada la segunda edición del libro 'Sigma-Delta Converters: Practical Design Guide', de José M. de la Rosa, investigador del IMSE-CNM y profesor de la Universidad de Sevilla.
Caracterización de Señales de Alta Velocidad: Fundamentos y Aplicaciones de Integridad de Señal.
29 Noviembre 2018
Sigma-Delta ADCs for IoT - Basics and Innovations.
Second Seasonal School in 'Circuits and Systems for the Industrial Internet-of-Things' (CAS4IIoT)
José M. de la Rosa
Universidade Nova de Lisboa (FCT NOVA), Portugal
29 Noviembre 2018
Semiconductor Intellectual Property (IP) start-ups.
Moises E. Robinson, Presidente y Cofundador de Vidatronic, Inc.
Salón de Grados del IMSE.
16 Noviembre 2018
Facultad de Física (US)
16 Noviembre 2018
IES San José de la Rinconada
15 Noviembre 2018

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Últimas publicaciones
PVT-robust CMOS programmable chaotic oscillator: Synchronization of two 7-scroll attractors  »
Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2-7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μm CMOS technology. Post-layout and process-voltage-temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master-slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

Journal Paper - Electronics, vol. 7, no. 10, article 252, 2018 MDPI
DOI: 10.3390/electronics7100252    ISSN: 2079-9292    » doi
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, C. Sanchez-Lopez and F.V. Fernandez-Fernandez
FPGA design example for maximum operating frequency measurements  »
The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it is presented with a low complexity, it is not possible to do it in a single practice session. This paper presents, as a demonstrator, the design at RT level and its implementation in FPGA of a digital system that uses the Trivium flow cipher and on which measurements of maximum operating frequency are made. This circuit is designed in three laboratory sessions of about two hours each.

Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
C.J. Fernandez, P.P. Fernandez, C.B. Oliva, M.V. Barrero and F.E. Potestad-Ordoñez
Distance measurement as a practical example of FPGA design  »
Digital design learning at the RT level requires practical examples and as learning progresses, the examples need to become more complex. FPGAs and development boards offer a very suitable platform for the implementation of these designs. However, classroom practice sessions usually last two hours, which does not allow the complexity of the designs be high enough. For this reason, interesting designs that can be made in several sessions are required In this paper, the construction of a distance measuring system is presented as a demonstrator. For this purpose, a distance measurement module based on ultrasound is available and the results are displayed in 7-segment displays on a Nexys4 board.

Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
C.J. Fernandez, P.P. Fernandez, C.B. Oliva, M.V. Barrero and F.E. Potestad-Ordoñez
On-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camera  »
This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image recognition on deep neural networks. Both the hardware configuration and the network model can be changed any time on the fly. Up to 24 hardware-model combinations are possible, enabling dynamic reconfiguration according to prescribed application requirements.

Conference - ACM International Conference on Distributed Smart Cameras ICDSC 2018 DOI: 10.1145/3243394.3243705    » doi
D. Velasco-Montero, J. Fernández-Berni, R. Carmona-Galan and A. Rodríguez-Vázquez
On practical issues for stochastic STDP hardware with 1-bit synaptic weights  »
In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

Journal Paper - Frontiers in Neuroscience, vol. 12, article 665, 2018 FRONTIERS RESEARCH FOUNDATION
DOI: 10.3389/fnins.2018.00665    ISSN: 1662-4548    » doi
A. Yousefzadeh, E. Stromatias, M. Soto, T. Serrano-Gotarredona and B. Linares-Barranco

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miércoles, 21 de noviembre de 2018
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