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Se buscan candidatos para un contrato de Titulado Superior en el área de Tecnología Electrónica y de Comunicaciones, asociado al Proyecto de Investigación MARAGDA (Aproximación multi-nivel al diseño orientado a la fiabilidad de circuitos integrados analógicos y digitales).
♦ Seminario Addlink
Modelado multifísico de MEMS y semiconductores dentro del entorno de trabajo de COMSOL Multiphysics.
4 Mayo 2016
Información e inscripción »
♦ Seminario IMSE Forum
Bayesian networks & Causal inference.
Dr. Alexandre Aussem, Professor in Computer Science CNRS, Université Lyon-1
3 Mayo 2016
[+info] »
♦ Visitas al IMSE
IES Sierra de Aras.
20 Abril 2016
IES Miguel Servet.
19 Abril 2016
♦ IEEE Circuits and Systems Society
El investigador del IMSE-CNM Dr. Manuel Delgado Restituto ha sido nombrado Vicepresidente de Publicaciones de la Sociedad de Circuitos y Sistemas de IEEE para el año 2016.
Convocatoria de becas de Introducción a la Investigación para estudiantes de posgrado. Información general y listado de los trabajos de investigación ofertados para su realización en el Instituto de Microelectrónica de Sevilla.
Plazo de solicitud: 11 de abril a 2 de mayo de 2016

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Últimas publicaciones
Comparative study by IBIC of Si and SiC diodes irradiated with high energy protons  »
The transport properties of a series of Si and SiC diodes have been studied using the Ion Beam Induced Charge (IBIC) technique. Structural defects were induced into the samples during the irradiation with 17 MeV protons. The experimental values of the charge collection efficiency (CCE) vs bias voltages have been analyzed using a modified drift-diffusion model, which takes into account the recombination of carriers in the neutral and depletion regions. From these simulations, we have obtained the values of the carrier's lifetime for pristine and irradiated diodes, which are found to degrade faster in the case of the SiC samples. However, the decrease of the CCE at high bias voltages is more important for the Si detectors, indicative of the lower radiation hardness of this material compared to SiC. The nature of the proton-induced defects on Si wafers has been studied by Positron Annihilation Spectroscopy (PAS) and Doppler Broadening Spectroscopy (DBS). The results suggest that the main defect detected by the positrons in p-type samples is the divacancy while for n-type at least a fraction of the positron annihilate in another defect. The concentration of defects is much lower than the number of vacancies predicted by SRIM.

Journal Paper - Nuclear Instruments and Methods in Physics Research, Section B: Beam Interactions with Materials and Atoms, vol. 372, pp 143-150, 2016 ELSEVIER
DOI: 10.1016/j.nimb.2015.12.029    ISSN: 0168-583X    » doi
J. Garcia Lopez, M.C. Jimenez-Ramos, M. Rodriguez-Ramos, J. Ceballos, F. Linez and J. Raisanen
A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs  »
This paper investigates the capability of an architecture with digitally controllable gain and power consumption, for mitigating the effects of process variations on CMOS Low-Noise Amplifiers (LNAs). A 130-nm 1.2-V LNA with the proposed architecture is designed, based on the analysis of variability in LNAs with a traditional architecture under different biasing currents conditions, and the corresponding effects in the performance of a complete receiver context. Two different adjusting strategies are evaluated, which could be implemented with already reported Built-in Self-Test (BIST) circuits. Results show that the proposed architecture allows yield enhancement with low-power operation compared to traditional LNAs.

Journal Paper - IEEE Latin America Transactions, vol. 14, no. 1, pp. 13-19, 2016 IEEE
ISSN: 1548-0992    
J.L. González, J.C. Cruz, R.L. Moreno and D. Vázquez
Energy-Aware Low-Power CMOS LNA with Process-Variations Management  »
A reconfigurable low-noise amplifier (LNA) with digitally controllable gain and power consumption is presented. This architecture allows increasing power consumption only when required, that is, to improve LNA's radiofrequency performance at extreme communication-channel conditions and/or to counteract the effect of process, voltage, and temperature variations. The proposed design leads to significant power saving when a relaxed operation is acceptable. The LNA is implemented in a 130 nm 1.2 V CMOS technology for a 2.4 GHz IEEE-802.15.4 application. Simulated LNA performance (taking into account the worst cases under process variations) is comparable to recently published works.

Journal Paper - Active and Passive Electronic Components, vol. 2016, Article ID 8351406, 2016 HINDAWI
DOI: 10.1155/2016/8351406    ISSN: 1563-5031    » doi
J.L. González, R.L. Moreno, J.C. Cruz and D. Vázquez
Low power two-stage comb decimation structures for high decimation factors  »
This paper presents power and area analysis of two-stage comb-based decimation structures for high decimation factors. The first stage is either in a recursive form cascaded-integrator-comb (CIC) or in a non-recursive form, while the second stage is in a recursive form. The proposed structures are compared with a single CIC structure. We demonstrated how to choose the decimation factor of the first stage in order to get simultaneously the highest possible power reduction and the lowest possible area increase, in a comparison with a single CIC structure. Additionally, the modified two-stage structure with an increased attenuation and a reduced power consumption is presented. Analysis is supported by MATLAB simulations and validated by the VHDL implementations.

Journal Paper - Analog Integrated Circuits and Signal Processing, First online: 06 February 2016, pp. 1-10, 2016 SPRINGER
DOI: 10.1007/s10470-016-0700-x    ISSN: 0925-1030    » doi
G. Molina-Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
AES T-Box tampering attack  »
The use of embedded block memories (BRAMs) in Xilinx FPGA devices makes it possible to store the T-Boxes that are employed to implement the AES block cipher's SubBytes and MixColumns operations. Several studies into BRAM resistance to side-channel attacks have been reported in the literature, whereas this paper presents a novel attack based on tampering the BRAMs storing the T-Boxes. This approach allows recovering the key using a ciphertext-only attack for all AES key sizes. The complexity of the attack makes it completely feasible. The attack was mounted against previously reported FPGA-based AES implementations, taking into account the different design criteria used in each case and focusing mainly on the implementation of the final round of the AES algorithm, which plays a crucial role in the analysis. Three different final round implementations extracted from well-known existing architectures are analyzed in this work. The paper also discusses some countermeasures with regard to security, performance and FPGA resource utilization. The attack is presented against FPGA-based implementations but it can be extended to software architectures as well.

Journal Paper - Journal of Cryptographic Engineering, vol. 6, no. 1, pp 31-48, 2016 SPRINGER
DOI: 10.1007/s13389-015-0103-4    ISSN: 2190-8516    » doi
A. Cabrera-Aldaya, A.J. Cabrera-Sarmiento and S. Sánchez-Solano

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