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En el marco de la convocatoria abierta por el CSIC para la formalización de contratos en prácticas en distintos institutos, centros y unidades del CSIC para la promoción del empleo joven e implantación de la Garantía Juvenil, el Instituto de Microelectrónica de Sevilla ofrece una plaza de Técnico Superior y otra de Titulado Superior para llevar a cabo la actuación denominada "Prestación del servicio de test de eventos simples mediante láser pulsado en el IMSE-CNM".
Nuevo plazo de presentación de solicitudes: hasta el 18 de febrero de 2016.
(Titulaciones e información adicional en el enlace)
♦ Defensa de Tesis Doctoral
On-Chip CMOS Vision System for High-Speed Applications.
Francisco J. Jiménez Garrido.
8 Febrero 2016
Móviles 5G y la radio definida por software.
José Manuel de la Rosa.
21 Enero 2016
Convocatoria de becas para Doctorado en Universidades y Centros de Investigación Españoles de la Obra Social "la Caixa".
Periodo de admisión de solicitudes: hasta el 29 de Febrero de 2016 a las 14:00 horas (hora peninsular)

IMSE-CNM: Instituto Mixto CSIC/Universidad de Sevilla

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Últimas publicaciones
Low power two-stage comb decimation structures for high decimation factors  »
This paper presents power and area analysis of two-stage comb-based decimation structures for high decimation factors. The first stage is either in a recursive form cascaded-integrator-comb (CIC) or in a non-recursive form, while the second stage is in a recursive form. The proposed structures are compared with a single CIC structure. We demonstrated how to choose the decimation factor of the first stage in order to get simultaneously the highest possible power reduction and the lowest possible area increase, in a comparison with a single CIC structure. Additionally, the modified two-stage structure with an increased attenuation and a reduced power consumption is presented. Analysis is supported by MATLAB simulations and validated by the VHDL implementations.

Journal Paper - Analog Integrated Circuits and Signal Processing, First online: 06 February 2016, pp. 1-10, 2016 SPRINGER
DOI: 10.1007/s10470-016-0700-x    ISSN: 0925-1030    » doi
G. Molina-Salgado, G. Jovanovic-Dolecek and J.M. de la Rosa
Image feature extraction acceleration  »
Abstract not avaliable

Book Chapter - Image Feature Detectors: Foundations, Innovations and Applications. A.I. Awad and M. Hassaballah (Eds.), 2015 SPRINGER

ISBN: 978-3-319-28852-9    
J. Fernández-Berni, M. Suárez-Cambre, R. Carmona-Galán, V. Brea, R. del Río, D. Cabello and Á. Rodríguez-Vázquez
A Bio-Inspired Vision Sensor with Dual Operation and Readout Modes  »
This paper presents a novel event-based vision sensor with two operation modes: 1) intensity mode and spatial contrast detection. They can be combined with two different readout approaches: 1) pulse density modulation and time-to-first spike. The sensor is conceived to be a node of an smart camera network made up of several independent an autonomous nodes that send information to a central one. The user can toggle the operation and the readout modes with two control bits. The sensor has low latency (below 1 ms under average illumination conditions), low power consumption (19 mA), and reduced data flow, when detecting spatial contrast. A new approach to compute the spatial contrast based on inter-pixel event communication less prone to mismatch effects than diffusive networks is proposed. The sensor was fabricated in the standard AMS4M2P 0.35-μm process. A detailed system-level description and experimental results are provided.

Journal Paper - IEEE Sensors Journal, vol. 16, no. 2, pp. 317-330, 2016 IEEE
DOI: 10.1109/JSEN.2015.2483898    ISSN: 1530-437X    » doi
J.A. Lenero-Bardallo, P. Hafliger, R. Carmona-Galan and A. Rodriguez-Vazquez
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques  »
The growing demand for new and more complex wireless communication devices is pushing continuous innovation in the design of Radio Frequency Integrated Circuits. New and stronger performance requirements are to be met in shorter times-to-market, using technologies which are not always RF-friendly, making the design of these circuits a challenging job.
Miniaturization and cost have driven CMOS technologies as attractive candidates for the design of RF integrated circuits. Furthermore, the scaling of these technologies down to the nanometric regime has pushed their frequencies of operation well into the millimeter-wave region. Currently, CMOS coexists with other high-performance technologies, like SiGe, providing the RF designer with a wide catalog of alternatives for the optimal system design considering a variety of aspects like size, cost, power consumption, performance, etc. .
One the most important challenges of RF design is the lack of good simulation and modeling tools that can combine the electrical characteristics of the different devices (active and passive) with their electromagnetic properties when operating at GHz frequencies. The development of new simulation methodologies and mathematical modeling for RFIC are crucial aspects for designing RF circuits that fulfill the requirements of the communication standards and effectively reduce the design time.

Journal Paper - Integration, the VLSI Journal, vol. 52, pp. 183-184, 2016 ELSEVIER
DOI: 10.1016/j.vlsi.2015.11.001    ISSN: 0167-9260    » doi
E. Roca and J. Sieiro
Semi-empirical RF MOST model for CMOS 65nm technologies: Theory, extraction method and validation  »
This paper presents a simple but accurate semi-empirical model especially focused on 65. nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5. GHz and 5.3. GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.

Journal Paper - Integration, the VLSI Journal, vol. 52, pp 228-236, 2016 ELSEVIER
DOI: 10.1016/j.vlsi.2015.07.018    ISSN: 0167-9260    » doi
R. Fiorelli and E. Peralías

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