Consejo Superior de Investigaciones Científicas · Centro Nacional de Microelectrónica
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Participación del Instituto de Microelectrónica de Sevilla en la Noche Europea de los Investigadores 2015.
25 Septiembre 2015
El profesor de la Universidad de Sevilla e investigador del IMSE-CNM Dr. Ángel Rodríguez Vázquez, imparte una charla dentro del ciclo de conferencias organizado por la Univ. de Sevilla para conmemorar el Año Internacional de la Luz.
8 Octubre 2015
Tecnologías de Medida de Materiales.
14 Octubre 2015
La Secretaría Gral. Adjunta de Recursos Humanos del CSIC, en colaboración con el Instituto de Microelectrónica de Sevilla, organiza este curso a celebrar en las instalaciones del IMSE. Dirigido al personal que preste sus servicios en los centros e institutos del CSIC. Admisión de solicitudes: hasta el 29 Mayo 2015.
19 a 23 Octubre 2015

El IMSE en la Noche Europea de los Investigadores

Oferta de servicios basados en el sistema automático de test ATE Agilent 93000

International Conference on Distributed Smart Cameras
September 8-11, 2015
Seville, Spain

El IMSE en los medios

Tríptico informativo

El IMSE en Linkedin

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El IMSE en Digital.CSIC

El IMSE en Digital.CSIC

Últimas publicaciones
Feedforward Categorization on AER Motion Events Using Cortex-Like Features in a Spiking Neural Network  »
This paper introduces an event-driven feedforward categorization system, which takes data from a temporal contrast address event representation (AER) sensor. The proposed system extracts bio-inspired cortex-like features and discriminates different patterns using an AER based tempotron classifier (a network of leaky integrate-and-fire spiking neurons). One of the system's most appealing characteristics is its event-driven processing, with both input and features taking the form of address events (spikes). The system was evaluated on an AER posture dataset and compared with two recently developed bio-inspired models. Experimental results have shown that it consumes much less simulation time while still maintaining comparable performance. In addition, experiments on the Mixed National Institute of Standards and Technology (MNIST) image dataset have demonstrated that the proposed system can work not only on raw AER data but also on images (with a preprocessing step to convert images into AER events) and that it can maintain competitive accuracy even when noise is added. The system was further evaluated on the MNIST dynamic vision sensor dataset (in which data is recorded using an AER dynamic vision sensor), with testing accuracy of 88.14%.

Journal Paper - IEEE Transactions on Neural Networks and Learning Systems, vol. 26, no. 9, pp 1963-1978, 2015
DOI: 10.1109/TNNLS.2014.2362542   » doi
ISSN: 2162-237X
B. Zhao, R. Ding, S. Chen, B. Linares-Barranco and H. Tang
On the convex formulation of area for slicing floorplans  »
Abstract In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with continuous convex functions of the width (height). It is proved that the area of a compact slicing floorplan is a convex function of its width (height). The convexity is shown for the cases with and without dead (empty) space. This feature can be exploited to efficiently optimize the dimensions of layout components with multiple variants, without enumerating all possible combinations. Layout of a voltage-doubler circuit is used to quantitatively verify the proof.

Journal Paper - Integration, the VLSI Journal, vol. 50, pp 74-80, 2015
DOI: 10.1016/j.vlsi.2015.01.008   » doi
ISSN: 0167-9260
A. Unutulmaz, G. Dündar and F.V. Fernández
Background Digital Calibration of Comparator Offsets in Pipeline ADCs  »
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, on-line first, art. 99, 2015
DOI: 10.1109/TVLSI.2014.2335233   » doi
ISSN: 1063-8210
A.J. Ginés, E. Peralías and A. Rueda
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach  »
This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.

Journal Paper - IEEE Transactions on Control Systems Technology, vol. 23, no. 3, pp 842-854, 2015
DOI: 10.1109/TCST.2014.2345094   » doi
ISSN: 1063-6536
M.C. Martínez-Rodríguez, P. Brox, P. and I. Baturone
Plasticity in memristive devices for spiking neural networks  »
Memristive devices present a new device technology allowing for the realization of compact non-volatile memories. Some of them are already in the process of industrialization. Additionally, they exhibit complex multilevel and plastic behaviors, which make them good candidates for the implementation of artificial synapses in neuromorphic engineering. However, memristive effects rely on diverse physical mechanisms, and their plastic behaviors differ strongly from one technology to another. Here, we present measurements performed on different memristive devices and the opportunities that they provide. We show that they can be used to implement different learning rules whose properties emerge directly from device physics: real time or accelerated operation, deterministic or stochastic behavior, long term or short term plasticity. We then discuss how such devices might be integrated into a complete architecture. These results highlight that there is no unique way to exploit memristive devices in neuromorphic systems. Understanding and embracing device physics is the key for their optimal use.

Journal Paper - Frontiers in Neuroscience, vol. 9, Article 51, 2015
DOI: 10.3389/fnins.2015.00051   » doi
ISSN: 1662-4548
S. Saïghi, C.G. Mayr, T. Serrano-Gotarredona, H. Schmidt, G. Lecerf, J. Tomas, J. Grollier, S. Boyn, A.F. Vincent, D. Querlioz, S. La Barbera, F. Alibart, D. Vuillaume, O. Bichler, C. Gamrat and B. Linares-Barranco
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