Consejo Superior de Investigaciones Científicas · Centro Nacional de Microelectrónica
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El Consejo Superior de Investigaciones Científicas ha concedido el tercer premio entre los planes de gestión de recursos elaborados por las gerencias de institutos y centros del CSIC en Andalucía al Instituto de Microelectrónica de Sevilla.
12 Mayo 2015
La Secretaría Gral. Adjunta de Recursos Humanos del CSIC, en colaboración con el Instituto de Microelectrónica de Sevilla, organiza este curso a celebrar en las instalaciones del IMSE los días 19 a 23 de octubre. Dirigido al personal que preste sus servicios en los centros e institutos del CSIC.
Periodo de admisión de solicitudes: Hasta el 29/05/2015
Convocatoria de becas de Introducción a la Investigación para estudiantes de posgrado.
Periodo de admisión de solicitudes: Hasta el 25/05/2015
♦ Seminario IMSE-Forum
Formación avanzada en Web of Science. Impartida por personal de Thomson Reuters. Organizado por FECYT.
13 Mayo 2015
Analizadores de Potencia y Fuentes de Alimentación inteligentes. La nueva revolución en electrónica de potencia.
15 Abril 2015

International Conference on Distributed Smart Cameras
September 8-11, 2015
Seville, Spain

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Tercer premio al Instituto de Microelectrónica de Sevilla

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Últimas publicaciones
An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs  »
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for highperformance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm).

Conference Paper - IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
J. Núñez, A.J. Ginés, E.J. Peralías and A. Rueda
Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach  »
This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.

Journal Paper - IEEE Transactions on Control Systems Technology, vol. 23, no. 3, pp 842-854, 2015
DOI: 10.1109/TCST.2014.2345094   » doi
ISSN: 1063-6536
M.C. Martínez-Rodríguez, P. Brox, P. and I. Baturone
Plasticity in memristive devices for spiking neural networks  »
Memristive devices present a new device technology allowing for the realization of compact non-volatile memories. Some of them are already in the process of industrialization. Additionally, they exhibit complex multilevel and plastic behaviors, which make them good candidates for the implementation of artificial synapses in neuromorphic engineering. However, memristive effects rely on diverse physical mechanisms, and their plastic behaviors differ strongly from one technology to another. Here, we present measurements performed on different memristive devices and the opportunities that they provide. We show that they can be used to implement different learning rules whose properties emerge directly from device physics: real time or accelerated operation, deterministic or stochastic behavior, long term or short term plasticity. We then discuss how such devices might be integrated into a complete architecture. These results highlight that there is no unique way to exploit memristive devices in neuromorphic systems. Understanding and embracing device physics is the key for their optimal use.

Journal Paper - Frontiers in Neuroscience, vol. 9, Article 51, 2015
DOI: 10.3389/fnins.2015.00051   » doi
ISSN: 1662-4548
S. Saïghi, C.G. Mayr, T. Serrano-Gotarredona, H. Schmidt, G. Lecerf, J. Tomas, J. Grollier, S. Boyn, A.F. Vincent, D. Querlioz, S. La Barbera, F. Alibart, D. Vuillaume, O. Bichler, C. Gamrat and B. Linares-Barranco
A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement  »
The design and measurements of a CMOS 64×64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reversed start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.

Conference Paper - Image Sensors and Imaging Systems 2015
I. Vornicu, R. Carmona-Galán and Á. Rodríguez-Vázquez
Automatic ROI for remote photoplethysmography using PPG and color features  »
Remote photoplethysmography (rPPG) enables contact-less monitoring of the blood volume pulse using a regular camera, thus providing valuable information about the cardiovascular system. However, the quality of the acquired rPPG signal is strongly affected by the region of skin where the analysis is carried out and, therefore, to be confident of obtaining valid information, a pre-selection of the region-of-interest (ROI) for the PPG analysis is necessary. In this paper, we propose a method for the automatic extraction of this ROI combining the local characteristics of the PPG-signal with the color information using fuzzy logic. Results of the quality of the ROI extraction and its application on pulse rate detection are provided.

Conference Paper - 10th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications VISIGRAPP 2015
E. Calvo-Gallego and G. de Haan
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