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♦ Premio Extraordinario de Doctorado
Alberto Rodríguez Pérez, estudiante de doctorado en el Instituto de Microelectrónica de Sevilla y la Universidad de Sevilla, ha recibido el Premio Extraordinario de Doctorado del curso 2012-2013 por la tesis Diseño de sensores implantables para la adquisición de señales neurocorticales.
El Consejo Superior de Investigaciones Científicas ha concedido el tercer premio entre los planes de gestión de recursos elaborados por las gerencias de institutos y centros del CSIC en Andalucía al Instituto de Microelectrónica de Sevilla.
12 Mayo 2015
La Secretaría Gral. Adjunta de Recursos Humanos del CSIC, en colaboración con el Instituto de Microelectrónica de Sevilla, organiza este curso a celebrar en las instalaciones del IMSE los días 19 a 23 de octubre. Dirigido al personal que preste sus servicios en los centros e institutos del CSIC.
Periodo de admisión de solicitudes: Hasta el 29/05/2015
Convocatoria de becas de Introducción a la Investigación para estudiantes de posgrado.
Periodo de admisión de solicitudes: Hasta el 25/05/2015
♦ Seminario IMSE-Forum
Formación avanzada en Web of Science. Impartida por personal de Thomson Reuters. Organizado por FECYT.
13 Mayo 2015

International Conference on Distributed Smart Cameras
September 8-11, 2015
Seville, Spain

Memoria IMSE-CNM 2011/2012
[Versión HQ: 29MB »»]

Oferta de servicios basados en el sistema automático de test ATE Agilent 93000


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Tercer premio al Instituto de Microelectrónica de Sevilla

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Últimas publicaciones
On the convex formulation of area for slicing floorplans  »
Abstract In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with continuous convex functions of the width (height). It is proved that the area of a compact slicing floorplan is a convex function of its width (height). The convexity is shown for the cases with and without dead (empty) space. This feature can be exploited to efficiently optimize the dimensions of layout components with multiple variants, without enumerating all possible combinations. Layout of a voltage-doubler circuit is used to quantitatively verify the proof.

Journal Paper - Integration, the VLSI Journal, vol. 50, pp 74-80, 2015
ELSEVIER
DOI: 10.1016/j.vlsi.2015.01.008   » doi
ISSN: 0167-9260
A. Unutulmaz, G. Dündar and F.V. Fernández
Physical vs. Surrogate Models of Passive RF Devices  »
The accuracy of high-frequency models of passive RF devices, e.g., inductors or transformers, presents one of the most challenging problems for RF integrated circuits. Accuracy limitations lead RF designers to time-consuming iterations with electromagnetic simulators. This paper will explore and compare two advanced modeling techniques. The first one is based on the segmented model approach, in which each device segment is characterized with a lumped element model. The second technique is based on the generation of surrogate models from the electromagnetic simulation of a set of device samples. Different modeling strategies (frequency separation, filtering according to self-resonance frequency, etc.) will be considered. Efficiency and accuracy of both, physical and surrogate, modeling techniques will be compared using a Si process technology.

Conference Paper - IEEE International Symposium on Circuits and Systems ISCAS 2015
F. Passos, M. Kotti, R. González-Echevarría, M.H. Fino, M. Fakhfakh, E. Roca, R.Castro-López and F.V. Fernández
On the Calibration of a SPAD-Based 3D Imager with in-Pixel TDC Using a Time-Gated Technique  »
The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. The overall full-width half-maximum (FWHM) of the detector ensemble SPAD plus TDC is 690ps. The sensor has been fabricated in a 0.18μm standard CMOS technology which features an average dark-count rate (DCR) of 42Khz at 1V excess voltage (Ve) and room temperature. The detector successfully uses its time-gating capability to mitigate this large amount of noise enabling the sensor for accurate time-of-flight (ToF) measurements. The effectiveness of the time-gating technique is experimentally demonstrated. According to measurements, a time window of 400ns is enough to ensure that the TDC is triggered by light rather than by spurious events.

Conference Paper - IEEE International Symposium on Circuits and Systems ISCAS 2015
I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Design Considerations for A Low-Noise CMOS Image Sensor  »
This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.

Conference Paper - Image Sensors and Imaging Systems 2015
A. González-Márquez, A. Charlet, A. Villegas, F. Jiménez-Garrido, F. Medeiro, R. Domínguez-Castro and A. Rodríguez-Vázquez
Background Digital Calibration of Comparator Offsets in Pipeline ADCs  »
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, on-line first, art. 99, 2015
IEEE
DOI: 10.1109/TVLSI.2014.2335233   » doi
ISSN: 1063-8210
A.J. Ginés, E. Peralías and A. Rueda
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