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Participación del Instituto de Microelectrónica de Sevilla en la Noche Europea de los Investigadores 2015.
25 Septiembre 2015
♦ Defensas de Trabajos Fin de Máster
- Sensor capacitivo de bajo consumo para trans-pondedores RFID
Almudena Rivadeneyra Torres
- Modelado de hardware para sensado y procesado de imágenes en OpenCV
Cristina Villegas Pachón
- Convertidores DC/DC con Capacidades en Conmutación para Recolección de Energía Solar en Tecnologías CMOS Estándar
Esteban Ferro Santiago
17 Julio 2015
♦ Premio Extraordinario de Doctorado
Alberto Rodríguez Pérez, estudiante de doctorado en el Instituto de Microelectrónica de Sevilla y la Universidad de Sevilla, ha recibido el Premio Extraordinario de Doctorado del curso 2012-2013 por la tesis Diseño de sensores implantables para la adquisición de señales neurocorticales.
La Secretaría Gral. Adjunta de Recursos Humanos del CSIC, en colaboración con el Instituto de Microelectrónica de Sevilla, organiza este curso a celebrar en las instalaciones del IMSE los días 19 a 23 de octubre. Dirigido al personal que preste sus servicios en los centros e institutos del CSIC.
Periodo de admisión de solicitudes: Hasta el 29/05/2015

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Oferta de servicios basados en el sistema automático de test ATE Agilent 93000

International Conference on Distributed Smart Cameras
September 8-11, 2015
Seville, Spain


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Últimas publicaciones
Automatic DR and spatial sampling rate adaptation for secure and privacy-aware ROI tracking based on focal-plane image processing  »
Embedded camera systems for the consumer mobile and wearable application market need to operate in a tight power budget. They need to cope with a vast range of illumination conditions, and at the same time, they need to incorporate enough intelligence to implement security and privacy-protection directives. The incorporation of image signal processing at the focal-plane can help reducing the necessary resources to implement tasks like DR adaptation and privacy-aware ROI tracking. In this paper we present a vision sensor that is able to perform single-exposure HDR imaging and ROI obfuscation on-chip, with the help of a reduced set of focal-plane processing elements.

Conference Paper - International Image Sensor Workshop IISW 2015
R. Carmona-Galán, J. Fernández-Berni and Á. Rodríguez-Vázquez
Hardware/Software co-design of video processing applications on a reconfigurable platform  »
The use of a reconfigurable platform, based on the Zynq-7000 Xilinx family, for hardware/software co-design of video processing applications is described in this work. The computing capability of ARM processors included in the device allows performing I/O and processing task by using conventional software libraries. On the other hand, the possibility to accelerate certain tasks through specific hardware implementation on the available programmable logic makes it easier to compare different design alternatives. The advantages of the proposed platform are demonstrated by using different design flows to implement some spatial filters usually required in video processing systems.

Conference Paper - IEEE International Conference on Industrial Technology ICIT 2015
J. Cerezuela-Mora, E. Calvo-Gallego and S. Sánchez-Solano
ConvNets Experiments on SpiNNaker  »
The SpiNNaker Hardware platform allows emulating generic neural network topologies, where each neuron-to-neuron connection is defined by an independent synaptic weight. Consequently, weight storage requires an important amount of memory in the case of generic neural network topologies. This is solved in SpiNNaker by encapsulating with each SpiNNaker chip (which includes 18 ARM cores) a 128MB DRAM chip within the same package. However, ConvNets (Convolutional Neural Network) posses "weight sharing" property, so that many neuron-to-neuron connections share the same weight value. Therefore, a very reduced amount of memory is required to define all synaptic weights, which can be stored on local SRAM DTCM (data-tightly-coupled-memory) at each ARM core. This way, DRAM can be used extensively to store traffic data for off-line analyses. We show an implementation of a 5-layer ConvNet for symbol recognition. Symbols are obtained with a DVS camera. Neurons in the ConvNet operate in an event-driven fashion, and synapses operate instantly. With this approach it was possible to allocate up to 2048 neurons per ARM core, or equivalently 32k neurons per SpiNNaker chip.

Conference Paper - IEEE International Symposium on Circuits and Systems ISCAS 2015
T. Serrano-Gotarredona, B. Linares-Barranco, F. Galluppi, L. Plana and S. Furber
DPA Vulnerability Analysis on Trivium Stream Cipher using an Optimized Power Model  »
In this paper, a Differential Power Analysis (DPA) vulnerability analysis on Trivium stream cipher is presented. Compared to the two previously presented DPA attacks on Trivium, we retrieve the whole key without making any hypothesis during the attack. An optimized power model is proposed allowing the power trace acquisition without making any algorithmic noise removement thus simplifying the attack strategy considerably. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our attack is successful for random keys, saving in computer resources and time respecting to previously reported attacks. The attack is independent on technology used for the implementation of Trivium and can be used to measure the security of novel Trivium implementations.

Conference Paper - IEEE International Symposium on Circuits and Systems ISCAS 2015
E. Tena-Sánchez and A.J. Acosta
Combining Adaptive Alternate Test and Multi-Site  »
Testing analog, mixed-signal and RF circuits represents one of the main cost components for complex SoCs. Multisite Testing is widely accepted as a straightforward technique to reduce the effective test time. This paper shows that an adaptive Alternate Test approach can be compatible with a multisite strategy. The proposed solution consists in ordering offline the signatures acquisition sequence and training incremental regression models for each new feature. These models can be used to diagnose the circuit as good, provided that the estimate of the performance is larger than the specification plus a guard-band related to the model error. If all the sites are diagnosed as good, the test program can be halted before completion. This decision is taken on-line and makes this scheme adaptive. We provide an analytical study of the expected test time reduction and of the test escape penalty that is incurred. Results obtained from post-layout MonteCarlo simulations of an LNA demonstrate the validity of the approach and show that significant test time improvements can be obtained, even for large number of sites, whenever the manufacturing yield is sufficiently high.

Conference Paper - Design, Automation and Test in Europe DATE 2015
G. Leger
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