Consejo Superior de Investigaciones Científicas · Centro Nacional de Microelectrónica
La conferencia será impartida por la profesora Mihaela van der Schaar, Distinguished Lecturer of the IEEE Communications Society, titulada:
Maximizing the Quality of Experience: Taking Care of Tomorrow
que tendrá lugar el próximo 25 de abril a las 10 de la mañana en el Instituto de Microelectrónica de Sevilla ( C/ Américo Vespuccio s/n esquina Leonardo da Vinci, Isla de la Cartuja, Sevilla).
♦ Defensa de Tesis Doctoral
Contribuciones a la implementación hardware de algoritmos de reconocimiento biométrico basados en huellas dactilares.
M. Rosario Arjona López
31 Enero 2014
El investigador del IMSE-CNM y profesor de la Universidad de Sevilla José M. de la Rosa ha recibido el premio al mejor editor asociado de la revista 'IEEE Transactions on Circuits and Systems-I: Regular Papers' en 2012-2013.
♦ Defensa de Tesis Doctoral
Análisis y Diseño de VCOs para Aplicaciones de Radio-Frecuencia en Tecnologías CMOS.
Ricardo Doldán Lorenzo
17 Enero 2014
Imágenes de la jornada de puertas abiertas que el pasado 23 de diciembre se celebró en el Instituto de Microelectrónica de Sevilla.
Trabajos presentados y fallo del jurado.
El IMSE-CNM en Digital.CSIC

Jornada puertas abiertas
Jornada de Puertas Abiertas en el IMSE-CNM
Últimas publicaciones
Análisis y Diseño de VCOs para Aplicaciones de Radio-Frecuencia en Tecnologías CMOS  »
Abstract not available

Thesis - Date of defense: 17/01/2014

R. Doldán-Lorenzo
Mixed-signal energy feature extractor of EEG frequency bands  »
This paper proposes a SAR-based circuit suitable to obtain the amount of signal energy contained in EEG frequency bands. It uses a reconfigurable topology which, in a first stage, acts as a conventional data converter for the incoming neural signal and, in a second stage, performs the squaring operation needed for energy extraction. A simple digital circuit keeps track of the most recent outputs from the squarer and provides the accumulated value of the input signal energy. The system has been simulated in an XFAB 0.18μm technology showing correct measurement of the energy.

Conference Paper - IEEE Latin American Symposium on Circuits and Systems LASCAS 2014

M. Carrasco-Robles and M. Delgado-Restituto
Smart imaging for power-efficient extraction of Viola-Jones local descriptors  »
In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors constitute inputs for trained classifiers which in turn enable diferent high-level vision tasks. While local descriptors certainly alleviate the computation load of subsequent processing stages by preventing them from handling raw images, they still have to deal with individual pixels. Feature vector extraction can thus become a major limitation for conventional embedded vision hardware. In this paper, we present a power-eficicient sensing-processing array conceived to provide the computation of integral images at diferent scales. These images are intermediate representations that speed up feature extraction. In particular, the mixed-signal array operation is tailored for extraction of Haar-like features. These features feed the cascade of classifiers at the core of the Viola-Jones framework. The processing lattice has been designed for the standard UMC 0.18μm 1P6M CMOS process. In addition to integral image computation, the array can be reprogrammed to deliver other early vision tasks: concurrent rectangular area sum, block-wise HDR imaging, Gaussian pyramids and image pre-warping for subsequent reduced kernel filtering.

Conference Paper - IS&T/SPIE Electronic Imaging 2014

J. Fernández-Berni, R. Carmona-Galán, R. del Río, J.A. Leñero-Bardallo, M. Suárez-Cambre and A. Rodríguez-Vázquez
Sigma-Delta Testability for Pipeline A/D Converters  »
Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixedsignal blocks, particularly if digital correction and calibration is considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplification as integrators with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that do not require any extra pin. In addition, digital test techniques developed for ΣΔ modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18μm CMOS process is used as a case of study for the introduction of the DfT modifications.

Conference Paper - Design Automation and Test in Europe DATE 2014

A. Gines and G. Leger
Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits  »
Emerging hierarchical design methodologies based on the use of Pareto-optimal fronts (PoFs) are promising candidates to reduce the bottleneck in the design of analog circuits. However, little work has been reported about how to transmit the information provided by the PoFs of low hierarchical level blocks through the hierarchy to compose the performance models of higher-level blocks. This composition actually poses several problems such as the dependence of the PoF performances on the surrounding circuitry and the complexity of dealing with multi-dimensional PoFs in order to explore more efficiently the design space. To deal with these problems, this paper proposes new mechanisms to represent and select candidate solutions from multi-dimensional PoFs that are transformed to the changing operating conditions enforced by the surrounding circuitry. These mechanisms are demonstrated with the generation of the performance model of an active filter by composing previously generated PoFs of operational amplifiers.

Conference Paper - Design Automation and Test in Europe DATE 2014

M. Velasco-Jiménez, R. Castro-López, E. Roca and F.V. Fernández
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