Consejo Superior de Investigaciones Científicas · Centro Nacional de Microelectrónica
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Visita a las instalaciones del Instituto de Microelectrónica de Sevilla. El IMSE participa en la Semana de la Ciencia 2014 con la organización de unas jornadas de puertas abiertas dirigidas al público general y estudiantes.
13, 14, 19 y 20 Noviembre 2014
♦ Seminario IMSE-Forum
Fiabilidad y variabilidad dependiente del tiempo en dispositivos CMOS nanométricos.
Dr. Javier Martín, Profesor de la Universidad Autónoma de Barcelona.
23 Octubre 2014
Participación del Instituto de Microelectrónica de Sevilla en la Noche de los Investigadores.
26 Septiembre 2014
♦ Defensa de Tesis Doctoral
Diseño e implementación de sistemas empotrados de detección de caras.
Laurentiu Acasandrei
23 Septiembre 2014
Nuestro compañero Miguel Angel Prada, Ingeniero de Telecomunicación por la US, ha sido galardonado con el premio al mejor modelo de negocio basado en un proyecto fin de máster, también ganador de uno de los proyectos que se desarrollarán en el primer centro de emprendimiento de Andalucía Open Future y premiado en el IX Concurso de Iniciativas Empresariales de la Universidad de Sevilla.
16 Septiembre 2014

El IMSE en la Semana de la Ciencia

75 aniversario del Consejo Superior de Investigaciones Científicas (CSIC)

Oferta de servicios basados en el sistema automático de test ATE Agilent 93000

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Últimas publicaciones
Maximizing Lyapunov Exponents in a Chaotic Oscillator by Applying Differential Evolution  »
This paper shows the application of the heuristic Differential Evolution (DE) algorithm to maximize the positive Lyapunov exponent in a third-order multi-scroll chaotic oscillator. The case of study is the saturated nonlinear function series-based chaotic oscillator. The positive Lyapunov exponent is computed for a 4-scrolls chaotic oscillator by varying the coefficients of the dynamical system (a, b, c, d(1)), in the range [0.001..1.000]. The experiments are performed and compared executing DE and a simple Genetic algorithm. The results show that DE algorithm is quite suitable to maximize the positive Lyapunov exponent of truncated coefficients over the continuous parameter spaces, because statistical studies show a small standard deviation. The comparison of the phase space diagrams of non-optimized and optimized chaotic oscillators show that for a low value of the positive Lyapunov exponent the attractor is well defined, while for its maximum value the attractor is not well appreciated, but the higher value of the exponent increases the unpredictability grade of the chaotic system.

Journal Paper - International Journal of Nonlinear Sciences and Numerical Simulation, vol. 15, no. 1, pp. 11-17, 2014
DOI: 10.1515/ijnsns-2011-0014   » doi
ISSN: 1565-1339
V.H. Carbajal-Gomez, E. Tlelo-Cuautle, F.V. Fernandez, L.G. de la Fraga and C. Sanchez-Lopez
MOST Moderate-Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs  »
In this paper, the MOS transistor (MOST) moderate- inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto-optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684μW, an NF of 4.36dB, a power gain of 9.7dB, and a third-order intermodulation intercept point of -4dBm with load and source resistances of 50Ω

Journal Paper - IEEE Transactions on Microwave Theory and Techniques, vol. 62, no. 3, pp. 556-566, 2014
DOI: 10.1109/TMTT.2014.2303476   » doi
ISSN: 0018-9480
R. Fiorelli, F. Silveira and E. Peralias
Detecting single-electron events in TEM using low-cost electronics and a silicon strip sensor  »
There is great interest in developing novel position-sensitive direct detectors for transmission electron microscopy (TEM) that do not rely in the conversion of electrons into photons. Direct imaging improves contrast and efficiency and allows the operation of the microscope at lower energies and at lower doses without loss in resolution, which is especially important for studying soft materials and biological samples.We investigate the feasibility of employing a silicon strip detector as an imaging detector for TEM. This device, routinely used in high-energy particle physics, can detect small variations in electric current associated with the impact of a single charged particle. The main advantages of using this type of sensor for direct imaging in TEM are its intrinsic radiation hardness and large detection area. Here, we detail design, simulation, fabrication and tests in a TEM of the front-end electronics developed using low-cost discrete components and discuss the limitations and applications of this technology for TEM.

Journal Paper - Microscopy, vol. 63, no. 2, pp. 119-130, 2014
DOI: 10.1093/jmicro/dft051   » doi
ISSN: 0022-0744
L.C. Gontard, G. Moldovan, R. Carmona-Galán, C. Lin and A.I. Kirkland
Focal-Plane Sensing-Processing: A Power-Efficient Approach for the Implementation of Privacy-Aware Networked Visual Sensors  »
The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image sensors pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. Power consumption also constitutes a crucial aspect. Images contain a massive amount of data to be processed under strict timing requirements, demanding high-performance vision systems. In this paper, we describe a hardware-based strategy to concurrently address these two key issues. By conveying processing capabilities to the focal plane in addition to sensing, we can implement privacy protection measures just at the point where sensitive data are generated. Furthermore, such measures can be tailored for efficiently reducing the computational load of subsequent processing stages. As a proof of concept, a full-custom QVGA vision sensor chip is presented. It incorporates a mixed-signal focal-plane sensing-processing array providing programmable pixelation of multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise dynamic range adaptation, integral image computation and multi-resolution filtering. The proposed circuitry is also suitable to build a granular space, becoming the raw material for subsequent feature extraction and recognition of categorized objects.

Journal Paper - Sensors, vol. 14, no. 8, pp. 15203-15226, 2014
DOI: 10.3390/s140815203   » doi
ISSN: 1424-8220
J. Fernandez-Berni, R. Carmona-Galan, R. del Rio, R. Kleihorst, W. Philips and A. Rodriguez-Vazquez
Design and Implementation of Embedded Face Detection Systems  »
In recent years a new field has emerged: Embedded Vision. This designation refers to machines that understand their environment through visual means. Embedded Vision is the merging of two fields: embedded systems and computer vision. By their definition an embedded system is any microprocessor-based system that isn't a general-purpose computer. The primary goal of the entities (research institutes or companies) involved with Embedded Vision is to incorporate computer vision capabilities (i.e. algorithms) into low-cost, energy-efficient embedded system. All the work presented in this Thesis fits perfectly to the Embedded Vision field. Two important object detection algorithm, i.e. Viola-Jones and Local Binary Patterns, were ported to a generic embedded system, had their performance bottlenecks analyzed and software and algorithmic optimization solutions were proposed. To make the detection embedded systems faster and more energy efficient, hardware accelerators were designed for the Viola-Jones and Local Binary Patterns algorithms. A Software-Hardware co-design methodology is proposed, that guides the designer during the complex process of embedded algorithm porting, performance analysis, bottlenecks identification, software and hardware partitioning of the embedded system. For the image processing algorithms that need a large bandwidth, the critical importance of the communication architecture is acknowledged and for the AMBA buses (APB, AHB, AXI, AXIStream) master and slaves interfaces were designed. Targeting very lower applications the Viola-Jones hardware accelerator IP was implemented in ASIC. Due to technological incompatibilities, pin and area constraints, several important units of the IP needed redesign. As a result of the redesign process three arithmetical circuit generators (a custom signed/unsigned combinational multiplier, a Nonrestoring pipeline square root and RADIX 4 sequential square root) were implemented. All contributions are available as a open source embedded vision library for object detection.

Thesis - Date of defense: 23/09/2014

L. Acasandrei
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