Publications related to the project
International Journals:
MAIN:
1- R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, L. Camuñas-Mesa, R. Berner, M. Rivas, T. Delbrück, S. C. Liu, R. Douglas, P. Häfliger, G. Jiménez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, B. Linares-Barranco, CAVIAR: A 45k-Neuron, 5M-Synapse, 12G-connects/sec AER Hardware Sensory-Processing-Learning-Actuating System for High Speed Visual Object Recognition and Tracking, IEEE Trans. on Neural Networks, vol. 20, No. 9, pp. 1417-1438, September 2009.
2- R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jimenez, C. Serrano-Gotarredona, J. A. Pérez-Carrasco, A. Linares-Barranco, G. Jiménez-Moreno, A. Civit-Ballcels, and B. Linares-Barranco, On Real-Time AER 2D Convolutions Hardware for Neuromorphic Spike Based Cortical Processing, IEEE Trans. on Neural Networks, vol. 19, No. 7, pp. 1196-1219. July 2008. (PDF)
3- M. Oster, Y. Wang, R. Douglas, and S.-C. Liu, Quantification of a spike-based winner-take-all VLSI network, IEEE Trans. Circ. Syst. Part-1, vol. 55, No. 10, pp. 3160-3169, Nov. 2008. (PDF)
4- P. Lichtsteiner, C. Posch, and T. Delbruck, A 128x128 120dB 15us latency asynchronous temporal contrast vision sensor, IEEE J. Solid State Circuits, 43(2) 566-576, 2007. (PDF)
5- A. Linares-Barranco, M. Oster, D. Cascado, G. Jimenez, A. Civit, B. Linares-Barranco, Inter-Spike-Intervals Analysis of AER Poisson like Generator Hardware, Neurocomputing, 70, pp. 2692-2700, May 2007. (PDF)
6- P. Häfliger, Adaptive WTA with an analog VLSI neuromorphic learning chip, IEEE Tran. Neural Networks, vol. 18, no. 2, pp. 551-572, 2007. (PDF)
7- R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, A Neuromorphic Cortical Layer Microchip for Spike Based Event Processing Vision Systems, IEEE Trans. on Circuits and Systems, Part-I. Vol. 53, No. 12, pp. 2548-2566, December 2006. (PDF)
8- A. Linares-Barranco, G. Jimenez-Moreno, B. Linares-Barranco and A. Civit-Ballcels, On Algorithmic Rate-Coded AER Generation, IEEE Transactions on Neural Networks, vol. 17, No. 3, pp. 771-788, May 2006. (PDF)
RELATED:
1- G. Vicente-Sanchez, J. Velarde-Ramirez, T. Serrano-Gotarredona, and B. Linares-Barranco,A Weak-to-Strong Mismatch Model for Analog Circuit Design, Int. Journal of Analog Integrated Circuits and Signal Processing, accepted for publication.
2- J. A. Leñero-Bardallo, T. Serrano-Gotarredona, and B. Linares-Barranco, A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells. Application to 5-bit 20nA DACs, IEEE Trans. Circuits and Systems, Part-II: Brief Papers, vol. 55, No. 6, pp. 522-526, June 2008. 2008. (PDF)
3- R. Serrano-Gotarredona, L. Camuñas-Mesa, T. Serrano-Gotarredona, J. A. Leñero-Bardallo, and B. Linares-Barranco, The Stochastic I-Pot: A Circuit Block for Programming Bias Currents, IEEE Trans. Circuits and Systems, Part-II: Brief Papers, vol. 54, No. 9, pp. 760-764, September 2007. (PDF)
4- B. Linares-Barranco and T. Serrano-Gotarredo na, On an Efficient CAD Implementation o f the Distance Term in Pelgrom's Mismatch Model IEEE Trans. on CAD, vol. 26, No. 8, pp. 1534-1538, August 2007.(PDF )
5- T. Delbruck, A. van Schaik (2005). Bias current generators with wide dynamic range. Analog Integrated Circuits and Signal Processing, vol . 43, pp. 247-268. (PDF)
6- Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, Compact Low Power Calibration Mini-DACs for Neural Massive Arrays with Programmable Weights, IEEE Trans. Neural Networks, September 2003. (PDF)
7- j. cOstas-Santos, T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco, A Spatial Contrast Retina with On-chip Calibration for Neuromorphic Spike-Based AER Vision Systems, IEEE Trans. Circuits and Systems, Part-I: Regular Papers, vol. 54, No. 7, pp. 1444-1458, July 2007. (PDF)
8-Linares-Barranco and T. Serrano-Gotarredona, On the Design and Characterization of Femtoampere Current-Mode Circuits, IEEE Journal of Solid-State Circuits, vol. 38, No. 8, pp. 1353-1363, August 2003. (PDF)
9- P. Häfliger and E. Jorgensen Aasebo, A rank encoder: Adaptive analog to digital conversion exploiting time domain spike signal processing, Int. Journal on Analog Integrated Circuits and Signal Processing, volume 40, no. 1, p. 39-52. (PDF)
10- H. K. O. Berge and P. Häfliger, A gate leakage feedback element in an adaptive amplifier application, IEEE Trans. on Circuits and Systems, Part II, vol. 55 (2), pp. 101-105, 2008. (PDF)
International Conferences:
1- B. Linares-Barranco and T. Serrano-Gotarredona, CMOS Mismatch Model valid from weak to strong inversion, Proc. 2003 European Solid-State Circ. Conf., pp. 2003. (PDF 2.98M, 4 pages)
2- B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona, and J. Velarde, A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion, IEEE Int. Symp. Circ. and Syst., ISCAS-2004.
3- B. Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, A New Charge-Packet Driven Mismatch-Calibrated Integrate-and-Fire Neuron for Processing Positive and Negative Signals in AER based Systems, IEEE Int. Symp. Circ. and Syst., ISCAS-2004.
4- A. Linares-Barranco, G. Jiménez-Moreno, A. Civit-Ballcels, and B. Linares- Barranco, On Synthetic AER Generation, IEEE Int. Symp. Circ. and Syst., ISCAS-2004.
5- B. Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, On Leakage Current Temperature Characterization using Sub-Pico-Ampere Circuit Techniques, IEEE Int. Symp. Circ. and Syst., ISCAS-2004.
6- B. Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, On Mismatch Properties of MOS and Resistors Calibrated Ladder Structures, IEEE Int. Symp. Circ. and Syst., ISCAS-2004.
8- Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit, B. Linares-Barranco. Synthetic Generation of Events for Address-Event-Representation Communications, PATMOS Proceedings. ISBN 3-540-44143-3 pp. 371-379. September 2002. Seville, Spain1
9- Alejandro Linares-Barranco,Gabriel Jiménez,A.Civit,J.L.Sevillano,R.Paz. Software Generation of Address-Event-Representation for Interchip Images Communications, IECON Proceedings ISBN 0-7803-7475-4, November 2002. Seville, Spain
10- A. Linares-Barranco, R. Senhadji-Navarro, I. García-Vargas, F. Gómez- Rodríguez, G. Jimenez and A. Civit. Synthetic Generation of Address-Event for Real-Time Image Processing. Proceedings of the IEEE Emerging Technologies and Factory Automation. ISBN 0-78037937-3, pp 462-467. Sep 2003. Lisbon, Portugal
11- F. Gómez-Rodríguez, A. Linares-Barranco, R. Senhadji-Navarro, I.García- Vargas,L. Miro-Amarante, G.Jiménez-Moreno. Sistemas Pulsantes para el Tratamiento de Imágenes en Tiempo Real. Procesado Mixto Analógico-Digital. XIV Jornadas de Paralelismo. ISBN 84-89315-34-5. pp. 475-479. Sep 2003. Leganés, Madrid, SPAIN
12- S-C. Liu and R. Douglas, Spike synchronization in a
network of silicon integrate-and-fire neurons,
Spike synchronization in a network of silicon
integrate-and-fire neurons, IEEE Int. Symp. Circ. and Syst.,
ISCAS-2004.
13- M. Azadmehr, J. P. Abrahamsen and P. Häfliger, A Foveated AER Imager Chip, Conference paper to appear at ISCAS 2005 in Kobe) abstract.
14- J. P. Abrahamsen, P. Häfliger and T. S. Lande, A Time Domain Winner-Take-All network of Integrate-and-Fire Neurons, Conference paper ISCAS 2004 in Vancouver, abstract, PDF
15- H. Kolle Riis and P. Häfliger, Spike Based Learning with Weak Multi-Level Static Memory, Conference paper ISCAS 2004 in Vancouver, abstract, PDF
16- P. Häfliger, On using the time domain for analog signal representation in electronic circuits, Newsletter: The Neuromorphic Engineer, Vol. 1, No. 1, 2004
17- P. Häfliger and H. Kolle Riis, A Multi-Level Static Memory Cell Conference paper ISCAS 2003 in Bangkok abstract, PDF
18- H. Kolle Riis and P. Häfliger, An Asynchronous 4-to-4 AER Mapper, Conference paper to appear at IWANN 2005 in Barcelona, abstract.
19- Liu, S.-C. and Oster, M., Feature competition in a spike-based winner-take-all VLSI network, Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, ISCAS06, Greece, May 2006.
20- M. Oster, S. Liu, Spiking Inputs to a Winner-take-all Network, NIPS 2005.
21- R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz- Vicente, F. Gómez-Rodríguez, H. Kolle Riis, T. Delbrück, S. C. Liu, S. Zahnd, A. M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez, B. Linares-Barranco, AER Building Blocks for Multi-Layers Multi-Chips Neuromorphic Vision Systems, NIPS2005. (presented poster[1843KB]) (PDF [902K])
22- Francisco Gomez Rodriguez, Rafael Paz Vicente, et al Aer Tools for Communications and Debugging, ISCAS 2006, May 2006.
23- Alejandro Linares-Barranco, Matthias Oster, Daniel Cascado, et al, Poisson Aer Generator: Inter-Spike-Intervals Analysis, ISCAS 2006, May 2006.
24- Rafael Serrano, Teresa Serrano, Antonio José Acosta, et al An Arbitrary Kernel Convolution Aer- Transceiver, ISCAS 2006, May 2006.
25- Rafael Paz-Vicente, Alejandro Linares-Barranco, et al PCI-Aer Interface for Neuro-Inspired Spiking Systems, ISCAS 2006, May 2006.
26- Rafael Serrano, Bernabe Linares-Barranco, et al, High-Speed Image Processing with Aer-Based Components, ISCAS 2006, May 2006.
27- Tobi Delbruck, Patrick Lichtsteiner, Fully Programmable Bias Current Generator with 24 Bit Resolution Pe... ISCAS 2006, May 2006.
28- Oster, M. and Whatley, A. M. and Liu,
S.-C. and Douglas, R. J., A Hardware/Software Framework for
Real-time Spiking Systems, Artificial Neural Networks:
Biological Inspirations ICANN 2005: 15th International Conference,
Warsaw, Poland, September 11-15, 2005. Proceedings, Part I, 3696:
161-166, Sep, Wlodzislaw Duch, Janusz Kacprzyk, Erkki Oja, et al.
(Eds.), Springer-Verlag GmbH, 2005. (PDF
[157KB])
29- A
100dB dynamic range high-speed dual-line optical transient sensor with
asynchronous readout, Lichtsteiner, P.; Delbruck, T.;
Posch, C.; Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006
IEEE International Symposium on, 21-24 May 2006 Page(s):1659 - 1662,
(see retina page)
30- Fully Programmable Bias Current Generator with 24 Bit Resolution Per Bias, Delbruck, T.; Lichtsteiner, P.; Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006 Page(s):2849 - 2852. (see bias generator pages).
31- Modeling Orientation Selectivity Using a Neuromorphic Multi-Chip System, Chicca, E.; Lichtsteiner, P.; Delbruck, T.; Indiveri, G.; Douglas, R.J.; Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 21-24 May 2006 Page(s):1235 - 1238
32- P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128×128 120dB 30mW Asynchronous Vision Sensor that Responds to Relative Intensity Change," presented at 2006 International Solid State Circuits Conference (ISSCC 2006), San Francisco, Feb. 2006, (paper 27.9). Published in 2006 IEEE ISSCC Digest of Technical Papers, p 508-509. (see retina page)
33- P. Lichtsteiner and T. Delbruck, "A 64x64 AER Logarithmic temporal derivative silicon retina," in IEEE PRIME 2005, EPFL, Lausanne, Switzerland, 2005. Published in Research in Microelectronics and Electronics, 2005 PhD, vol. 2, pp 202-205 (see retina page)
34- P. Lichtsteiner and T. Delbruck, "64x64 Event-Driven Logarithmic Temporal Derivative Silicon Retina," in 2005 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Nagano, Japan, 2005, pp. 157-160. (see retina page)
35- P. Lichtsteiner, J. Kramer, T. Delbruck, Improved ON/OFF temporally differentiating address-event imager, 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2004) Tel Aviv, Israel, pp. 211-214 (see retina page)
36- T. Delbruck, D. Oberhof, Self biased low power adaptive photoreceptor, 2004 International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, Canada, May 23-25 2004 pp. IV-844-847 (see photoreceptor pages)
37- T. Delbruck, A. van Schaik, Bias current generators with wide dynamic range,
2004 International Symposium on Circuits and Systems (ISCAS 2004),
Vancouver, Canada, May 23-25 2004 pp. I-337-340 (see bias
generator pages).
38- Alejandro Linares-Barranco1, Bernabé Linares-Barranco2, Gabriel Jiménez-Moreno1, Antón Civit-Balcells, "AER SYNTHETIC GENERATION IN HARDWARE FOR BIO-INSPIRED SPIKING SYSTEMS," PROCEEDINGS OF SPIE. MICROTECHNOLOGIES FOR THE NEW MILLENNIUM 2005. BIOENGINEERED AND BIOINSPIRED SYSTEMS II. Volume 5839. pp: 103-110. SPIE 2005.
39- R. Paz-Vicente, A. Linares-Barranco, D. Cascado, S. Vicente, G. Jimenez, A. Civit, "TIME-RECOVERING PCI-AER INTERFACE FOR BIO-INSPIRED SPIKING SYSTEMS," PROCEEDINGS OF SPIE. MICROTECHNOLOGIES FOR THE NEW MILLENNIUM 2005. BIOENGINEERED AND BIOINSPIRED SYSTEMS II. Volume 5839. pp: 111-118. SPIE 2005.
40- Rafael Serrano Gotarredona, Bernabé
Linares Barranco y Teresa Serrano Gotarredona, "On event generators for
Address-Event Representation transmitters," Microtechnologies for the
new Millenium (SPIE 2005), Seville, May 2005.
41- A. Linares-Barranco1, M. Oster2, D.
Cascado1, G. Jiménez1, A. Civit1, B. Linares-Barranco,
"INTER-SPIKE-INTERVALS ANALYSIS OF POISSON LIKE HARDWARE SYNTHETIC AER
GENERATION," Lecture Note on Computer Science: Volume: 3512, pp
479-485, IWANN 2005.
42- F. Gomez-Rodriguez, R. Paz , L. Miro, A.
Linares-Barraco, G. Jimenez, A. Civit, "TWO HARDWARE IMPLEMENTATIONS OF
THE EXHAUSTIVE SYNTHETIC AER GENERATION METHOD," Lecture Note on
Computer Science: Volume: 3512, pp 534-540, IWANN 2005.
43- R. Paz, F. Gomez-Rodriguez, M. A.
Rodriguez, A. Linares-Barranco, G. Jimenez, A. Civit, "Test
Infrastructure for Address-Event-Representation Communications,"
Lecture Note on Computer Science: Volume: 3512, pp 518-526, IWANN 2005.
44- M.Rivas, F.Gomez-Rodriguez, R.Paz,
A.Linares-Barranco, S.Vicente and D.Cascado., "Tools for
Address-Event-Representation Communication Systems and Debugging,"
Lecture Note on Computer Science: Volume: 3696. pp: 289-296, ICANN 2005.
45- L. Miró, A. Jiménez, A.
Linares-Barranco, F. Gómez-Rodríguez, R.
Serrano-Gotarredona, G. Jiménez, A. Civit. "Parallel AER to
Serial LVDS for Spiking Systems," ICECS 2006.
46- R. Serrano-Gotarredona, T.
Serrano-Gotarredona, A.J. Acosta-Jimenez, B. Linares-Barranco, L.A.
Camunas-Mesa, "A Bio-inspired Event-Based Real-Time Image Processor,"
Proc. of BioRob 2006, Pisa, February 2006.
47- Rafael Serrano Gotarredona, Bernabé
Linares Barranco, Teresa Serrano Gotarredona, Clara Serrano
Gotarredona, Alejandro Linares Barranco, Gabriel Jiménez Moreno
y Antón Civit Ballcels, "A programmable convolution-chip
prototype for real-time image processing," Proc. of DCIS05 conference,
Lisbon, November 2005.
48- Rafael Serrano Gotarredona, Bernabé
Linares Barranco y Teresa Serrano Gotarredona, "Charge-packet Driven
Mismatch-Calibrated Integrate-and-Fire Neuron for Address-Event
Representation," XIX International Conference on Design of Circuits and
Integrated Systems (DCIS 2004), Bordeux, November 2004.
49- Rafael Serrano Gotarredona, Teresa Serrano
Gotarredona y Bernabé Linares Barranco, "Mismatch Properties of
MOS and Resistor Calibrated Ladder Structures," XIX International
Conference on Design of Circuits and Integrated Systems (DCIS 2004),
Bordeux, November 2004.
Previous Publications that inspired CAVIAR:
1- Teresa Serrano-Gotarredona , Andreas G. Andreou , and Bernabé Linares-Barranco, AER Image Filtering Architecture for Vision Processing Systems, IEEE Trans. Circuits and Systems (Part II): Analog and Digital Signal Processing, vol. 46, No. 9, pp. 1064-1071, September 1999. (PDF [287K], 8 pages)
2- J. Kramer, An Integrated Optical Transient Sensor, IEEE Trans. on Circ. and Syst. (Part II): Analog and Digital Signal Processing, vol. 49, No. 9, pp. 612-628, September 2002.
3- T. Delbrück and C.A.Mead. (1995). Analog VLSI phototransduction by continuous-time, adaptive, logarithmic photoreceptor circuit, in Vision Chips: Implementing vision algorithms with analog VLSI circuits, C. Koch and H. Li editors, IEEE Computer Society Press, 1995, pp. 139-161 .
Diploma Projects:
1- 2006, Raphael Berner, High speed USB2.0 AER interfaces.. See also INI-AE-Biasgen page page
Semester projects:
1- 2006, Janick Cardinale, Tracking objects and wing beat analysis methods of a fruit fly with the event-based silicon retina
2- 2006, Peter Hess, Event-based stereo disparity computation.
Links:
1- Tobi's CAVIAR page: http://caviar.ini.unizh.ch
2- Tobi/Patrick's retina page: http://siliconretina.ini.unizh.ch
3- Tobi's USB2AER page: http://www.ini.unizh.ch/~tobi/caviar/INI-AE-Biasgen/
4- Tobi's SimpleMonitorUSBXPress page: http://www.ini.unizh.ch/~tobi/caviar/SimpleMonitorUSBXPress/
5- Tobi's biasgen pages: http://www.ini.unizh.ch/~tobi/biasgen
Other Results:
1- Bias
Generator Compiler
2- CMOS
Transistor Characterization
3- Test board for AER chips (according to consortium
standards pinout, PGA-100)
4- Consortium
Standards Document (in progress)
