Projects. PULPOSS

Processing for Ultra Low POwer using Steep Slope devices: circuits and arquitectures

Different applications with a great social and economic impact (loT, wearables, implantable devices, WSNs) demand circuits with very low power consumption and efficient in terms of energy. In this context, the field-effect transistor has severe limitations associated with its SS, that cannot be reduced below 60mVldec, which prevents it from reducing its polarization voltage, without significantly degrading its performance in terms of speed or excessively increasing its leakage curren!. Currently important efforts are devoted to the development of "steep slope" devices that do not exhibit this limitation. This project addresses the design of circuits and architectures implemented with these transistors in order to contribute to the development of such applications. The work developed in NACLUDE (TEC2013-40670-P) with tunneling transistors (TFETs) is extended to other steep slope devices, including negative capacitan ce transistors (NCFET, FeFET), transistors incorporating materials that exhibi! phase !ransitions (HyperFET, PC-FET) or "super steep slope" devices tha! combine these physical phenomena with TFETs (PC-TFET, NC-TFET) to improve their performance.
Although there is consensus in the scientific community about !he potential of these devices to implement circuits more efficient in terms of power consumption and energy than MaS and FinFET transistors, the simple replacement of conventional transistors by steep slope devices does not allow to obtain the maximum benefit of its use. It is necessary to adapt the topologies andlor architectures to the distinctive characteristics of ea eh device. The general objective of this project is the development of logical architectures and circuits with steep slope devices to optimize their performance in terms of power, energy or power-speed trade-offs in different application scenarios. The specific objectives that we formulate are: 1) To develop, analyze, validate and evaluate appropriate topologies for basic logical blocks; 2) to Develop, analyze, validate and evaluate appropriate logic architectures; 3) To apply design techniques for low power; 4) To explore alternative computing paradigms to CMOS logic; 5) To maintain a library of models of steep-slope devices updated with the advances and proposals that are taking place.

Principal Investigator

María J. Avedillo de Juan  >

José M. Quintana Toledo  >

Project Details

  • Type: Research project
  • Funding Body: Ministerio de Ciencia e Innovación
  • Reference: TEC2017-87052-P
  • Start date: 2018
  • End date: 30/06/2021
  • Funding: 85.910,00 €