Spanish National Research Council · University of Seville
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Funding for the research activities carried out at IMSE-CNM comes primarily from the participation in competitive tender processes. The research is then conducted out via agreements, projects and contracts with national and international public organizations and private companies and organizations.

Towards Trusted Low-Power Things: Devices, Circuits and Architectures
PI: Francisco V. Fernández Fernández / Rafael Castro López
Type: Research project
Reference: TEC2016-75151-C3-3-R
Funding Body: Ministerio de Economía, Industria y Competitividad
Start date: 30/12/2016
End date: 29/12/2019
Funding: 240.911,00 €
Abstract: To bridge the gap between the physical and digital worlds, any type of product would need to integrate networked electronic components and systems, built on micro/nanotechnologies, in what has been called "Internet of Things" (IoT). To fulfill the IoT vision, many technology enablers are required, with trusted (i.e., reliable and secure) as well as low-power ICs and components, among others, playing a pivotal role. All these enablers must be properly handled with a multidomain approach -covering device, circuit and architectural levels- in a context where technology scaling has slowed down. Thus, at technology level, innovations in materials and device structures will be required and, next to this, low-power robust circuits and alternative architectures will have to be implemented. Consequently, the experience of researchers with complementary expertise must be properly combined under a collaborative framework. Following these guidelines, device reliability engineers (UAB) and analog and digital circuit designers (IMSE and UPC) will work together in this project on the design of low-power, variability-resilient nanoelectronic circuits and systems, by using a multilevel approach and taking into account IoT challenges.
To achieve this general objective, several lines of work will be followed. Since circuit and system design for IoT relies upon a deep knowledge of phenomena at device level, a detailed statistical and multiscale characterization of the variability in advanced CMOS devices will be done in all regimes of operation, for the development of variability-aware compact models. Emerging devices (i.e., memristors and graphene-based devices) will be also considered to evaluate their suitability as building components in alternative circuits and architectures. At circuit and system levels, low-power and variability-resilient design strategies and methodologies will be developed. Variability will be tackled from two perspectives: palliation and exploitation. From a palliative perspective, adequate design methodologies will be created, able to consider and reduce variability across many hierarchical levels in a complex AMS/RF system. Also, the use of Body Bias modulation for variability mitigation in RF and digital circuits in FDSOI technologies will be analyzed. From the exploitation perspective, unreliability aspects in CMOS and memristive devices will be explored for the implementation of cryptographic primitives. Energy-efficient hierarchical design methodologies will be implemented to reduce power consumption in AMS/RF circuits and ultra-low voltage AMS/RF and digital circuits will be designed. Non-conventional strategies for computing systems and non-von Neumann computing architectures will be studied too. Finally, the adoption of emerging technologies for alternative computing architectures (combining memristors and FETs) as well as neuromorphic architectures will be addressed. The innovations in devices, design techniques, extremely low-power and reliable circuits and architectures will enable competitive advantages in numerous IoT applications and markets, supporting the relevance of the proposed research from the societal, industrial and economical points of view. This fact, together with the experience of the proposing partners, foresees publications and technology transfer of the results.

Design techniques of low-cost, low-consumption, flexible and reconfigurable micro-nanoelectronic circuits and systems with application to wireless communications
PI: Francisco V. Fernández Fernández
Type: Research project
Reference: P12-TIC-1481
Funding Body: Junta de Andalucía
Start date: 30/01/2014
End date: 16/02/2019
Funding: 181.492,50 €
Abstract: The rapid development of communications systems has been possible thanks to the relentless advance of the micro / nano-electronic circuits. Although the domain of digital circuits is overwhelming, the fact remains that analog circuits, mixed signal and RF (AMS / RF) play a key role in the interface of digital circuits with the outside world, either to sense signals, act or transmitting signals in a communication channel.

Among other factors, the development of electronic technologies has been made possible thanks to the development of tools and AMS / RF design techniques, although it is true that this development has been far behind their digital counterparts. However, factors linked to technological scaling, demands for greater flexibility and reconfigurability, the greater variability of processes, degradation of the devices during operation, increasing complexity, the demand for higher performance and new business challenges, lie altogether beyond the capabilities of existing design paradigms. In fact, the strategic research agenda of the European Technology Platform on Nanoelectronics, has established the Design Tools and Techniques domain (and among them, those dedicated to AMS / RF circuits) as a critical technological domain to prioritize if we want to achieve the objectives of health, transportation, security, energy and communications in the year 2020.

In this project, we intend to address these challenges through the development of new design techniques, introducing novel techniques of modeling and synthesis of circuits that allow to design circuits beyond the current state of art, as well as new architectures and circuit topologies that facilitate incorporating greater flexibility and reconfigurability, taking next-generation wireless communications as application and demonstration field. To do this, we will deepen in the generation and application of performance fronts (models showing the best compromise between performances), defining a new concept, which we call meta-front. This new concept allows the incorporation of crucial information, beyond just circuit performances, in the design process. Thus, the meta-front includes the variability derived from manufacturing technology, parametric drifts along the life cycle of the circuits, and parasitics associated to the physical implementation, as well as the flexibility and reconfiguration capabilities required for the circuit to adapt to new condition operations. In addition, we will explore flexible architectures and circuit blocks and develop new synthesis strategies that make use of the performance modeling techniques and the information these models provide to achieve the balanced design in terms of energy consumption and cost.

As hardware demonstrator of the project, a flexible receiver will be designed and manufactured. This receiver can be continuously reconfigurable in the range of 800 MHz to 6 GHz, with bandwidths from 100KHz to 100MHz and dynamic ranges of 50dB to 75dB, thus covering the performance specifications of all communication standards in this band (GSM, UMTS, BT, GPS, DVB-H, WLAN, WiMAX, LTE etc.). This design will be done with minimum consumption and minimum cost, and it will be done so the receiver can adapt to different operating conditions. The advantages of the new techniques will be also demonstrated through its application to the design of a multi-standard data converter, a reconfigurable low noise amplifier and a circuit in commercial operation, designed with previously existing techniques and whose characterization experimental data are available.