ODS Objetivo 9
Objetivos de Desarrollo Sostenible. Objetivo 9: 'Industria, Innovación e Infraestructura'

Entrevista al investigador y director del IMSE Bernabé Linares Barranco sobre hacia dónde se dirige la micro y nano electrónica, cómo pueden acceder a ella los países menos desarrollados y qué proyectos nacionales, europeos e internacionales se llevan a cabo en el IMSE para ayudar a lograr el Objetivo de Desarrollo Sostenible 9.


Kick-off SPIRS
Kick-off meeting del proyecto europeo SPIRS

Los días 28 y 29 de Octubre se celebró en la Delegación del CSIC de Andalucía el kick-off meeting del proyecto europeo SPIRS (Secure Platform For ICT Systems Rooted at the Silicon Manufacturing Process).


Defensa de Tesis Doctoral
Defensa de Tesis Doctoral

Study of variability phenomena on CMOS technolologies for its mitigation and exploitation.
Pablo Sarazá Canflanca
12 Noviembre 2021

Ranking Stanford
Cuatro investigadores del IMSE, entre el 2% de los mejores del mundo

La Universidad de Stanford, en California, ha publicado la lista 'Ranking of the World Scientists: World´s Top 2% Scientists', que recoge a profesionales de la investigación cuyos trabajos han sido más citados durante su carrera profesional hasta 2019. En dicha lista aparecen los investigadores del IMSE Bernabé Linares, Ángel Rodríguez, Teresa Serrano y José Manuel de la Rosa.


Libro Visual Inference for IoT Systems
Libro 'Visual Inference for IoT Systems: A Practical Approach'

Publicado el libro 'Visual Inference for IoT Systems: A Practical Approach', de los investigadores del IMSE Delia Velasco-Montero, Jorge Fernández-Berni y Ángel Rodríguez-Vázquez.


Chips, un inventario sin stock
Chips, un inventario sin stock

Entrevista al profesor José Manuel de la Rosa para el programa 'Puerta al Presente' de RNE Radio 5, sobre el desabastecimiento existente en el mercado de semiconductores.



Próximos eventos

13 Dic
Conferencia de Timothée Masquelier

Surrogate gradient learning in spiking neural networks.

13 Diciembre 202113:30h.

Formación en el IMSE

- Doctorado
- Máster
- Grados
- Trabajos Fin de Grado
- Prácticas en Empresa


Publicaciones recientes

Visual Inference for IoT Systems: A Practical Approach
D. Velasco-Montero, J. Fernández-Berni and A. Rodríguez-Vázquez
Book · 145 p, 2022
SPRINGER    ISBN: 978-3-030-90903-1    
resumen      link      

This book presents a systematic approach to the implementation of Internet of Things (IoT) devices achieving visual inference through deep neural networks. Practical aspects are covered, with a focus on providing guidelines to optimally select hardware and software components as well as network architectures according to prescribed application requirements.
The monograph includes a remarkable set of experimental results and functional procedures supporting the theoretical concepts and methodologies introduced. A case study on animal recognition based on smart camera traps is also presented and thoroughly analyzed. In this case study, different system alternatives are explored and a particular realization is completely developed.
Illustrations, numerous plots from simulations and experiments, and supporting information in the form of charts and tables make Visual Inference and IoT Systems: A Practical Approach a clear and detailed guide to the topic. It will be of interest to researchers, industrial practitioners, and graduate students in the fields of computer vision and IoT.

Gate-Level Design Methodology for Side-Channel Resistant Logic Styles using TFETs
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Embedded Systems Letters, first online, 2021
IEEE    ISSN: 1943-0663
resumen      doi      

The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an effective solution to secure applications with power constraints. The paper deals with the optimized design of DPA-resilient hiding-based techniques, using Tunnel Field-Effect Transistors (TFETs). Specifically, proposed TFET implementations of Dual-Precharge-Logic primitives optimizing their computation tree in three different ways, are applied to the design of PRIDE Sbox-4, the most vulnerable block of the PRIDE lightweight cipher. The performance of simulation-based DPA attacks on the proposals have shown spectacular results in security gain (34 out of 48 attacks fail for optimized computation trees in TFET technology) and power reduction (x25), compared to their CMOS-based counterparts in 65nm, which is a significant advance in the development of secure circuits with TFETs.

Experimental FIA Methodology using Clock and Control Signal Modifications under Power Supply and Temperature Variations
F.E. Potestad-Ordóñez, E. Tena-Sánchez, J.M. Mora-Gutierrez, M. Valencia-Barrero and C.J. Jiménez-Fernández
Journal Paper · Sensors, vol. 21, no. 22, article 7596, 2021
MDPI    ISSN: 1424-8220
resumen      doi      

The security of cryptocircuits is determined not only for their mathematical formulation, but for their physical implementation. The so-called fault injection attacks, where an attacker inserts faults during the operation of the cipher to obtain a malfunction to reveal secret information, pose a serious threat for security. These attacks are also used by designers as a vehicle to detect security flaws and then protect the circuits against these kinds of attacks. In this paper, two different attack methodologies are presented based on inserting faults through the clock signal or the control signal. The optimization of the attacks is evaluated under supply voltage and temperature variation, experimentally determining the feasibility through the evaluation of different Trivium versions in 90 nm ASIC technology implementations, also considering different routing alternatives. The results show that it is possible to inject effective faults with both methodologies, improving fault efficiency if the power supply voltage decreases, which requires only half the frequency of the short pulse inserted into the clock signal to obtain a fault. The clock signal modification methodology can be extended to other NLFSR-based cryptocircuits and the control signal-based methodology can be applied to both block and stream ciphers.

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System
N. Perez-Prieto, A. Rodriguez-Vazquez, M. Alvarez-Dolado and M. Delgado-Restituto
Journal Paper · IEEE Transactions on Biomedical Circuits and Systems, first online, 2021
IEEE    ISSN: 1932-4545
resumen      doi      

This paper presents a high dynamic range, lowpower, low-noise mixed-signal front-end for the recording of local field potentials or electroencephalographic signals with invasive neural implants. It features time-multiplexing of 32 channels at the electrode interface for area saving and offers the ability to spatially delta encode signals to take advantage of the large correlations between nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information, thus effectively increasing the dynamic range of the system while avoiding the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro and shows an integrated input-referred noise in the 0.5200 Hz band of 1.4 Vrms for a spot noise of about 85 nV/Hz. The system draws 1.5 W per channel from 1.2 V supply and obtains 71 dB + 26 dB (with artifact compression) dynamic range, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.


Investigación en el CSIC

Qué hacemos en el IMSE

El área de especialización del Instituto es el diseño de circuitos integrados analógicos y de señal mixta en tecnología CMOS, así como su uso en diferentes contextos de aplicación tales como dispositivos biomédicos, comunicaciones inalámbricas, conversión de datos, sensores de visión inteligentes, ciberseguridad, computación neuromórfica y tecnología espacial.

La plantilla del IMSE-CNM está formada por unas cien personas, entre personal científico y de apoyo, que participan en el avance del conocimiento, la generación de diseños de alto nivel científico-técnico y la transferencia de tecnología.


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