Projects. SARATSO

Asynchronous timing self-optimization for SAR-ADC

This project takes upon the achievements of the StatSET project (RTI2018-098513-B-I00). In the frame of that project, the quality of the test vehicle was not a primary requirement since the objective was to validate a Single-Event simulation flow. However, in order to challenge the simulation flow with high-order effects, we designed an analog-to-digital data converter that is in the state-of-the-art for radiation-hardened parts. In this follow-up project, we want to put the focus on this design and bring the ADC closer to industrialization.
The architecture is based on a redundant successive approximation register (SAR-ADC). The redundancy opens the trade-off between resolution and speed because, although it requires some extra comparison cycles, it allows more error budget for settling errors. For an asynchronous implementation, with self-timed successive comparisons, this can be very beneficial.
From an innovation viewpoint, the ASIC has two interesting characteristics: On one hand it implements a self-calibration machine to correct the weights of the feedback DAC that includes a mechanism to account for the comparator offset. This is not trivial in the presence of redundancy. On the other hand, the prototype also implements a tuning mechanism to easily adjust the timing between the successive comparisons. In this follow-up project, we will augment the potential of this tuning mechanism, introducing a low-cost algorithm in the digital section to perform a self-optimization of the asynchronous timing. This will allow the ADC to maximize its performance by adapting to external drifts that may affect the settling properties (aging, temperature, sampling frequency changes, total ionizing dose, etc.). The existing prototype has already shown promising experimental results: a very good low-frequency effective resolution of 11 effective bits over a 2Vpp input range, up to 30MHz of sampling frequency, and over a large temperature range. In addition, the prototype was submitted to a radiation campaign for Single-Event characterization. The radiation-hardening techniques of the ASIC were found efficient, with a Linear Energy Transfer (LET) threshold over for Single-Event Latchup (SEL) and a cross-section of only 0.0138 mm2 for Single-Event Transients (SET) at the output (with a stringent amplitude requirement of only 10 Least-Significant Bits, which correspond to 2.4mV).
In this project, we will extend the electrical characterization to higher frequency input signals and widen the temperature range. We will also test several packaging options to assess the sensitivity of the ASIC to inductive parasitics. In addition, we will complement the SEE radiation data by characterizing the performance drifts associated with the Total Ionizing Dose.

Project PDC2023-145912-I00 funded by MICIU/AEI/10.13039/501100011033 and European Union NextGenerationEU/ PRTR.

Principal Investigator

Gildas Léger  >

Project Details

  • Type: Research project
  • Funding Body: Agencia Estatal de Investigación
  • Reference: PDC2023-145912-I00
  • Start date: 01/01/2024
  • End date: 31/12/2025
  • Funding: 73.955,20 €