Spanish National Research Council · University of Seville
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IMSE-CNM in Digital.CSIC


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Author: Bandi, Franco N.
Year: Since 2002
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Low-Noise and High-Efficiency Near-IR SPADs in 110nm CIS Technology
I. Vornicu, F. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - European Solid-State Device Research Conference ESSDERC 2019
Photon detection at longer wavelengths is much desired for LiDAR applications. Silicon photodiodes with deeper junctions and larger multiplication regions are more sensitive to near-IR photons. This paper presents the complete electro-optical characterization of a P-well/Deep N-well single photon avalanche diode integrated in 110nm CIS technology. Devices with various sizes, shapes and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is of 18V. The proposed structure has 0.4Hz/um2 dark count rate, 0.5% afterpulsing, 188ps FWHM (total) jitter and around 10% photon detection probability at 850nm wavelength. All figures have been measured at 3V excess voltage.

Design of a Compact and Low-Power TDC for an Array of SiPM´s in 110nm CIS Technology
F.N. Bandi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Conference on Ph.D Research in Microelectronics and Electronics PRIME 2017
Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their -to name a few interesting Properties- compactness, lower bias voltage, tolerance to magnetic fields and finer spatial resolution. SiPMs can also be built in CMOS technology. This allows the incorporation of active quenching and recharge schemes at cell level and processing circuitry at pixel level. One of the elements that can lead to finer temporal resolutions is the time-to-digital converter (TDC). In this paper we describe the architecture of a compact TDC to be included at each pixel of an array of SiPMs. It is compact and consumes low power. It is based on a voltage controlled oscillator that generates multiple internal phases that are interpolated to provide time resolution below the time delay of a single gate. Simulation results of a 11b TDC based on a 4-stage VCRO in 110nm CIS technology yield a time resolution of 80.0ps, a DNL of ±0.28 LSB, a INL ±0.52 LSB, and a power consumption of 850μW.

VCRO-based TDCs in submicron CIS technology
F.N. Bandi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2017
Time-to-Digital Converters (TDCs) based on Voltage Controlled Ring Oscillators (VCROs) provides a good trade off between area occupation, time resolution and power consumption. These specifications are determined by applications like nuclear medicine and high energy physics imaging, in which an accurate timestamp of the detected photons is needed and small area footprint to maximize fill factor is desired. This is specially true when the number of incident photons is low and oversampling is impossible. Other TDC architectures like pulse stretching, Vernier delay lines, time amplification or multi-path gated ring oscillator are able to provide finer time resolution at the price of higher area occupation and power consumption. If in sensor intregation is desired, these area and power increments are prohibitive. VCROs provides a large number of alternatives during the design phase, each one with their advantages and disadvantages. The first step is the selection of the stage topology, that is, single-ended, differential and pseudo-differential. In this application, pseudo-differential stages outperforms the other alternatives in terms of lower power consumption, lower jitter and better noise rejection. The second step consist in the selection of a pseudo-differential stage using a common metric. To this end, the two most used pseudo-differential stages were compared in terms of time resolution, by using the small signal model and the GBW product. Analytical expression points out that pseudo-differential stage with cross-coupled inverters have finer time resolution than pseudo-differential stage with cross-coupled PMOS. Pre-layout simulations support the analytical expression and shows a clear difference between the time resolution of each stage.

A CMOS Digital SiPM with Focal-Plane Light-Spot Statistics for DOI Computation
I. Vornicu, F.N. Bandi, R. Carmona-Galán and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, vol. 17, no. 3, pp 632-643, 2017
IEEE    DOI: 10.1109/JSEN.2016.2632200    ISSN: 1530-437X     » doi
Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This paper contemplates the computation of DOI based on the standard deviation of the light distribution. The simulations have been carried out by GAMOS. The design of the proposed digital silicon photomultiplier (d-SiPM) with focal plane detection of the center of mass position and dispersion of the scintillation light is presented. The d-SiPM shares the same off-chip time-to-digital converter such that each pixel can be individually connected to it. A miniature d-SiPM 8×8 single-photon avalanche-diode (SPAD) array has been fabricated as a proof of concept. The SPADs along each row and column are connected through an OR combination technique. It has 256×256μm2 without peripherals circuits and pads. The fill factor is about 11%. The average dark count rate of the mini d-SiPM is of 240 kHz. The average photon detection efficiency is 5% at 480 nm wavelength, room temperature, and 0.9 V excess voltage. The dynamic range is of 96 dB. The sensor array features a time resolution of 212 ps. The photon-timing SNR is 81 dB. The focal plane statistics of the light-spot has been proved as well by measurements.

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