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Author: Delgado Lozano, Ignacio María
Year: Since 2002
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Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A. Acosta
Journal Paper - ACM Journal on Emerging Technologies in Computing Systems, vol. 16,no. 3, article 30, 2020
ACM    DOI: 10.1145/3381857    ISSN: 1550-4832    » doi
[abstract]
The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.

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