Found results matching for:
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles using TFETs
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A.J. Acosta
Journal Paper · IEEE Embedded Systems Letters, vol. 14, no. 2, pp 99-102, 2021
abstract
doi
Projection of dual-rail DPA countermeasures in future FinFET and emerging TFET technologies
I.M. Delgado-Lozano, E. Tena-Sánchez, J. Núñez and A. Acosta
Journal Paper · ACM Journal on Emerging Technologies in Computing Systems, vol. 16, no. 3, article 30, 2020
abstract
doi
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
E. Tena-Sánchez, I.M. Delgado-Lozano, J. Nuñez and A.J. Acosta
Conference · Conference on Design of Circuits and Integrated Systems DCIS 2018
abstract
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