Spanish National Research Council · University of Seville
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IMSE-CNM in Digital.CSIC


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Author: Parsakordasiabi, Mojtaba
Year: Since 2002
All publications
PhD Forum: A survey on FPGA-based high-resolution TDCs
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - International Conference on Distributed Smart Cameras ICSDC 2019
Time-to-digital converters based on Nutt method are especially suitable for FPGA implementation. They are able to provide high resolution, range and linearity with low resources usage. The core of this architecture consist in a coarse counter for long range, a fine time interpolator for high resolution and real-time calibration for high linearity. This paper reviews different time interpolation and real-time calibration techniques. Moreover, a comparison of state-of-the-art FPGA-based TDCs is presented as well.

Evaluation of Architectures for FPGA-Implementation of High-Resolution TDCs
M. Parsakordasiabi, I. Vornicu, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2019
Time-to-digital converters (TDCs) are a central component in systems based on time-delay assessment. The principal characteristics to be sought for in a TDC are high resolution, long time range, linearity and low power consumption. Besides, field-programmable gate arrays (FPGAs) represent an interesting option to explore fully-digital TDC architectures, because of their flexibility, shorter development time and lower implementation cost than ASICs. They are reconfigurable and usually built on the finest silicon technologies. The purpose of this work is to identify the different architectures that lead to high-resolution TDCs on FPGA, and to compare them in terms of the appropriate figures of merit. The most extended method to cover a long time interval while preserving a high time resolution is to combine a coarse counter with a fine time interpolator. Two techniques have been widely used to implement the interpolator, namely a tapped delay line (TDL) and a multiple-phase clock interpolator. Exploiting fast carry chains present in most modern FPGAs, sub-clock-period resolution have been achieved, down to tens of picoseconds. Other important aspects of the TDC design are the thermometer-to-binary encoder, the minimization of the clock skew, the analysis of the influence of voltage and temperature changes and bin-width calibration. Accordingly, we report an analysis of the different TDC architectures on FPGA based on their performance characteristics.

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