Spanish National Research Council · University of Seville
 HOME
INTRANET
esp    ing
IMSE-CNM in Digital.CSIC


 


In all publications
Author: Estrada Pérez, Adrián
Year: Since 2002
All publications
Evaluación multiagente en la formación de profesores noveles
J. Benjumea, A. Estrada, E. Ostúa, O. Rivera, J. Ropero, F. Sivianes and M. Valencia
Book Chapter - Programa de equipos docentes para la formación de profesores noveles, pp 263-275, 2011
FÉNIX EDITORA    ISBN: 978-84-86849-73-3    
[abstract]
Seis profesores noveles y un mentor de Tecnología Electrónica presentan los resultados de su participación dentro de un programa de formación de noveles. En las actividades de observación, que han sido de cuatro tipos, se han utilizado diferentes instrumentos de evaluación (cuantitativos/cualitativos, cerrados/abiertos) y diversos agentes observadores (el propio novel, alumnos suyos, mentor y especialistas pedagógicos). Se presentan los principales resultados que han obtenido los noveles en estas evaluaciones, resultados que muestran una gran coherencia en el análisis de los distintos agentes. Se extraen asimismo los aspectos mejorables del programa y se destaca su principal beneficio: la mejora docente de los participantes.

Problemas de Electrónica Básica
A. Yúfera-García, J. Barbancho-Concejero, A. Estrada-Pérez, F. Sivianes-Castillo and A. Carrasco-Muñoz
Book - 200 p, 2009
LIBRERÍA PANELLA    ISBN: 978-84-934-1149-7    
[abstract]
Abstract not available

Aplicación de medidas de seguimiento y evaluación continua en las prácticas de Arquitectura de Redes de Computadores I (ARCI) y Comunicaciones (CI)
A.V. Medina-Rodríguez, J. Benjumea-Mondéjar, A. Estrada-Pérez, A. Barbancho-Concejero and S. Martín-Guillén
Book Chapter - Experiencia de Innovacion Universitaria (I) Curso 2006-2007, vol. 1, pp 453-461, 2009
ICE UNIVERSIDAD DE SEVILLA    ISBN: 978-84-86849-70-2    
[abstract]
Abstract not available

Aplicación de técnicas de evaluación continua en grupos numerosos de alumnos
M.C. Baena-Oliva, M.J. Bellido-Díaz, A. Estrada-Pérez, J. Juan-Chico, S. Martín-Guillén, A.J. Molina-Cantero, E. Ostua-Aranguena, M.P. Parra-Fernández, O. Rivera-Romero, M.C. Romero-Ternero, J. Ropero-Rodríguez, P. Ruiz de Clavijo-Vázquez, G. Sánchez-Antón, M. Valencia-Barrero and J.M. Gómez-González
Book Chapter - Experiencia de Innovacion Universitaria (I) Curso 2006-2007, vol. 1, pp 350-365, 2009
ICE UNIVERSIDAD DE SEVILLA    ISBN: 978-84-86849-70-2    
[abstract]
Abstract not available

Tecnología de Computadores: Asignaturas en Red. Plan de Renovación de Metodologias Docentes. I Plan Propio de Docencia de la Universidad de Sevilla
A. Yúfera-García, J. Barbancho-Concejero, E. Ostua and A. Estrada Pérez
Book - 2008
UNIVERSIDAD DE SEVILLA    ISBN: 978-84-691-1460-5    
[abstract]
Abstract not available

Partitioning and characterization of high speed adder structures in deep-submicron technologies
A. Estrada, G. Sassaw, C.J. Jiménez and M. Valencia
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
The availability of higher performance (in area, time and power consumption) and greater precision binary adders is a constant requirement in digital systems. Consequently, the design and characterization of adders and, most of all, their adaptation to the requisites of present-day deep-submicron technologies, are today still issues of concern. The binary adder structures in deep-submicron technologies must be revised to achieve the best balance between the number of bits in the adder and its delay, area and power consumption. It is therefore very important to make an effort to carefully optimize adder structures, thus obtaining improvements in digital systems. This communication presents the optimization of adder structures for implementations in deep-submicron technologies through their partitioning into blocks. This partitioning consists of dividing the number of input bits to the adder into several subsets of bits that will constitute the inputs to several adder structures of the same. or of different types. The structures used to accomplish this study range from the more traditional types, such as the carry look ahead adder, the ripple carry adder or the carry select adder, to more innovative kinds, like the parallel prefix adders of the type proposed by Brent-Kung, Han-Carlson, Kogge-Stone or Ladner-Fischer. The analyses carried out allow the characterization of structures implemented in deep-submicron technologies for area, delay and power consumption parameters.

A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
A. Estrada, C.J. Jiménez and M. Valencia
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
Integration technologies have favored the design and implementation of more complex circuits. Thanks to this increased complexity, these circuits are capable of implementing algorithms which a few years ago were too expensive in both area and computational resources. However, they now offer interesting choices which should be considered. This new generation of integrated circuits nevertheless presents other kinds of restrictions that the designer should bear in mind. Parameters such as frequency of operation or power consumption are new restrictions that the designer has to deal with in order to fulfill the conditions established by the circuit functionality. Finally, the shrinking integration scale of current technologies makes the timing behavior of the design differ from previous technologies. Thus, a review of the timing behavior of the digital circuit should be done. So far, arithmetic circuits have been used as a benchmark for the analysis and design procedures of digital circuits. Therefore, it is our goal now to analyze both conventional and modem arithmetic circuits structures for different deep-submicron technologies. To achieve this goal, a good solution is to characterize a set of algorithmic circuits for several deep submicron processes, so that the designer can select the most suitable one depending upon the intended application and existing restrictions. In this paper, the first steps to attain such selection are presented. In particular, we propose a design and VHDL characterization methodology based on an RTL description of each component, on the utilization of an automated synthesis tool, and on the generation of logic characteristics from the logic level. This methodology is applied to a set of adders structures, the results of which are also presented.

Scopus access Wok access