IMSE Publications

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Author: Andrés Santana Andreo
Year: Since 2002

Journal Papers


A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs
A. Santana-Andreo, P. Saraza-Canflanca, H. Carrasco-Lopez, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Integration, vol. 85, pp 1-9, 2022
abstract      doi      

PUFs based on the power-up values of an array of SRAM cells are a popular solution to provide secure and low-cost key generation suitable for IoT devices. However, SRAM cells do not always power up to the same value due to external factors like noise, temperature, or aging. This results in a decrease of reliability for the SRAM PUF, an issue generally solved by employing complex Error Correction Codes (ECCs). However, ECCs significantly increase the cost of the complete system. A way to alleviate this issue is the use of bit selection methods, which increase the reliability of the SRAM PUF by using only the power-up values of the most reliable cells (i.e., the SRAM cells that consistently power up to the same value). In this work, the reduction in ECC complexity through a bit selection method based on the Data Retention Voltage metric is demonstrated.

Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, P. Brox, R. Castro-Lopez, E. Roca and F.V. Fernandez
Journal Paper · Microelectronics Reliability, vol. 118, article 114049, 2021
abstract      doi      pdf

The utilization of power-up values in SRAM cells to generate PUF responses for chip identification is a subject of intense study. The cells used for this purpose must be stable, i.e., the cell should always power-up to the same value (either ‘0’ or ‘1’). Otherwise, they would not be suitable for the identification. Some methods have been presented that aim at increasing the reliability of SRAM PUFs by identifying the strongest cells, i.e., the cells that more consistently power-up to the same value. However, these methods present some drawbacks, in terms of either their practical realization or their actual effectiveness in selecting the strongest cells at different scenarios, such as temperature variations or when the circuits have suffered aging-related degradation. In this work, the experimental results obtained for a new method to classify the cells according to their power-up strength are presented and discussed. The method overcomes some of the drawbacks in previously reported methods. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation and temperature variations, which ultimately translates into the construction of reliable SRAM-based PUFs.

Conferences


Characterization and analysis of BTI and HCI effects in CMOS current mirrors
A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
abstract     

This paper presents experimental results on the aging-induced degradation of CMOS current mirrors fabricated in a 65-nm CMOS technology. A dedicated integrated circuit array with custom test structures allowing for accelerated aging tests is used for the characterization, including several geometries of simple current mirrors, in PMOS and NMOS versions. The bi-directional link between device degradation and bias conditions that comes into play during circuit aging, as well as the permanent degradation, are both reported and analysed.

On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF
E. Camacho-Ruiz, A. Santana-Andreo, R. Castro-Lopez, E. Roca and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
abstract     

Physical Unclonable Functions (PUFs) use variability as an entropy source from which to generate secure authentication and identification. While most silicon PUFs exploit the well-known Time-Zero Variability of CMOS technologies, the lack of efficient simulation tools for the Time- Dependent Variability (TDV) has left the potential benefits of this other kind of variability largely unexplored. However, recent advances in the field are allowing this exploration to begin. The objective of this paper is then to take a recently reported simulation tool to design a novel PUF that uses the Random Telegraph Noise (RTN), a TDV phenomenon, as the underlying entropy source. In the ensuing analysis, essential design guidelines are provided to best exploit such entropy source with factors like transistor biasing and sizing.

Impact of BTI and HCI on the reliability of a majority voter
A. Santana-Andreo, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2022
abstract     

Triple Modular Redundancy is a commonly used hardware technique in mission- and safety-critical systems to ensure reliability. Although a simple circuit, the majority voter can be the weak link in this system and different designs have been proposed to increase its robustness to single event effects and permanent faults. However, no study has been performed to analyze the effect of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on a majority voter, which can lead to timing failures or exacerbate other failure mechanisms. This work uses a state-of-the-art aging simulator to estimate the effects of aging on a majority voter.

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies
P. Saraza-Canflanca, H. Carrasco-Lopez, A. Santana-Andreo, J. Diaz-Fortuny, R. Castro, E. Roca and F.V. Fernandez
Conference · IEEE International Reliability Physics Symposium IRPS 2022
abstract     

Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.

Characterizing Aging Degradation of Integrated Circuits with a Versatile Custom Array of Reliability Test Structures
A. Santana-Andreo, P. Martin-Lloret, E. Roca, R. Castro-Lopez and F.V. Fernandez
Conference · IEEE International Conference on Microelectronic Test Structures ICMTS 2022
abstract     

Abstract not available

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