IMSE Publications

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Author: Luis F. Rojas Muñoz
Year: Since 2002

Journal Papers


True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez and P. Brox
Journal Paper · Electronics, vol. 11, no. 23, article 4028, 2022
abstract      doi      

This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator-physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource-efficiency trade-off already achieved in the design.

Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems
M.C. Martínez-Rodríguez, L.F. Rojas-Muñoz, E. Camacho-Ruiz, S. Sánchez-Solano and P. Brox
Journal Paper · Cryptography, vol. 6, no.4, article 51, 2022
abstract      doi      

The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.

Hardware/Software Co-Design of a Circle Detection System based on Evolutionary Computing
L.F. Rojas-Munoz, H. Rostro-Gonzalez, C.H. Garcia-Capulin and S. Sanchez-Solano
Journal Paper · Electronics, vol. 11, no. 17, article 2686, 2022
abstract      doi      

In recent years, the strategy of co-designing Hardware/Software (HW/SW) systems has been widely adopted to exploit the synergy between both approaches thanks to technological advances that have led to more powerful devices providing an increasingly better cost-benefit trade-off. This paper presents an HW/SW system for the detection of multiple circles in digital images based on a genetic algorithm. It is implemented on an Ultra96-v2 development board, which contains a Xilinx Zynq UltraScale+ MPSoC device and supports a Linux operating system that facilitates application development. The design is powered by developing an interactive computing environment by means of the Jupyter Notebook platform, in which different programming languages coexist. The specific advantages of each of these languages have been used to describe the hardware component that accelerates the evolutionary computation for circle detection (VHDL), to execute SW-HW interaction functions, as well as the pre- and post-processing of the images (ANSI-C) and to code, evaluate, and document the system execution process (Python). As a result, a computationally efficient application was obtained, with high accuracy in the detection of circles in synthetic and real images, and with a high degree of reconfigurability that provides the user with the necessary tools to incorporate it in a specific area of interest.

Embedded system implementation of an evolutionary algorithm for circle detection on programmable devices
L.F.Rojas-Muñoz, S. Sánchez-Solano, C.H.García-Capulín and H. Rostro-González
Journal Paper · Computers & Electrical Engineering, vol. 99, article 107714, 2022
abstract      doi      

Programmable devices combine powerful processing systems with a rich infrastructure of general-purpose and specific logic blocks, making it possible the efficient implementation of embedded systems to perform complex tasks by facilitating hardware acceleration of critical stages to improve their performance. Based on these characteristics, a hardware implementation of a genetic algorithm for circle detection in digital images is described in this paper. The detection system has been designed for Xilinx Zynq-7000 and Zynq UltraScale+ family devices and implemented on two low-cost development boards that reach acceleration factors of 33.12 and 37.3, respectively, when compared to the fully software implementation. Detection results from both development boards have been compared using synthetic and real images from different scenarios. The accuracy and performance achieved demonstrate the suitability of this proposal to design embedded systems with restricted size, resources and energy consumption for applications in Internet of Things, Industry 4.0 and other related paradigms.

Conferences


SoPC Implementation of a Genetic Algorithm for Circle Detection
L.F. Rojas-Muñoz, S. Sánchez-Solano, C.H. García-Capulín and H. Rostro-González
Conference · IEEE International Autumn Meeting on Power, Electronics and Computing ROPEC 2021
abstract     

This article presents a system-on-programable-chip implementation of a genetic algorithm for circle detection. The use of this implementation technique allows the development of an efficient, decentralized and embedded system with high scalability and robustness, in addition to providing it with an effective and easy-to-use interface. The hardware components of the system implement the evolutionary process and the software elements perform image pre-processing tasks and provide the user interface. The SoPC was implemented on a Zybo-Z7 development board equipped with a Xilinx Zynq-7000 family device and it has been numerically validated on synthetic and real images. Detection rates obtained for both types of images demonstrate the suitability of this proposal to design embedded systems with size, resources and power consumption limitations for applications in Industry 4.0 and other related paradigms.

Implementación en SoC de un Sistema Embebido para la Detección de Círculos en Imágenes Digitales
Luis F. Rojas-Muñoz, S. Sánchez-Solano, C.H. García-Capulín and H. Rostro-González
Conference · Congreso Internacional de Investigación Academia Journals Celaya CELAYA 2021
abstract     

Los dispositivos basados en lógica programable que incorporan potentes sistemas de procesamiento permiten la implementación eficiente de sistemas embebidos que realizan tareas complejas, facilitando la aceleración en hardware de sus etapas críticas para mejorar su eficiencia. En este artículo se presenta el diseño de un sistema de detección de círculos en imágenes digitales basado en un algoritmo genético e implementado en la placa de desarrollo Pynq-Z2. Esta placa contiene un dispositivo Zynq-7000 SoC de Xilinx que incluye un procesador ARM Cortex-A9 de doble núcleo. Los beneficios que brindan la lógica programable y el sistema de procesado son aprovechados para acelerar el algoritmo genético mediante su implementación en hardware y llevar a cabo las etapas de pre- y post-procesamiento de la imagen en software. La aplicación Jupyter Notebook, incorporada en el entorno de desarrollo PYNQ (Phython productivity for Zynq), permite utilizar funciones y librerías en Python para controlar de manera interactiva el flujo de datos entre los componentes software/hardware del sistema y los periféricos de entrada/salida. Los resultados obtenidos en precisión y rendimiento demuestran la idoneidad de esta propuesta para diseñar sistemas embebidos con tamaño, recursos y consumo de energía restringidos.

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