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Author: Liñán Cembrano, Gustavo
Year: Since 2002
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Does the use of nest materials in a ground-nesting bird result from a compromise between the risk of egg overheating and camouflage?
J. Gómez, G. Liñán-Cembrano, C. Ramo, M. Castro, A. Pérez-Hurtado and J.A. Amat
Journal Paper - Biology Open, bio.042648, first online, 2019
THE COMPANY OF BIOLOGISTS    DOI: 10.1242/bio.042648    ISSN: 2046-6390    » doi
[abstract]
Many studies addressing the use of nest materials by animals have focused on only one factor to explain its function. However, the consideration of more than one factor could explain the apparently maladaptive choice of nest materials that makes the nests conspicuous to predators. We experimentally tested whether there is a trade-off in the use of nest materials between the risks of egg predation versus protection from overheating. We studied the ground-nesting Kentish plover, Charadrius alexandrinus, in southern Spain. We added materials differing in their thermal properties and coloration to the nests, thus affecting rates of egg heating and nest temperature and camouflage. Before these manipulations, adults selected materials that were lighter than the microhabitat, probably to buffer the risk of egg overheating. However, the adults did not keep the lightest experimental materials, probably because they reduced camouflage, and this could make the nests to be even more easily detectable by predators. In all nests, adults removed most of the experimental materials independently of their properties, so that egg camouflage returned to the original situation within a week of the experimental treatments. Although the thermal environment may affect the choice of nest materials by the plovers, the ambient temperatures were not too high at our study site as to determine the acceptance of the lightest experimental materials.

The protoporphyrin content of Kentish Plover Charadrius alexandrinus eggshells is better predicted by the fractal dimension of spottiness than by colour
J. Gómez, G. Liñán-Cembrano, M. Castro, A. Pérez-Hurtado, C. Ramo and J.A. Amat
Journal Paper - Journal of Ornithology, vol. 160, no. 2, pp 409-415, 2019
SPRINGER    DOI: 10.1007/s10336-018-1616-2    ISSN: 2193-7192    » doi
[abstract]
Quantifying the pigment content in avian eggshells is important for the validation of hypotheses on the functionality of eggshell coloration. The few studies that have analysed whether eggshell coloration and spottiness are related to pigment content have found contradictory results. In this study, we analysed whether the coloration and the degree of spottiness of Kentish Plover Charadrius alexandrinus eggshells are related to pigment concentrations (protoporphyrin and biliverdin). We also examined whether the concentrations of these pigments are related to the fractal dimension (FD) of spottiness. The FD of spottiness may be useful as a simple standardized method to quantify complex patterning. We found that protoporphyrin was more abundant than biliverdin in eggshells. Contrary to expectations, the content of protoporphyrin was not related to eggshell colour, probably due to a different allocation of pigments between the spots and the background of the eggshell, and/or to the different allocation of pigments among eggshell layers. However, we found a positive relationship between the FD of eggshell spottiness and the amount of protoporphyrin. It is likely that the FD of spottiness (indicative not only of spot size and the degree of spottiness, but also of how convoluted the outlines of spots are and how spots are distributed across an eggshell) may be related to the mechanical function of protoporphyrin (e.g. in strengthening eggshells, which may interfere with the fractal structure of potential fractures), and/or it may also improve egg camouflage. However, more studies in other avian species are needed to evaluate if the FD of spottiness is a good surrogate for protoporphyrin content in eggshells.

Individual egg camouflage is influenced by microhabitat selection and use of nest materials in ground-nesting birds
J. Gómez, C. Ramo, J. Troscianko, M. Stevens, M. Castro, A. Pérez-Hurtado, G. Liñán-Cembrano and J.A. Amat
Journal Paper - Behavioral Ecology and Sociobiology, vol. 72, article 142, 2018
SPRINGER    DOI: 10.1007/s00265-018-2558-7    ISSN: 0340-5443    » doi
[abstract]
Camouflage is a widespread strategy to avoid predation and is of particular importance for animals with reduced mobility or those in exposed habitats. Camouflage often relies on matching the visual appearance of the background, and selecting fine-scale backgrounds that complement an individual´s appearance is an effective means of optimising camouflage. We investigated whether there was an active selection of microhabitats and nest materials in three ground-nesting birds (pied avocet, Kentish plover, and little tern) to camouflage their eggs using avian visual modelling. Plovers and avocets selected substrates in which their eggs were better camouflaged, and that choice was done at an individual level. Terns have lighter, less spotted eggs, and while they did select lighter background than the other species, their eggs were a poor match to their backgrounds. The worse matching of the tern eggs was likely due to a compromise between thermal protection and camouflage because they breed later, when temperatures are higher. Finally, the addition of nest materials improved egg camouflage in terms of luminance, although the materials reduced pattern matching, which may be associated with the different roles that the nest materials play. Active selection of substrates at an individual level may be crucial to improve nest success in species that nest in exposed sites.

Latitudinal variation in biophysical characteristics of avian eggshells to cope with differential effects of solar radiation
J. Gómez, C. Ramo, M. Stevens, G. Liñán-Cembrano, M.A. Rendón, J.C. Troscianko and J.A. Amat
Journal Paper - Ecology and Evolution, vol 8, no. 16, pp 8019-8029, 2018
JOHN WILEY & SONS    DOI: 10.1002/ece3.4335    ISSN: 2045-7758    » doi
[abstract]
Solar radiation is an important driver of animal coloration, not only because of the effects of coloration on body temperature but also because coloration may protect from the deleterious effects of UV radiation. Indeed, dark coloration may protect from UV, but may increase the risk of overheating. In addition, the effect of coloration on thermoregulation should change with egg size, as smaller eggs have higher surface-volume ratios and greater convective coefficients than larger eggs, so that small eggs can dissipate heat quickly. We tested whether the reflectance of eggshells, egg spottiness, and egg size of the ground-nesting Kentish plover Charadrius alexandrinus is affected by maximum ambient temperature and solar radiation at breeding sites. We measured reflectance, both in the UV and human visible spectrum, spottiness, and egg size in photographs from a museum collection of plover eggshells. Eggshells of lower reflectance (darker) were found at higher latitudes. However, in southern localities where solar radiation is very high, eggshells are also of dark coloration. Eggshell coloration had no significant relationship with ambient temperature. Spotiness was site-specific. Small eggs tended to be light-colored. Thermal constraints may drive the observed spatial variation in eggshell coloration, which may be lighter in lower latitudes to diminish the risk of overheating as a result of higher levels of solar radiation. However, in southern localities with very high levels of UV radiation, eggshells are of dark coloration likely to protect embryos from more intense UV radiation. Egg size exhibited variation in relation to coloration, likely through the effect of surface area-to-volume ratios on overheating and cooling rates of eggs. Therefore, differential effects of solar radiation on functions of coloration and size of eggshells may shape latitudinal variations in egg appearance in the Kentish plover.

Effects of network modularity on the spread of perturbation impact in experimental metapopulations
L.J. Gilarranz, B. Rayfield, G. Linan-Cembrano, J. Bascompte and A. Gonzalez
Journal Paper - Science, vol. 357, no. 6347, pp 199-201, 2017
AAAS    DOI: 10.1126/science.aal4122    ISSN: 0036-8075    » doi
[abstract]
Networks with a modular structure are expected to have a lower risk of global failure. However, this theoretical result has remained untested until now. We used an experimental microarthropod metapopulation to test the effect of modularity on the response to perturbation. We perturbed one local population and measured the spread of the impact of this perturbation, both within and between modules. Our results show the buffering capacity of modular networks. To assess the generality of our findings, we then analyzed a dynamical model of our system. We show that in the absence of perturbations, modularity is negatively correlated with metapopulation size. However, even when a small local perturbation occurs, this negative effect is offset by a buffering effect that protects the majority of the nodes from the perturbation.

Incubating terns modify risk-taking according to diurnal variations in egg camouflage and ambient temperature
J.A. Amat, J. Gómez, G. Liñán-Cembrano, M.A. Rendón and C. Ramo
Journal Paper - Behavioral Ecology and Sociobiology, vol. 71, no. 4, article 72, 2017
SPRINGER    DOI: 10.1007/s00265-017-2306-4    ISSN: 0340-5443    » doi
[abstract]
Studies of risk-taking by breeding birds have frequently addressed the effect of brood value on the decisions taken by incubating birds when predators approach their nests. However, leaving eggs unattended during predator disturbance may expose embryos to other potentially harmful factors, to which parent birds should respond when making decisions about when to leave or return to their nest. In this study, we show that diurnal changes in flushing behaviour of incubating terns from nests during predator approach were affected by egg camouflage, the terns allowing a closer approach to individual nests when the eggs appeared better camouflaged. Return times to the nests were affected by ambient temperature, with the terns shortening such times at high ambient temperatures, thus diminishing the risk of egg overheating. As a whole, our results show that the decisions of the birds on when to leave or return to their nests depended on shifting payoffs, as a consequence of diurnal variations in both the thermal risks incurred by embryos and egg crypsis. Environmental costs of risk-taking, such as those considered here, should be addressed in studies of risk-taking by breeding birds. This type of study may have implications for our knowledge of cognitive processes that affect risk-taking.

SpotEgg: An image-processing tool for automatised analysis of colouration and spottiness
J. Gómez and G. Liñán-Cembrano
Journal Paper - Journal of Avian Biology, vol. 48, no. 4, pp 502-512, 2017
BLACKWELL PUBLISHING    DOI: 10.1111/jav.01117    ISSN: 1600-048X    » doi
[abstract]
Colouration and patterning are widespread amongst organisms. Regarding avian eggs, colouration (reflectances) has been previously measured using spectrometers whereas spottiness has been determined using human-based scoring methods or by applying global thresholding over the luminance channel on photographs. However, the availability of powerful computers and digital image-processing algorithms and software offers new possibilities to develop systematised, automatable, and accurate methods to characterise visual information in eggs. Here, we provide a computing infrastructure (library of functions and a Graphical User Interface) for eggshell colouration and spottiness analysis called SpotEgg, which runs over MATLAB. Compared to previous methods, our method offers four novelties for eggshell visual analysis. First, we have developed a standardised non-human biased method to determine spottiness. Spottiness determination is based on four parameters that allow direct comparisons between studies and may improve results when relating colouration and patterning to pigment extraction. Second, researcher time devoted to routine tasks is remarkably reduced thanks to the incorporation of image-processing techniques that automatically detect the colour reference chart and egg-like shapes in the scene. Third, SpotEgg reduces the errors in colour estimation through the eggshell that are created by the different angles of view subtended from different parts of the eggshell and the optical centre of the camera. Fourth, SpotEgg runs automatic Fractal Dimension analysis (a measure of how the details in a pattern change with the scale at which this pattern is measured) of the spots pattern in case researchers want to relate other measurements with this special spatial pattern. Finally, although initially conceived for eggshell analysis, SpotEgg can also be applied in images containing objects different from eggs as feathers, frogs, insects, etc., since it allows the user to manually draw any region to be analysed making this tool useful not only for oologist but also for other evolutionary biologists.

Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms
M. Velasco-Jiménez, R. Castro-López and J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems, ISCAS 2016
[abstract]
This demo shows how to use multi-objective evolutionary algorithms for the optimum high-level design of ΣΔ analog-to-digital converters. The methodology illustrated in the demo is based on the combination of SIMSIDES, a SIMULINK-based time-domain behavioral simulator for ΣΔ modulators, with multi-objective optimization techniques. The proposed methodology allows designers to explore the design space in an efficient and intuitive way in order to fulfill a number of different design objectives simultaneously, by finding out the best sets of target specifications - defined as Pareto-optimal fronts. The presented approach can be extended to several kinds of optimizers implemented in MATLAB, and diverse examples are illustrated so that visitors will learn how to apply it to their own designs and projects. Although the demo is focused on ΣΔ ADCs, the tools shown in the demo can be used for the optimization of any other analog integrated circuits and systems.

Hairiness: the missing link between pollinators and pollination
J.R. Stavert, G. Liñán-Cembrano, J.R. Beggs, B.G. Howlett, D.E. Pattemore and I. Bartomeus
Journal Paper - PeerJ, vol. 2016, no. 12, article no. e2779, 2016
PEERJ    DOI: 10.7717/peerj.2779    ISSN: 2167-8359    » doi
[abstract]
Functional traits are the primary biotic component driving organism influence on ecosystem functions; in consequence, traits are widely used in ecological research. However, most animal trait-based studies use easy-to-measure characteristics of species that are at best only weakly associated with functions. Animal-mediated pollination is a key ecosystem function and is likely to be influenced by pollinator traits, but to date no one has identified functional traits that are simple to measure and have good predictive power. Here, we show that a simple, easy to measure trait (hairiness) can predict pollinator effectiveness with high accuracy. We used a novel image analysis method to calculate entropy values for insect body surfaces as a measure of hairiness. We evaluated the power of our method for predicting pollinator effectiveness by regressing pollinator hairiness (entropy) against single visit pollen deposition (SVD) and pollen loads on insects. We used linear models and AICC model selection to determine which body regions were the best predictors of SVD and pollen load. We found that hairiness can be used as a robust proxy of SVD. The best models for predicting SVD for the flower species Brassica rapa and Actinidia deliciosa were hairiness on the face and thorax as predictors (R2 = 0.98 and 0.91 respectively). The best model for predicting pollen load for B. rapa was hairiness on the face (R2 = 0.81). Accordingly, we suggest that the match between pollinator body region hairiness and plant reproductive structure morphology is a powerful predictor of pollinator effectiveness. We show that pollinator hairiness is strongly linked to pollination -an important ecosystem function, and provide a rigorous and time-efficient method for measuring hairiness. Identifying and accurately measuring key traits that drive ecosystem processes is critical as global change increasingly alters ecological communities, and subsequently, ecosystem functions worldwide.

Networks under the microscope, buffering pertubations
L.J. Gillarranz, B. Rayfield, G. Liñán-Cembrano, J. Bascompte and A. González
Conference - International School and Conference on Network Science NetSci2015
[abstract]
Connectivity is an important characteristic in many systems, from landscapes to food webs. The more connected a systems is, the easier is the flow of individuals or biomass across the system. However, connectivity is a two-edged sword. When facing a perturbation, it spreads through the very same routes that in normal conditions are beneficial to the system. Therefore, how can we engineer a system that minimizes perturbation spread while keeping a high connectivity?
Theoretical approaches to this question seem to encounter the answer in systems organized in compartments or modules. The constituent nodes of those systems are organized in compartments where nodes within a compartment tend to be connected among themselves while showing much fewer connections with nodes from other compartments. However, the consequences of a modular system have never been explored empirically.
Here, we develop a microcosm experiment to measure how a perturbation spreads through a network. Hundreds of individuals of an arthropod species, Folsomia candida, live in the nodes and disperse freely between them. As a perturbation we severely diminish population size at a local patch. We record the spatiotemporal dynamics of the system before and after a perturbation occurs. For that, we use state-of-the-art image recognition techniques.

Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression
S. Vargas-Sierra, G. Liñan-Cembrano and A. Rodriguez-Vazquez
Conference - IEEE International Symposium on Circuits and Systems, ISCAS 2015
[abstract]
This demonstration targets the acquisition of realtime video sequences involving High Dynamic Range (HDR) scenes. Adaptation to different illumination conditions while preserving contrast is achieved by using a sensor chip, which implements an adaptive content-aware tone mapping compression algorithm by using in-pixel circuitry. Its response gets adapted to changing illumination conditions by using at each frame a statistical estimation of the light distribution, which is derived from the HDR histogram calculated at the previous frame. This method allows adaptive HDR video, while capable to capture very large DR scenes including moving objects.

A 151 dB high dynamic range CMOS image sensor chip architecture with tone mapping compression embedded in-pixel
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Journal Paper - IEEE Sensors Journal, vol. 15, no. 1, pp 180-195, 2015
IEEE    DOI: 10.1109/JSEN.2014.2340875    ISSN: 1530-437X    » doi
[abstract]
This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone mapping algorithm during image capture operation. The histogram of the previous frame of an auxiliary image, which contains time stamp information, is employed as an estimation of the probability of illuminations impinging pixels at the present frame. The compression function of illuminations, namely tone mapping curve, is calculated using this histogram. A QCIF resolution proof-of-concept prototype has been fabricated using a 0.35 μm opto-flavored standard technology. The sensor is capable of mapping scenes with a maximum intra-frame dynamic range of 151 dB (25 bits/pixel in linear representation) by compressing them to only 7 bits/pixel, while keeping visual quality in details and contrast. The in-pixel on-the-fly fully parallel tone mapping achieves high-frame rate allowing real-time high dynamic range video (120 dB at 30 frames/s).

A tone mapping algorithm for acquisition of high dynamic range images using event-driven adaptive digital CMOS pixels
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 77, no. 3, pp 401-413, 2013
SPRINGER    DOI: 10.1007/s10470-013-0204-x    ISSN: 0925-1030    » doi
[abstract]
An algorithm for the tone mapping of high dynamic range (HDR) scenes in digital CMOS pixels has been developed. The algorithm performs a content-aware compression over HDR scenes, which produces a representation of several decades of acquired data while keeping the main contents in the scene using only 7-bits/pixel.

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
R. Carmona-Galán, Á. Zarándy, C. Rekeczky, P. Földesy, A. Rodríguez-Pérez, C. Domínguez-Matas, J. Fernández-Berni, G. Liñán-Cembrano, B. Pérez-Verdú, Z. Kárász, M. Suárez-Cambre, V. Brea-Sánchez, T. Roska, Á. Rodríguez-Vázquez
Journal Paper - Journal of Systems Architecture, vol. 59, no. 10 part A, pp 908-919, 2013
ELSEVIER    DOI: 10.1016/j.sysarc.2013.03.002    ISSN: 1383-7621    » doi
[abstract]
This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15 μm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.

CMOS-3D Smart Imager Architectures for Feature Detection
V.M. Brea, J. Fernández-Berni, R. Carmona-Galán, G. Liñán, D. Cabello and A. Rodríguez-Vázquez
Journal Paper - IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 4, pp 723-736, 2012
IEEE    DOI: 10.1109/JETCAS.2012.2223552    ISSN: 2156-3357    » doi
[abstract]
This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.

Control and Acquisition System for a High Dynamic Range CMOS Image Sensor
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
A control and acquisition system for the visualization of the images captured with a High Dynamic Range (HDR) CMOS Image Sensor is developed. The image sensor is inserted in a PCB system, which performs low level control, in communication with a PC software, which performs high level control and images visualization. In order to make it user-friendly, we have opted to use object-oriented method to implement the computer software. The system has an attractive interface, and it is easy to operate. It also includes additional functionalities, such as the increment of the frame rate, enhancement of human perception of details contained in the depicted scene and the possibility to display statistical data for illustrating the behavior of the chip.

Design of a smart camera SoC in a 3D-IC technology
R. Carmona-Galán, J. Fernández-Berni, S. Vargas-Sierra, G. Liñán-Cembrano, A. Rodríguez-Vázquez, V. Brea-Sánchez, M. Suárez-Cambre and D. Cabello-Ferrer
Conference - Workshop on Architecture of Smart Camera, 2012
[abstract]
Conventional digital signal processing architectures introduce data bottlenecks and are inefficient when dealing with multidimensional sensory signals; Architectures adapted to the nature of the stimulus are more efficient in terms of power consumption per operation but¿;Concurrent sensing, processing and memory in planar technologies introduces serious limitations to image resolution and image size via the penalties in fill factor and pixel pitch; 3D integrated circuit technologies with a dense TSV distribution permits eliminating data bottlenecks without degrading image resolution and size.

A 148dB focal-plane tone-mapping QCIF imager
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2012
[abstract]
This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by an in-pixel tone-mapping scheme [1]. The tone mapping curve (TMC) is calculated from the histogram of an auxiliary previous image, which serves as a probability indicator of the distribution of illuminations within the current frame. The chip maps 148dB scenes onto 7-bit/pixel coding, containing illuminations from 2.2mlux (SNR10) to 55.33klux -with extreme values captured at 8s and 2.34μs, respectively. Pixels use an Nwell-Psubstrate photodiode and autozeroing for establishing the reset voltage. Measured sensitivity is 5.79 V over lux·s. Dark current effects in the final image are attenuated by an automatic programming of the DAC levels. The chip has been fabricated in the 0.35μm OPTO technology from AMS.

A 176x144 148dB adaptive tone-mapping imager
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference - Sensors, Cameras, and Systems for Industrial and Scientific Applications XIII IMAGING 2012
[abstract]
This paper presents a 176x144 (QCIF) HDR image sensor where visual information is simultaneously captured and adaptively compressed by means of an in-pixel tone mapping scheme.(1) The tone mapping curve (TMC) is calculated from the histogram of a Time Stamp image captured in the previous frame, which serves as a probability indicator of the distribution of illuminations within the present frame. The chip produces 7-bit/pixel images that can map illuminations from 311 mu lux to 55.3 klux in a single frame in a way that each pixel decides when to stop observing photocurrent integration-with extreme values captured at 8s and 2.34 mu s respectively. Pixels size is 33x33 mu m(2), which includes a 3x3 mu m(2) Nwell-Psubstrate photodiode and an autozeroing technique for establishing the reset voltage, which cancels most of the offset contributions created by the analog processing circuitry. Dark signal (10.8mV/s) effects in the final image are attenuated by an automatic programming of the DAC top voltage. Measured characteristics are Sensitivity 5.79V/lux-s s, FWC 12.2ke(-),Conversion Factor 129(e(-)/DN), and Read Noise 25e(-). The chip has been designed in the 0.35 mu m OPTO technology from Austriamicrosystems (AMS). Due to the focal plane operation, this architecture is especially well suited to be implemented in a 3D (vertical stacking) technology using per-pixel TSVs.

A focal plane processor for continuous-time 1-D optical correlation applications
G. Liñán-Cembrano, L. Carranza, B. Alexandre, A. Rodríguez-Vázquez, P. de la Fuente and T. Morlanes
Book Chapter - Focal-Plane Sensor-Processor Chips, pp 151-179, 2011
SPRINGER    DOI: 10.1007/978-1-4419-6475-5_7    ISBN: 978-1-4419-6474-8    » doi
[abstract]
This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation applications. The chip contains 200 sensory processing elements, which acquire light patterns through a 2mm×10.9μm photodiode. The photogenerated current is scaled at the pixel level by five independent 3-bit programmable-gain current scaling blocks. The correlation patterns are defined as five sets of two hundred 3-bit numbers (from 0 to 7), which are provided to the chip through a standard I2C interface. Correlation outputs are provided in current form through 8-bit programmable gain amplifiers (PGA), whose configurations are also defined via I2C. The chip contains a mounting alignment help, which consists of three rows of 100 conventional active pixel sensors (APS) inserted at the top, middle and bottom part of the main photodiode array. The chip has been fabricated in a standard 0.35μm CMOS technology and its maximum power consumption is below 30mW. Experimental results demonstrate that the chip is able to process interference patterns moving at an equivalent frequency of 500kHz.

A QCIF 145dB Imager For Focal Plane Processor Chips Using a Tone Mapping Technique in Standard 0.35μm CMOS Technology
S. Vargas-Sierra, G. Liñán-Cembrano and A. Rodríguez-Vázquez
Conference - International Image Sensor Workshop IISW 2011
[abstract]
This paper presents a QCIF HDR imager where visual informatioin is simultaneously captured and adptively compressed by means of an in-pixel tone mapping scheme. The tone mapping curve (TCM) is calculated from a non-linear histogram of the previous image, wich serves as a probability indicator of the distribution of illuminations within the present frame. The chip produces 7-bit/pixel images that can map illuminations from 311x10(-6)lux to 5875 lux in a single frame in a way that each pixel decides when to stop observing photocurrent integration -with exttreme values captured at 8s and 20μs respectively. Pixels use a 3x3μm2 Nwell-Psubstrate photodiode and an autozeroing technique for establishing the reset voltage, which cancels most of the offset contributions created by the analog processing circuitry. Measured sensitivity is 5.79 v/lux.s. Dark current effects in the final image are attenuated by an automatic programming of the DAC top voltage. The chip has been designed in the 0.35 μm OPTO technology from AMS.

VISCUBE: A multi-layer vision chip
A. Zarándy, C. Rekeczky, P. Földesy, R. Carmona-Galán, G. Liñán-Cembrano, S. Gergely, A. Rodríguez-Vázquez and T. Roska
Book Chapter - Focal-Plane Sensor-Processor Chips, pp 181-208, 2011
SPRINGER    DOI: 10.1007/978-1-4419-6475-5_8    ISBN: 978-1-4419-6474-8    » doi
[abstract]
Vertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital processor arrays on a four layer structure is introduced. The mixed-signal processor array is designed to perform early image processing, while the role of the digital processor array is to accomplish foveal processing. The architecture supports multiscale, multifovea processing. The chip has been designed on a 0.15um feature sized 3DM2 SOI technology provided by MIT Lincoln Laboratory.

Demo: Real-time remote reporting of active regions with Wi-FLIP
J. Fernández-Berni, R. Carmona-Galán, G. Liñán-Cembrano, A. Zarándy and A. Rodríguez-Vázquez
Conference - ACM/IEEE International Conference on Distributed Smart Cameras ICDSC 2011
[abstract]
This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration of FLIP-Q, a focal-plane low-power image processor, and Imote2, a commercial WSN platform. The application, though simple, shows the potentiality of the reduced scene representations achievable at FLIP-Q to speed up the processing. It consists of detecting the active regions within the scene being surveyed, that is, those regions undergoing thresholded variations with respect to the background. If an activity pattern is prescribed, FLIP-Q enables the reconfigurability of the image plane accordingly, making its detection and tracking easier. For each frame, the number of active regions is calculated and wirelessly reported in real time. A base station picks up the radio signal and sends the information to a PC via USB, also in real time. Frame rates up to around 10fps have been achieved, although it greatly depends on the light conditions and the image plane division grid. © 2011 IEEE.

Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor
J. Fernández-Berni, R. Carmona-Galán, G. Liñán-Cembrano, A. Zarándy and A. Rodríguez-Vázquez
Conference - ACM/IEEE International Conference on Distributed Smart Cameras ICDSC 2011
[abstract]
This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, and Imotel, a commercial WSN platform. In Wi-FLIP, image processing is not only constrained to the digital domain like in conventional architectures. Instead, its image sensor - the FLIP-Q prototype - incorporates pixel-level processing elements (PEs) implemented by analog circuitry. These PEs are interconnected, rendering a massively parallel SIMD-based focal-plane array. Low-level image processing tasks fit very well into this processing scheme. They feature a heavy computational load composed of pixel-wise repetitive operations which can be realized in parallel with moderate accuracy. In such circumstances, analog circuitry, not very precise but faster and more area- and power-efficient than its digital counterpart, has been extensively reported to achieve better performance. The Wi-FLIP's image sensor does not therefore output raw but pre-processed images that make the subsequent digital processing much lighter. The energy cost of such pre-processing is really low - 5.6mW for the worst-case scenario. As a result, for the configuration where the Imote2's processor works at minimum clock frequency, the maximum power consumed by our prototype represents only the 5.2% of the whole system power consumption. This percentage gets even lower as the clock frequency increases. We report experimental results for different algorithms, image resolutions and clock frequencies. The main drawback of this first version of Wi-FLIP is the low frame rate reachable due to the non-standard GPIO-based FLIPQ-to-Imote2 interface. © 2011 IEEE.

High-dynamic range tone-mapping algorithm for focal plane processors
S. Vargas-Sierra, G. Liñan-Cembrano, E. Roca and A. Rodríguez-Vázquez
Conference - SPIE Microtechnologies for the New Millennium 2011
[abstract]
This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors (FPP) due to its very limited computing requirements since only local memories, little digital control and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure time to create a 4-bit non-linear image whose histogram determines the shape of the tone-mapping curve which is applied to create the final image. Simulations results over a highly bimodal 120dB image are presented showing that both the highly and poorly illuminated parts of the image keep a sufficient level of details.

Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3D technology
M. Suárez, V.M. Brea, C. Domínguez-Matas, R. Carmona, G. Liñán and A. Rodríguez-Vázquez
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2010
[abstract]
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS-3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW.

In-pixel ADC for a vision architecture on CMOS-3D technology
M. Suarez, V.M. Brea, C. Dominguez Matas, R. Carmona, G. Liñán and A. Rodríguez-Vázquez
Conference - IEEE 3D System Integration Conference 3DIC 2010
[abstract]
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a resolution of 320 × 240 pixels bump-bonded to a three-tier chip on the 150 nm FDSOI CMOS-3D technology from MIT-Lincoln Laboratories. The top tier is a mixed-signal layer with 160 × 120 processing elements. The ADC is distributed between the top two tiers. The top tier contains both global and local circuitry. The ramp generation is implemented with global circuitry through an 8-bit unary current-steering DAC. The end of conversion at every pixel or processing element is triggered by a local comparator. The digital words are stored in a frame-buffer in an intermediate tier. The area of the local circuitry in the ADC is consumed by the comparator, capable of reaching less than 3 mV of resolution in less than 150 ns with less than 220 μm2, and by the memory cells, each one storing 6 8-bit words along with two additional bits in less than 50 μm × 50 μm. Every ADC conversion is performed in less than 120 μs.

A FPP-Oriented Tone Mapping Technique for High Dynamic Range Imagers Using Temporal and Final Exposure Measurements
S. Vargas-Sierra, G. Liñán-Cembrano, E. Roca-Moreno and A. Rodríguez-Vázquez
Conference - European Solid State Circuits Conference ESSCIRC 2010
[abstract]
This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors due to its very limited computing requirements since only local memories and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure time to create a 4-bit artificial image whose histogram determines the shape of the tone-mapping curve which is applied to create the final image. Simulations results over a highiy bimodal120dB image are presented showing that both the highiy and poorly iiiuminated parts of the image keep a sufficient level of details.

A 3-D chip architecture for optical sensing and concurrent processing
A. Rodríguez-Vázquez, R. Carmona, C. Domínguez-Matas, M. Suárez-Cambre, V. Brea, F. Pozas, G. Liñán, P. Foldessy, A. Zarandy and C. Rekeczky
Conference - SPIE EUROPHOTONICS 2010
[abstract]
This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5um x 5um pitch. © 2010 Copyright SPIE - The International Society for Optical Engineering.

Pixel Design and Evaluation In CMOS Image Sensor Technology
S. Vargas-Sierra, E. Roca-Moreno and G. Liñán-Cembrano
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2009
[abstract]
A chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor (APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses. Besides, structures to study the influence of crosstalk between pixels have been incorporated.

APS design alternatives in 0.18 μm CMOS image sensor technology
S. Vargas-Sierra, E. Roca, G. Liñán-Cembrano
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
This paper presents a chip designed for the purpose of evaluating different design alternatives in a 0.18 mu m CMOS Image Sensor Technology (CIS) for Active Pixel Sensor (APS) based vision applications. CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. It also allows the use of special structures, such as color light filters and microlenses. This chip includes a set of pixel architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses. Besides, structures to study the influence of crosstalk between pixels have been incorporated.

A focal plane processor for continuous-time 1-D optical correlation applications
G. Liñán-Cembrano, L. Carranza, B. Alexandre, E. Roca and A. Rodríguez-Vázquez
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
This paper describes a 1-D Focal Plane Processor incorporating 200 pixels for Continuous-Time Optical Correlation Applications. Each pixel incorporates a 2mmx10.9mm photodiode whose current is scaled, at the pixel level, by 5 independent 3-bit programmable-gain current amplifiers. Correlation patterns, defined as 5 sets of 200 3-bits numbers, are communicated to the chip via . a standard (IC)-C-2 interface. Correlation outputs are provided in current form through independent 8-bit-programmable amplifiers whose gains are also defined via I2C. The chip contains an alignment help by incorporating 3 rows of 100 conventional Active Pixel Sensors (AI'S) inserted at the top, middle, and lower part of the main photodiode array. The chip has been fabricated in a standard 0.35mm CMOS technology and maximum power consumption is below 30mW.

Integrated circuitry to detect slippage inspired by human skin and artificial retinas
R. Maldonado-López, F. Vidal-Verdú, G. Liñán and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 8, pp 1554-1565, 2009
IEEE    DOI: 10.1109/TCSI.2008.2008290    ISSN: 1549-8328    » doi
[abstract]
This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage via the data provided by a tactile sensor. Some implementations use different layers of piezoresistive and piezoelectric materials to build upon the raw sensor and obtain the static (pressure) as well as the dynamic (slippage) information. In this paper, a simple raw sensor is used, and a circuitry is implemented, which is able to extract the dynamic information from a single piezoresistive layer. The circuitry was inspired by structures found in human skin and retina, as they are biological systems made up of a dense network of receptors. It is largely based on an artificial retina [22], which is able to detect motion by using relatively simple spatial temporal dynamics. The circuitry was adapted to respond in the bandwidth of microvibrations produced by early slippage, resembling human skin. Experimental measurements from a chip implemented in a 0.35-m four-metal two-poly standard CMOS process are presented to show both the performance of the building blocks included in each processing node and the operation of the whole system as a detector of early slippage.

Insect-vision inspired collision warning vision processor for automobiles
G. Liñán-Cembrano, L. Carranza, C. Rind, A. Zarandy, M. Soininen and A. Rodríguez-Vázquez
Journal Paper - IEEE Circuits and Systems Magazine, vol. 8, no. 2, pp 6-24, 2008
IEEE    DOI: 10.1109/MCAS.2008.916097    ISSN: 1531-636X    » doi
[abstract]
Vision is expected to play important roles for car safety enhancement. Imaging systems can be used to enlarging the vision field of the driver. For instance capturing and displaying views of hidden areas around the car which the driver can analyze for safer decision-making. Vision systems go a step further. They can autonomously analyze the visual information, identify dangerous situations and prompt the delivery of warning signals. For instance in case of road lane departure, if an overtaking car is in the blind spot, if an object is approaching within collision course, etc. Processing capabilities are also needed for applications viewing the car inteRíor such as "intelligent airbag systems" that base deployment decisions on passenger features. On-line processing of visual information for car safety involves multiple sensors and views, huge amount of data per view and large frame rates. The associated computational load may be prohibitive for conventional processing architectures. Dedicated systems with embedded local processing capabilities may be needed to confront the challenges. This paper describes a dedicated sensory-processing architecture for collision warning which is inspired by insect vision. Particularly, the paper relies on the exploitation of the knowledge about the behavior of Locusta Migratoria to develop dedicated chips and systems which are integrated into model cars as well as into a commercial car (Volvo XC90) and tested to deliver collision warnings in real traffic scenaríos.

Integrated circuit interface for artificial skins
R. Maldonado-López, F. Vidal-Verdú, G. Liñán and A. Rodríguez-Vázquez
Conference - Conference on Bioengineered and Bioinspired Systems III, 2007
[abstract]
Artificial sensitive skins are intended to emulate the human skin to improve the skills of robots and machinery in complex unstructured environments. They are basically smart arrays of pressure sensors. As in the case of artificial retinas, one problem to solve is the management of the huge amount of information that such arrays provide, especially if this information should be used by a central processing unit to implement some control algorithms. An approach to manage such information is to increment the signal processing performed close to the sensor in order to extract the useful information and reduce the errors caused by long wires. This paper proposes the use of voltage to frequency converters to implement a quite straightforward analog to digital conversion as front end interface to digital circuitry in a smart tactile sensor. The circuitry commonly implemented to read out the information from a piezoresistive tactile sensor can be modified to turn it into an array of voltage to frequency converters. This is carried out in this paper, where the feasibility of the idea is shown through simulations and its performance is discussed.

Early slip detection with a tactile sensor based on retina
R. Maldonado-López, F. Vidal-Verdú, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 53, no. 2-3, pp 97-108, 2007
SPRINGER    DOI: 10.1007/s10470-007-9059-3    ISSN: 0925-1030    » doi
[abstract]
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The array of pressure data provided by these devices can be treated with different image processing algorithms to extract miscellaneous information. However, as in the case of vision chips or artificial retinas, problems arise when the size of the array and the computational complexity increase. Having a look at the skin, the information collected by every mechanoreceptor is not sent to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks, as the case of slip detection with tactile sensors, which is demanding in computing requirements. Here we show some results from a tactile processor based on circuitry proposed for an artificial retina that has been modified to mimic the way the biological skin works.

Locust-Inspired Vision System On Chip Architecture for Collision Detection in Automotive Applications
L. Carranza-González, R. Laviana-Gonzalez, S. Vargas-Sierra, J. Cuadri-Carvajo, G. Liñan-Cembrano and E. Roca-Moreno
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2006
[abstract]
Abstract not available

Tactile retina for slip detection
R. Maldonado López, F. Vidal-Verdú, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference - IEEE International Conference on Virtual Environments, Human-Computer Interfaces and Measurement Systems VECIMS 2006
[abstract]
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The array of pressure data provided by these devices can be treated with different image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look at the skin, the information collected by every mechanoreceptor is not sent to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. Something similar happens in the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results illustrated for the case of slip detection, which is certainly demanding in computing requirements. © 2006 IEEE.

Locust-inspired vision system on chip architecture for collision detection in automotive applications
L. Carranza, R. Laviana, S. Vargas, J. Cuadri, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference - International Symposium on Circuits and Systems ISCAS 2006
[abstract]
This paper describes a programmable digital computing architecture dedicated to process information in accordance to the organization and operating principles of the four-layer neuron structure encountered at the visual system of Locusts. This architecture takes advantage of the natural collision detection skills of locusts and is capable of processing images and ascertaining collision threats in real-time automotive scenaRíos. In addition to the Locust features, the architecture embeds a Topological Feature Estimator module to identify and classify objects in collision course.

A bioinspired collision detection algorithm for VLSI implementation
J. Cuadri, G. Liñán, R. Stafford, M.S. Keil and E. Roca
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne(1,2). The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenaRío, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenaRío. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.

ACE16k based stand-alone system for real-time pre-processing tasks
L. Carranza, F. Jiménez Garrido, G. Liñán-Cembrano, E. Roca, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.

Macromodelling for analog design and robustness boosting in bio-inspired computing models
J. Cuadri, G. Liñán and A. Rodríguez-Vázquez
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
DOI: 10.1117/12.608830    » doi
[abstract]
Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads to a netlist of more than 100.000 nodes for a small array of 100x150 pixels. Moreover, introducing an optical input in the low level simulation is nowadays not feasible with standard electrical simulation environments. Given that, to accomplish the task of integrating those systems in silicon to build compact, low power consuming, and reliable systems, a previous step in the standard analog electronic design flux should be introduced. Here a methodology to make the translation from the biological model to circuit-level specifications for electronic design is proposed. The purpose is to include non ideal effects as mismatching, noise, leakages, supply degradation, feedthrough, and temperature of operation in a high level description of the implementation, in order to accomplish behavioural simulations that require less computational effort and resources. A particular case study is presented, the analog electronic implementation of the locust's Lobula Giant Movement Detector (LGMD), a neural structure that fires a collision alarm based on visual information. The final goal is a collision threat detection vision system on-chip for automotive applications.

A bioinspired vision chip architecture for collision detection in automotive applications
R. Laviana, L. Carranza, S. Vargas, G. Liñán and E. Roca
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
This paper describes the architecture and retino-topic unit of a bio-inspired vision chip intended for automotive applications. The chip contains an array of 100 x 150 sensors which are able to capture high dynamic range (HDR) images, with a programmable compressive characteristic. The chip also incorporates a mechanism for adaptation of the global exposition time to the average illumination conditions. Average values are evaluated over image areas which are programmable by the user. In addition to the HDR pixel, every retino-topic unit in the array incorporates digital memory for three 6-bit pixel values (18-bits), as required for the implementation of a bionspired computing model for collisions detection which has been developed in the framework of a multidisciplinary European research project. All processing steps are executed off-chip, though we are currently working in the design of tiny digital processors (one per column) which will allow for running the whole model on-chip in a future version of this prototype. The chip has been designed in a 0.3 5 mu m 2P-4M technology and maintains its correct operation in extreme temperature conditions (from -40 degrees C to 110 degrees C).

Tactile on-chip pre-processing with techniques from artificial retinas
R. Maldonado-López, F. Vidal-Verdú, G. Liñán, E. Roca and A. Rodríguez-Vázquez
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide can be managed with many image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look to the skin, the information collected by every mechanoreceptor is not carried to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. This is also the behavior of the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results when it faces the detection of the slip, which involves fast real-time processing.

ACE16k-Ds: un Sistema autónomo programable para el preprocesamiento de imágenes en tiempo real
L. Carranza-González, F.J. Jimenez-Garrido, G. Liñán-Cembrano, E. Roca-Moreno, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference - Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2004
[abstract]
Este artículo describe un sistema electrónico autónomo y programable, denominado ACE16k-DS, que permite sensar y procesar imágenes en tiempo real. La arquitectura del sistema está basada en el chip ACE16k y en la FPGA Xc4028xl de Xilinx en la que se han sintetizado una Unidad de Control Programable de propósito específico y un generador de vídeo digital. Las imágenes son sensadas y procesadas, en modo analógico, en el chip ACE16k, siguiendo instrucciones secuenciadas por la Unidad de Control Programable. El generador de vídeo digital permite visualizar, en una pantalla TFT, las imágenes procesadas en tiempo real.

CMOS mixed-signal flexible vision chips
G. Liñán-Cembrano, L. Carranza-González, S. Espejo-Meana, R. Domínguez-Castro and A. Rodríguez-Vázquez
Book Chapter - Smart Adaptive Systems on Silicon, pp 103-118, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_7    ISBN: 978-1-4757-1051-9    » doi
[abstract]
Today, with 0.18μm technologies fully mature for mixed-signal design, CMOS compatible optical sensors available, and with 0.09μm knocking at the door of designers, we have the pieces to confront the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last years towards the realization of Vision Systems on Chips. Such VSoCs are targeted to integrate in a semiconductor substrate the functions of sensing, image processing in space and time, high-level processing and control of actuators. Based on newest discoveries of neurobiologists about the behavior of mammalian retinas, a new generation of flexible mixed-signal vision chips has been created which feature better Speed vs. Power figures than DSP-based systems. These devices are true mixed-signal microprocessors including standard digital I/O, embedded image and program memories. This chapter presents some concepts related to the architectures, circuits and methodologies associated to the design of these chips. Due to space limitations, and for the sake of illustrating different topics related to the design of such a kind of vision chips we will concentrate on the series of ACE devices developed by our group since 1996, referring the interested reader to some of the references at the end of the chapter.

A 1000 FPS@128x128 vision processor with 8-bit digitized I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference - European Solid-State Circuits Conference ESSCIRC 2004
[abstract]
This paper presents a mixed-signal programmable, chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-mum fully digital CMOS technology, contains similar to 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm(2) and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be: programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions - applications using exposures of about 50 mus have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory) and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

ACE16k: The third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs
A. Rodríguez-Vázquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro and S. Espejo-Meana
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 851-863, 2004
IEEE    DOI: 10.1109/TCSI.2004.827621    ISSN: 1057-7122    » doi
[abstract]
Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm(2) and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3 x 3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

ACE16k: a 128x128 focal plane analog processor with digital I/O
G.L. Cembrano, A. Rodríguez-Vázquez, S. Espejo Meana and R. Domínguez-Castro
Journal Paper - International Journal of Neural Systems, vol. 13, no. 6, pp 427-434, 2003
WORLD SCIENTIFIC PUBLISHING    DOI: 10.1142/S0129065703001765    ISSN: 0129-0657    » doi
[abstract]
This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.

An improved elementary processing unit for high-density CNN-based mixed-signal microprocessors for vision
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - Journal of Circuits, Systems and Computers, vol. 12, no. 6, pp 675-690, 2003
WORLD SCIENTIFIC PUBLISHING    DOI: 10.1142/S0218126603001100    ISSN: 0218-1266    » doi
[abstract]
This paper presents the architecture of the (E) under bar lementary (P) under bar rocessing (U) under bar nit - EPU which has been employed to design a CNN-Based 128 x 128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3 x 3 convolution masks,1 or information propagative CNN templates.(2) Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128 x 128 EPUs and a completely digital interface, in a standard fully-digital 0.35 mum CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm(2) and 100 GOP/J.

A modem in CMOS technology for data communication on the low-voltage power line
O. Guerra, C.M. Domínguez-Matas, S. Escalera, J.M. García-González, G. Liñán, R. del Río, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper - Integration, the VLSI Journal, vol. 36, no. 4, pp 229-236, 2003
ELSEVIER    DOI: 10.1016/j.vlsi.2003.09.007    ISSN: 0167-9260    » doi
[abstract]
This paper presents a CMOS 0.8 mum mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line. It includes all the analog circuitry needed for input interfacing and modulation/ demodulation (low-noise amplifier, PLL-based frequency synthesis, tunable filter banks, and decision circuitry), logic circuitry for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283muV(rms) (these are worst case values among 30 randomly-selected samples used as vehicles for detailed electrical characterization; most of the samples featured 200 muV(rms), sensitivity; bit error rate (BER) is below 0.5 x 10(-5)) at 10 kbps, and operates correctly in the whole industrial temperature range, from -45degreesC to 80degreesC, under 5% variations of the 5V supply voltage. This ASIC is now in commercial production. (C)2003 Published by Elsevier B.V.

Analog weight buffering strategy for CNN chips
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Carmona, S. Espejo and R. Domínguez Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, accuracy is ultimately limited by the controlling signals. This paper presents a buffering strategy intended to achieve 8-bit equivalent accuracy in the distribution of the internal analog signals, as employed in the chips ACE4k [1], ACE16k [2], and CACE1k [3].

A versatile sensor interface for programmable vision systems-on-chip
A. Rodríguez-Vázquez, G. Liñán, E. Roca, S. Espejo and R. Dominguez-Castro
Conference - Conf. on Sensors and Camera Systems for Scientific, Industrial, and Digital Photography 2003
[abstract]
This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35mum n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 x 128 identical cells, each cell corresponding to a pixel. Die size is 11.885 x 12.230mm(2) and cell size is 75.7mum x 73.3mum. Each cell contains 198 transistors dedicated to functions like processing, storage, and sensing. The system is oriented to real-time, single-chip image acquisition and processing. Since each pixel performs the basic functions of sensing, processing and storage, data transferences are fully parallel (image-wide). The programmability of the processing functions enables the realization of complex image processing functions based on the sequential application of simpler operations. This paper provides a general overview of the system architecture and functionality, with special emphasis on the optical interface.

A mixed-signal early vision chip with embedded image and programming memories and digital I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Domiguez-Castro and S. Espejo
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35mum standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

Mismatch-induced trade-offs and scalability of analog preprocessing visual microprocessor chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range. The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenaRíos, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.

Diseño de chips programables de señal mixta con bajo consumo de potencia para sistemas de vision en tiempo real
G. Liñán-Cembrano
Thesis - Date of defense: 28/06/2002
UNIVERSIDAD DE SEVILLA, IMSE-CNM    » link
[abstract]
Esta Tesis presenta distitnas contribuciones relacionadas con el diseño de chips de señal-mixta programables, reconfigurables y flexibles para procesar imágenes en el plano focal. Estos chips están concebidos para lo que se conoce como tratamiento de imágenes a bajo nivel, llamado también 'early-visión', tratamiento que es parte muy importante en el proceso de interpretación de la información visual puesto que permite reducir enormemente la cantidad de información a transmitir a las estapas posteriores del flujo de procesamiento, etapas encargadas de la interpretación de la señal visual.
Las principales características novedosas de los chips desarrollados en esta Tesis radican en cuatro puntos: primero en el uso de circuitos analógicos altamente optimizados para las tareas de procesamiento en sí, lo que permite conseguir densidades de integración (y por tanto resoluciones espaciales) altas, y velocidades de operación muy altas en relación con la potencia eléctrica consumida; segundo, en el uso de interfaces de control y de entrada/salida de datos totalmente digitales, lo que hace posible la interconexión de estos chips dentro de sistemas completos de percepción-actuación que incluyan procesadores digitales; tercero, en la integración conjunta, sobre el mismo substrato semiconductor, de los planos sensor y procesador; cuarto, en la incorporación de estructuras de programación y reconfiguración optimizadas que confieren a los circuitos diseñados las características propias de un microprocesador visual.

A processing element architecture for high-density focal plane analog programmable array processors
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
The architecture of the elementary Processing Element - PE- used in a recently designed 128x128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 x 3 convolution masks. The vision chip has been implemented in a standard 0.35mum CMOS technology. The main PE related figures are: 180 cells/mm(2), 18 MOPS/cell; and 180 muW/cell.

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper explores different trade-offs associated to the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of processors), as fabrication technologies scale down into deep sub-micron.

CE16K: A 128x128 focal plane analog processor with digital I/O.
G. Liñán, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
This paper presents a new generation 128x128 Focal-Plane. Analog Programmable Array Processor FPAPAP-, from a system level perspective, which has been manufactured in a 0.35mum standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy -8b-requirements of most real time -early-vision processing applications. It is easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 90% of them working in analog mode, and exhibits a relatively low power consumption -<4W, i.e. less than 1muW per transistor. Computing vs. power peak values are in the order of 1TeraOPS/W, while maintained VGA processing throughputs of 100Frames/s are possible with about 10-20 basic image processing tasks on each frame.

A multimode gray-scale CMOS optical sensor for Visual computers
G. Liñán, A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro and E. Roca
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as well as the mechanism for transducing the photogenerated charges into the correspondent pixel voltage. Both linear or logarithmic compression acquisition modes are available. This makes the sensor very suitable to be used in very different illumination conditions.

Architectural and basic circuit considerations for a flexible 128x128 mixed-signal SIMD vision chip
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 179-190, 2002
SPRINGER    ISSN: 0925-1030    
[abstract]
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 mum standard digital IP-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10-20 basic image processing tasks on each frame.

ACE4k: An analog I/O 64 x 64 visual microprocessor chip with 7-bit analog accuracy
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 30, no. 2-3, pp 89-116, 2002
JOHN WILEY & SONS    DOI: 10.1002/cta.191    ISSN: 0098-9886    » doi
[abstract]
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 mum standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time ( < 300 ns for linear convolutions) and using a low power budget ( < 1.2 W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with > 7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templatesigma-either directly or through template decomposition. This means the 100% of the 3 x 3 linear templates reported in Roska et al. 1998, [1]. Copyright (C) 2002 John Wiley Sons, Ltd.

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