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Author: Darie, Angela A.
Year: Since 2002
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TOF estimation based on compressed real-time histogram builder for SPAD image sensors
I. Vornicu, A. Darie, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
[abstract]
This paper presents a FPGA implementation of a novel depth map estimation algorithm for direct time-of-flight CMOS image sensors (dToF-CISs) based on single-photon avalanche-diodes (SPADs). Conventional ToF computation algorithms rely on complete ToF histograms. The next generation of high speed dToF-CIS is expected to have wide dynamic range and high depth resolution. Applications such as 3D imaging based on dToF-CISs require pixel-level ToF histograms which have to be stored by huge fully-random access memory (RAM) modules. The proposed shifted inter-frame histogram (SiFH) algorithm has the same accuracy but requires a memory footprint 128 times smaller than the conventional algorithm. Thus a much larger number of pixels can be resolved using limited block RAM resources of FPGAs. Moreover the overall frame rate is also remarkably improved compared to the scanning method. The proof of concept of the SiFH algorithm on 15 bits has been implemented on Spartan-3E. An automated testbench was developed to confirm that no ambiguity errors occur along the entire dynamic range.

Compact Real-Time Inter-Frame Histogram Builder for 15Bits High-Speed ToF-Imagers based on Single-Photon Detection
I. Vornicu, A. Darie, R. Carmona-Galan and A. Rodriguez-Vazquez
Journal Paper - IEEE Sensors Journal, vol. 19, no. 6, pp 2181-2190, 2019
IEEE    DOI: 10.1109/JSEN.2018.2885960    ISSN: 1530-437X    » doi
[abstract]
Time-of-flight image sensors based on single-photon detection, i.e. SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for ToF computation. This method makes use of the shifted inter-frame histogram (SifH). It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 28 words memory is enough to process histograms containing up to 215 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodríguez-Pérez, A. Darie, A. Rodríguez-Vázquez, C. Soto-Sánchez and E. Fernández-Jover
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an autocalibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data stream coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
M. Delgado-Restituto, A. Rodriguez-Perez, A. Darie, C. Soto-Sánchez, E. Fernandez-Jover and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 2, pp 420-433, 2017
IEEE    DOI: 10.1109/TBCAS.2016.2618319    ISSN: 1932-4545    » doi
[abstract]
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

A 64-channel ultra-low power system-on-chip for local field and action potentials recording
A. Rodríguez-Pérez, M. Delgado-Restituto, A. Darie, C. Soto-Sánchez, E. Fernández-Jover and Á. Rodríguez-Vázquez
Conference - SPIE Micro Technologies, 2015
[abstract]
This paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other,feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330μW.

A 330μW, 64-Channel Neural Recording Sensor with Embedded Spike Feature Extraction and Auto-calibration
A. Rodríguez-Pérez, M. Delgado-Restituto, A. Darie, C. Soto-Sánchez, E. Fernández-Jover and Á. Rodríguez-Vázquez
Conference - IEEE Asian Solid-State Circuits Conference A-SSCC 2014
[abstract]
This paper reports a 64-channel neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results show that the power consumption of the complete system is 330μW.

In vivo measurements with a 64-channel extracellular neural recording integrated circuit
M. Delgado-Restituto, A. Rodríguez-Pérez, A.A. Darie, Á. Rodríguez-Vázquez, C. Soto-Sánchez and E. Fernández-Jover
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2014
[abstract]
This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific Integrated Circuit (ASIC) developed at IMSE and gives details of the computer interface used for real-time data acquisition. This interface connects the ASIC to a conventional 2.0 USB port by means of a Field Programmable Gate Array (FPGA). Communications are bidirectional and employ custom protocols both for delivering commands to the ASIC and for recording neural information under different channel selection and operation modes. The link is controlled by a user-friendly programming interface written in C++ which includes a built-in routine to efficiently index and store the captured data. Mesurements demonstrate the suitability of the ASIC for capturing local field and action potentials with two different microelectrode array platforms.

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