Spanish National Research Council · University of Seville
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Author: Sarazá Canflanca, Pablo
Year: Since 2002
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TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V.Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2019
[abstract]
Time-Dependent Variability has attracted increasing interest in the last years. In particular, phenomena such as Bias Temperature Instability, Hot Carrier Injection and Random Telegraph Noise can have a large impact on circuit reliability, and must be therefore characterized and modeled. For technologies in the nanometer range, these phenomena reveal a stochastic behavior and must be characterized in a massive manner, with enormous amounts of data being generated in each measurement. In this work, a novel tool with a user-friendly interface, which allows the robust and fullyautomated parameter extraction for RTN, BTI and HCI experiments, is presented.

A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors
P. Saraza-Canflanca, J. Martin-Martinez, R. Castro-Lopez, E. Roca, R. Rodriguez, M. Nafria and F.V. Fernandez
Journal Paper - Microelectronic Engineering, vol. 215, article 111004, 2019
ELSEVIER    DOI: 10.1016/j.mee.2019.111004    ISSN: 0167-9317    » doi
[abstract]
Random Telegraph Noise (RTN) has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which can cause performance degradation in circuits. In this work, the dependence of RTN parameters, namely current jump amplitude and emission and capture time constants, on the bias conditions, both VG and VD, has been studied on a set of devices, with a high granularity in a broad voltage range. The results obtained for the VG dependences corroborate previous works, but suggest a unique trend for all the devices in a VG range that goes from the near-threshold region up to voltages over the nominal operation bias. However, different trends have been observed in the parameters dependence for the case of VD. From the experimental data, the probabilities of occupation of the associated defects have been evaluated, pointing out large device-to-device dispersion in the VD dependences.

Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A. Toro-Frias, P. Saraza-Canflanca, F. Passos, P. Martin-Lloret, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Design Automation and Test in Europe DATE 2019
[abstract]
Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and timeefficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability.

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
P. Saraza-Canflanca, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria, F.V. Fernandez
Conference - Design Automation and Test in Europe DATE 2019
[abstract]
Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometerscale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

A new time efficient methodology for the massive characterization of RTN in CMOS devices
G. Pedreira, J. Martin-Martinez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodriguez, R. Castro-Lopez, E. Roca, F.V. Fernandez and M. Nafria
Conference - IEEE International Reliability Physics Symposium IRPS 2019
[abstract]
Abstract not avaliable

Flexible Setup for the Measurement of CMOS Time-Dependent Variability with Array-Based Integrated Circuits
J. Diaz-Fortuny, P. Saraza-Canflanca, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, F.V. Fernandez and M. Nafria
Journal Paper - IEEE Transactions on Instrumentation and Measurement, first online, 2019
IEEE    DOI: 10.1109/TIM.2019.2906415    ISSN: 0018-9456    » doi
[abstract]
This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P. Saraza-Canflanca, D. Malagon, F. Passos, A. Toro, J. Nuñez, J. Diaz-Fortuny, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.

A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation
J. Diaz-Fortuny, P. Saraza-Canflanca, A. Toro-Frias, R. Castro-Lopez, J. Martin-Martinez, E. Roca, R. Rodriguez, F.V. Fernandez and M. Nafria
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by timedependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of aging device effects for reliability circuit

Automated massive RTN characterization using a transistor array chip
P. Saraza-Canflanca, J. Diaz-Fortuny, A. Toro-Frias, R. Castro-Lopez, E. Roca, J. Martin-Martinez, R. Rodriguez, M. Nafria and F.V. Fernandez
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2018
[abstract]
In this work, a CMOS transistor array for the massive measurement of random telegraph noise (RTN), together with a dedicated experimental setup, is presented. The array chip, called ENDURANCE, allows the massive characterization of the RTN parameters needed for a complete understanding of the phenomenon. Additionally, some experimental results are presented that demonstrate the convenience of the setup.

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