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Author: Domínguez Castro, Rafael
Year: Since 2002
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Design Considerations for A Low-Noise CMOS Image Sensor
A. González-Márquez, A. Charlet, A. Villegas, F. Jiménez-Garrido, F. Medeiro, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2015
[abstract]
This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.

High-speed global shutter CMOS machine vision sensor with high dynamic range image acquisition and embedded intelligence
F. Jiménez-Garrido, J. Fernández-Pérez, C. Utrera, J.M. Muñoz, M.D. Pardo, A. Giulietti, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Conference - Sensors, Cameras, and Systems for Industrial and Scientific Applications XIII IMAGING 2012
[abstract]
High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, etc. Many of these applications call also for large spatial resolution, high sensitivity and the ability to detect images with large intra-frame dynamic range. This paper reports a CIS intelligent digital image sensor with 5.2Mpixels which delivers 12-bit fully-corrected images at 250Fps. The new sensor embeds on-chip digital processing circuitry for a large variety of functions including: windowing; pixel binning; sub-sampling; combined windowing-binning-subsampling modes; fixed-pattern noise correction; fine gain and offset control; color processing, etc. These and other CIS functions are programmable through a simple four-wire serial port interface.

A CMOS vision system on-chip with multicore sensory processing architecture for image analysis above 1,000F/s
A. Rodríguez-Vázquez, R. Domínguez-Castro, F. Jiménez-Garrido and S. Morillas
Conference - SPIE Sensors, Cameras, and Systems for Industrial/Scientific Applications XI, 2010
[abstract]
This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand's frame-per-second rate. The chip employs a distributed processing architecture with a pre-processing stage consisting of an array of programmable sensory-processing cells, and a post-processing stage consisting of a digital microprocessor. The pre-processing stage operates as a retina-like sensor front-end. It performs parallel processing of the images captured by the sensors which are embedded together with the processors. This early processing serves to extract image features relevant to the intended tasks. The front-end incorporates also smart read-out structures which are conceived to transmit only these relevant features, thus precluding full gray-scale frames to be coded and transmitted. The chip is capable to close action-reaction loops based on the analysis of visual flow at rates above 1,000F/s with power budget below 1W peak. Also, the incorporation of processors close to the sensors enables signal-dependent, local adaptation of the sensor gains and hence high-dynamic range signal acquisition.

Data Matrix Code Recognition using the Eye-RIS Vision System
A. Jimenez-Marrufo, A. Mendizabal, S. Morillas-Castillo, R. Dominguez-Castro, S. Espejo, R, Romay-Juarez and A. Rodriguez-Vazquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2007
[abstract]
This demo illustrates the processing capabilities of the Eye-RIS vision systems; specifically using the Eye-RIS v1.2. These systems employ an AnaFocus's a proprietary architecture where processing is realized in two steps. The first stage of the architecture embeds sensors, parallel processing analog and mixed-signal circuitry, control circuitry and memory. This front-stage is implemented through dedicated bio-inspired chips. The second stage of the Eye-RIS vision system architecture is a digital microprocessor. The combination of parallel preprocessing and serial post-processing makes the Eye-RIS systems very efficient particularly the Eye-RIS systems are capable to close the sensor-processing-actuation loop at a high speed. In this demo, the Eye-RIS v1.2 is used to recognize data matrix codes at more than 200 codes/sec rate.

CMOS mixed-signal flexible vision chips
G. Liñán-Cembrano, L. Carranza-González, S. Espejo-Meana, R. Domínguez-Castro and A. Rodríguez-Vázquez
Book Chapter - Smart Adaptive Systems on Silicon, pp 103-118, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_7    ISBN: 978-1-4757-1051-9    » doi
[abstract]
Today, with 0.18μm technologies fully mature for mixed-signal design, CMOS compatible optical sensors available, and with 0.09μm knocking at the door of designers, we have the pieces to confront the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last years towards the realization of Vision Systems on Chips. Such VSoCs are targeted to integrate in a semiconductor substrate the functions of sensing, image processing in space and time, high-level processing and control of actuators. Based on newest discoveries of neurobiologists about the behavior of mammalian retinas, a new generation of flexible mixed-signal vision chips has been created which feature better Speed vs. Power figures than DSP-based systems. These devices are true mixed-signal microprocessors including standard digital I/O, embedded image and program memories. This chapter presents some concepts related to the architectures, circuits and methodologies associated to the design of these chips. Due to space limitations, and for the sake of illustrating different topics related to the design of such a kind of vision chips we will concentrate on the series of ACE devices developed by our group since 1996, referring the interested reader to some of the references at the end of the chapter.

Vertebrate retina emulation using multi-layer array-processor mixed-signal chips
R. Carmona-Galán, A. Rodríguez-Vázquez, R. Domínguez-Castro and S. Espejo Meana
Book Chapter - Smart Adaptive Systems on Silicon, pp 85-101, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_6    ISBN: 978-1-4757-1051-9    » doi
[abstract]
A bio-inspired model for an analog programmable array processor (APAP), based on stu dies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented here.

A 1000 FPS@128x128 vision processor with 8-bit digitized I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference - European Solid-State Circuits Conference ESSCIRC 2004
[abstract]
This paper presents a mixed-signal programmable, chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-mum fully digital CMOS technology, contains similar to 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm(2) and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be: programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions - applications using exposures of about 50 mus have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory) and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

ACE16k: The third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs
A. Rodríguez-Vázquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro and S. Espejo-Meana
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 851-863, 2004
IEEE    DOI: 10.1109/TCSI.2004.827621    ISSN: 1057-7122    » doi
[abstract]
Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm(2) and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3 x 3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
R. Carmona-Galán, F. Jiménez-Garrido, C.M. Domínguez-Mata, R. Domínguez-Castro, S. Espejo-Meana, I. Petras and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 913-925, 2004
IEEE    DOI: 10.1109/TCSI.2004.827641    ISSN: 1057-7122    » doi
[abstract]
Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple, resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-mum CMOS technology.

Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
IEEE    DOI: 10.1109/TCSI.2003.821308    ISSN: 1057-7122    » doi
[abstract]
We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.

ACE16k: a 128x128 focal plane analog processor with digital I/O
G.L. Cembrano, A. Rodríguez-Vázquez, S. Espejo Meana and R. Domínguez-Castro
Journal Paper - International Journal of Neural Systems, vol. 13, no. 6, pp 427-434, 2003
WORLD SCIENTIFIC PUBLISHING    DOI: 10.1142/S0129065703001765    ISSN: 0129-0657    » doi
[abstract]
This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.

CMOS comparators
R. Domínguez-Castro, M. Delgado-Restituto, A. Rodríguez-Vázquez, J.M. de la Rosa and F. Medeiro
Book Chapter - CMOS Telecom Data Converters, pp 149-182, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_4    ISBN: 978-1-4419-5382-7    » doi
[abstract]
abstract not available

An improved elementary processing unit for high-density CNN-based mixed-signal microprocessors for vision
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - Journal of Circuits, Systems and Computers, vol. 12, no. 6, pp 675-690, 2003
WORLD SCIENTIFIC PUBLISHING    DOI: 10.1142/S0218126603001100    ISSN: 0218-1266    » doi
[abstract]
This paper presents the architecture of the (E) under bar lementary (P) under bar rocessing (U) under bar nit - EPU which has been employed to design a CNN-Based 128 x 128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3 x 3 convolution masks,1 or information propagative CNN templates.(2) Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128 x 128 EPUs and a completely digital interface, in a standard fully-digital 0.35 mum CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm(2) and 100 GOP/J.

Programmable retinal dynamics in a CMOS mixed-signal array processor chip
R. Carmona, F. Jiménez-Garrido, R. Domiguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - Conference on Bioengineered and Bioinspired Systems 2003
[abstract]
The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5mum CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 x 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.

Analog weight buffering strategy for CNN chips
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Carmona, S. Espejo and R. Domínguez Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, accuracy is ultimately limited by the controlling signals. This paper presents a buffering strategy intended to achieve 8-bit equivalent accuracy in the distribution of the internal analog signals, as employed in the chips ACE4k [1], ACE16k [2], and CACE1k [3].

A versatile sensor interface for programmable vision systems-on-chip
A. Rodríguez-Vázquez, G. Liñán, E. Roca, S. Espejo and R. Dominguez-Castro
Conference - Conf. on Sensors and Camera Systems for Scientific, Industrial, and Digital Photography 2003
[abstract]
This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35mum n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 x 128 identical cells, each cell corresponding to a pixel. Die size is 11.885 x 12.230mm(2) and cell size is 75.7mum x 73.3mum. Each cell contains 198 transistors dedicated to functions like processing, storage, and sensing. The system is oriented to real-time, single-chip image acquisition and processing. Since each pixel performs the basic functions of sensing, processing and storage, data transferences are fully parallel (image-wide). The programmability of the processing functions enables the realization of complex image processing functions based on the sequential application of simpler operations. This paper provides a general overview of the system architecture and functionality, with special emphasis on the optical interface.

A mixed-signal early vision chip with embedded image and programming memories and digital I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Domiguez-Castro and S. Espejo
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35mum standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

A bio-inspired two-layer mixed-signal flexible programmable chip for early vision
R.C. Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, T. Roska, C. Rekeczky, I. Petras and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1313-1336, 2003
IEEE    DOI: 10.1109/TNN.2003.816377    ISSN: 1045-9227    » doi
[abstract]
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the Visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 mum. CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.

Mismatch-induced trade-offs and scalability of analog preprocessing visual microprocessor chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range. The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenaRíos, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.

Ultra-high frame rate focal plane image sensor and processor
A. Zarándy, R. Domínguez-Castro and S. Espejo
Journal Paper - IEEE Sensors Journal, vol. 2, no. 6, pp 559-565, 2002
IEEE    DOI: 10.1109/JSEN.2002.806895    ISSN: 1530-437X    » doi
[abstract]
Application examples of a fully-programmable analogic focal plane array processor are introduced. One mixed-signal sensory/processing chip is presented, which is capable to capture, process, and evaluate over 10,000 images in a second. Morphological analysis of silhouettes and sparks were done and real-time decision making was performed running on this extraordinary high frame-rate. © 2002 IEEE.

A processing element architecture for high-density focal plane analog programmable array processors
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
The architecture of the elementary Processing Element - PE- used in a recently designed 128x128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 x 3 convolution masks. The vision chip has been implemented in a standard 0.35mum CMOS technology. The main PE related figures are: 180 cells/mm(2), 18 MOPS/cell; and 180 muW/cell.

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper explores different trade-offs associated to the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of processors), as fabrication technologies scale down into deep sub-micron.

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5mum CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper.

Bio-inspired analog VLSI design realizes programmable complex spatio-temporal dynamics on a single chip
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2002
[abstract]
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed in 0.5 mum CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper.

CE16K: A 128x128 focal plane analog processor with digital I/O.
G. Liñán, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
This paper presents a new generation 128x128 Focal-Plane. Analog Programmable Array Processor FPAPAP-, from a system level perspective, which has been manufactured in a 0.35mum standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy -8b-requirements of most real time -early-vision processing applications. It is easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 90% of them working in analog mode, and exhibits a relatively low power consumption -<4W, i.e. less than 1muW per transistor. Computing vs. power peak values are in the order of 1TeraOPS/W, while maintained VGA processing throughputs of 100Frames/s are possible with about 10-20 basic image processing tasks on each frame.

CMOS realization of a 2-layer CNN universal machine chip
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the possibilities of these complex spatio-temporal dynamics in image processing, a prototype chip has been developed implementing this CNN model with analog signal processing blocks. This chip has been designed in a 0.5 mum CMOS technology. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper(a).

A multimode gray-scale CMOS optical sensor for Visual computers
G. Liñán, A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro and E. Roca
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as well as the mechanism for transducing the photogenerated charges into the correspondent pixel voltage. Both linear or logarithmic compression acquisition modes are available. This makes the sensor very suitable to be used in very different illumination conditions.

Architectural and basic circuit considerations for a flexible 128x128 mixed-signal SIMD vision chip
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 179-190, 2002
SPRINGER    ISSN: 0925-1030    
[abstract]
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 mum standard digital IP-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10-20 basic image processing tasks on each frame.

ACE4k: An analog I/O 64 x 64 visual microprocessor chip with 7-bit analog accuracy
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 30, no. 2-3, pp 89-116, 2002
JOHN WILEY & SONS    DOI: 10.1002/cta.191    ISSN: 0098-9886    » doi
[abstract]
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 mum standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time ( < 300 ns for linear convolutions) and using a low power budget ( < 1.2 W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with > 7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templatesigma-either directly or through template decomposition. This means the 100% of the 3 x 3 linear templates reported in Roska et al. 1998, [1]. Copyright (C) 2002 John Wiley Sons, Ltd.

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