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Author: Espejo Meana, Servando
Year: Since 2002
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SIS20: A CMOS ASIC for Solar Irradiance Sensors in Mars Surface
D. Vázquez, J. Ceballos and S. Espejo
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
[abstract]
This paper reports the design and characterization of the ASIC SIS20, planned for an instrument aimed to measure Solar Irradiance on the surface of Mars. It has been designed using the AMS0.35u CMOS technology and with the rad-hard digital library developed at IMSE (Spain). The ASIC is intended for flying with the ExoMars2020 mission.

Characterization, Screening and Qualification of the MEDA Wind-Sensor ASIC
S. Espejo, J. Ceballos, A. Ragel, L. Carranza, J.M. Mora, M.A. Lagos, J. Ramos, S. Sordo, E. Cordero and D. López
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2018
[abstract]
The paper describes the final characterization results of the MEDA-WS ASIC, which was described in a previous paper in AMICSA-2016. It describes as well the qualification and the screening processes that have been carried out, and the present status of its integration and calibration in the final engineering and flying modules of the wind-sensor instrument.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutierrez and M.A. Lagos-Florido
Journal Paper - IEEE Transactions on Nuclear Science, vol. 63, no. 4, pp. 2379-2389, 2016
IEEE    DOI: 10.1109/TNS.2016.2586140    ISSN: 0018-9499    » doi
[abstract]
This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35 μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz,A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Journal Paper - IEEE Transactions on Magnetics, vo. 51, no. 1, article 4001804, 2015
IEEE    DOI: 10.1109/TMAG.2014.2356976    ISSN: 0018-9464    » doi
[abstract]
This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D magnetometer for space applications, with a significant reduction in mass and volume while maintaining a high sensitivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances and a rad-hard mixed-signal ASIC designed in a standard 0.35 μm CMOS technology. The ASIC performs sensor-signal conditioning and analogue-to-digital conversion, and handles calibration tasks, system configuration, and communication with the outside. The proposed system provides high sensitivity to low magnetic fields, down to 3 nT, while offering a small and reliable solution under extreme environmental conditions in terms of radiation and temperature.

Four-channel self-compensating single-slope ADC for space environments
S. Sordo-Ibáñez, S. Espejo-Meana, B. Piñero-García, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez, M.A. Lagos-Florido and J. Ramos-Martos
Journal Paper - Electronics Letters, vol. 50, no.8, pp 579-581, 2014
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el.2014.0664    ISSN: 0013-5194    » doi
[abstract]
A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates for process, voltage and temperature variations, as well as for radiation effects, in order to be used in extreme environmental conditions. The design combines an efficient implementation by using a feedback loop that ensures an inherently monotonic and very accurate ramp generation, with high levels of configurability in terms of resolution and conversion rate, as well as input voltage range. The SS ADC was designed in a standard 0.35 μm CMOS technology. Experimental measurements of the performance and stability against radiation and temperature are presented to verify the proposed approach.

A Front-End ASIC for a 3-D Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - European Conference on Magnetic Sensors and Actuators EMSA 2014
[abstract]
Abstract not avaliable

A Rad-Hard Multichannel Front-End Readout ASIC for Space Applications
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - IEEE International Workshop on Metrology for Aerospace METROAEROSPACE 2014
[abstract]
This paper presents a single-chip solution for sensor-signals conditioning and digitalization in space applications. The rad-hard ASIC implements a set of 6 generic instrumentation channels that are highly configurable in terms of resolution, conversion rate, and input voltage range, providing a flexible solution for space applications requiring the digital acquisition of slow input signals with medium-to-high resolutions. The resolution can be configured between 12 bits at 19.6 kS/s and 16 bits at 2.6 kS/s. The differential input voltage range can be extended up to 4 Vpp. The instrumentation channels combine a programmable-gain, high input impedance instrumentation amplifier and dual-slope analog-to-digital converters with radiation hardening by design (RHBD) techniques in a standard 0.35 μm CMOS technology. Experimental results demonstrate the performance of the ASIC across an operating temperature range of -90 ºC to +125 ºC and its robustness against radiation effects up to 318 krad of TID, absence of latch-up up to at least 81.8 MeV·cm2/mg, and a SEUs LETth of 22.5 MeV·cm2/mg.

SEE Characterization of a Magnetometer Front-End ASIC using a RHBD Digital Library in AMS 0.35μm CMOS
J. Ramos-Martos, A. Arias-Drake, L. Carranza-González, S. Sordo-Ibáñez, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, S. Espejo-Meana and M.A. Lagos-Florido
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2014
[abstract]
A radiation-hardened-by-design (RHBD) digital library, developed for the Austria Microsystems (AMS) 0.35μm CMOS technology has been applied in a mixedsignal ASIC that operates as a multi-channel data acquisition system for magnetometers using anisotropic magnetoresistances (AMR). The circuit has been tested in the Heavy-Ion facilities of the Université Catholique de Louvain-la-Neuve (HIF-UCL). The experimental results demonstrate a LET threshold of 22.5 MeV·cm2/mg and absence of latchup up to 81.8 MeV·cm2/mg. This radiation-tolerant performance is obtained at the cost of a penalty in area and power with respect to the unhardened technology.

An Adaptive Approach to On-Chip CMOS Ramp Generation for High Resolution Single-Slope ADCs
S. Sordo-Ibanez, B. Piñero-García, S. Espejo-Meana, A. Ragel-Morales, J. Ceballos-Cáceres, M. Muñoz-Díaz, L. Carranza-González, A. Arias-Drake, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - European Conference on Circuit Theory and Design ECCTD 2013
[abstract]
Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.

SEE Characterization of the AMS 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, J.M. Mora-Gutiérrez, M. Muñoz-Díaz, A. Ragel-Morales, B. Piñero-García, J. Ceballos-Cáceres, L. Carranza-González, S. Sordo-Ibáñez, M.A. Lagos-Florido and S. Espejo-Meana
Conference - European Conference on Radiation and Its Effects on Components and Systems RADECS 2013
[abstract]
This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 ΣΔm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a RHBD digital library.

Design Methodology and Development of Mixed-Signal ASICs for Space Applications in Standard CMOS Technology
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2013
[abstract]
The design of mixed-signal ASICs for on-board space applications can provide several advantages that would not otherwise be possible with discrete components. However, extreme environmental conditions in terms of radiation and temperature imply a detailed knowledge of the technology used while CMOS commercial foundries do not usually have or make available these data. The aim of this work is to overcome these obstacles and offer solutions for space applications based on mixed-signal ASICs in commercial CMOS technologies. This paper presents the methodology followed for the assessment of a commercial (Austria Microsystems, AMS) 0.35 µm CMOS technology and for the development of a radiation hardened by design (RHBD) digital library. In addition, the described methodology has been applied to the development of two mixed-signal ASICs. The first chip performs the function of an optical digital transceiver for diffused-light intra-satellite optical communications. The second one implements a front-end solution for sensor data acquisition and signal conditioning and consists in a set of configurable multi-mode dual slope ADCs with resolution up to 16 bits.

A Front-End ASIC for a 16-Bit Three-Axis Magnetometer for Space Applications Based on Anisotropic Magnetoresistors
S. Sordo-Ibáñez, B. Piñero-García, M. Muñoz-Díaz, A. Ragel-Morales, J. Ceballos-Cáceres, L. Carranza-González, S. Espejo-Meana, A. Arias-Drake, J. Ramos-Martos, J.M. Mora-Gutiérrez and M.A. Lagos-Florido
Conference - Conference on the Design of Circuits and Integrated Systems DCIS 2013
[abstract]
Many space applications require the measurement of magnetic fields. This includes many scientific and meteorological instruments, as well as satellite attitude control systems. The most widely used method for measuring magnetic fields in space missions has been the use of fluxgate sensors, mainly due to their reliability, robustness and relatively small mass and volume with respect to the total size of the satellite. However, the current trends of cost reduction and standardization in aerospace technology tends towards the design of small satellites, commonly called nano-satellites or even picosatellites, embodying a new challenge in the design of low-cost space instrumentation. In this scope, fluxgate sensors are massy and large enough so that their use is not addressable for these small satellites. This paper presents an alternative design of a three-axis magnetometer for the measurement of the strength and direction of an incident magnetic field in space applications, with a significant reduction in mass and volume while maintaining a high detectivity. The proposed system uses magnetic field sensors based on anisotropic magnetoresistances (AMR) and a radiation hardened by design (RHBD) mixed-signal ASIC that performs signal conditioning and analog to digital conversion up to 16 bits, and also handles calibration tasks, system configuration and communication with the outside. The use of an ASIC instead of discrete components reduces both weight and volume, and achieves improvements in performance and consumption. The proposed magnetometer provides high sensitivy to low magnetic fields up to 30 μG of resolution while offering a small, low cost and reliable solution for space applications.

OWLS: A Mixed-Signal Asic for Optical Wire-Less Links in Space Instruments
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, M.A. Lagos-Florido, S. Sordo-Ibáñez, S. Espejo-Meana, I. Arruego, J. Martínez-Oter and M.T. Álvarez
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2012
[abstract]
This paper describes the design of a mixed-signal ASIC for space application and the techniques employed for radiation hardening and temperature effects compensation. The work is part of a planned long-term effort and collaboration between "Instituto de Microelectrónica de Sevilla (IMSE)", "Universidad de Sevilla (US)", and "Instituto Nacional de Técnica Aeroespacial (INTA)" aimed to consolidate a group of experienced mixed-signal space-ASIC designers.

Evaluation of the AMS 0.35μm CMOS Technology for use in Space Applications
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero-García, M. Muñoz-Díaz, M.A. Lagos-Florido, S. Sordo-Ibáñez and S. Espejo-Meana
Conference - Int. Workshop on Analogue and Mixed Signal Integrated Circuits For Space Applications AMICSA 2012
[abstract]
The design of mixed-signal application specific integrated circuits (ASICs) requires a detailed knowledge of the behavior of the technology which exceeds the needs of digital designs. For space applications, with its extended-temperature and radiation environment, the job of the mixed-signal designer is made even more difficult as in most cases commercial foundries do not have or make available data on the behavior of their devices under those nonstandard conditions.

Radiation Characterization of the austriamicrosystems 0.35 μm CMOS Technology
J. Ramos-Martos, A. Arias-Drake, A. Ragel-Morales, J. Ceballos-Cáceres, J.M. Mora-Gutiérrez, B. Piñero.García, M. Muñoz-Díaz, M.A. Lagos-Florido and S. Espejo-Meana
Conference - Conference on Radiation Effects on Components and Systems RADECS 2011
[abstract]
The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica de Sevilla and Universidad de Sevilla (IMSE-USE) have started a long term collaboration with the Spanish Instituto Nacional de Técnica Aeroespacial (INTA) to extend its experience on mixed-signal design to the field of ASICs for space applications. The assessment of a commercial (austriamicrosystems) 0.35 μm CMOS technology is a first step towards the development of a mixed-signal design methodology, including an RHBD digital library suitable for use in space conditions.

Image processing for surface quality control in stainless steel production lines
C. Spinola, J.M. Cañero-Nieto, M.J. Martín-Vázquez, J.M. Bonelo, F. GarcÍa-Vacas, G. Moreno-Aranda, S. Espejo, G. Hylander and J. Vizoso
Conference - IEEE International Conference on Imaging Systems and Techniques IST 2010
[abstract]
In this paper we present an image processing algorithm to detect and measure the amount of residual oxide remaining on the surface of stainless steel coils for quality control in a production line. This algorithm processes in real time the images taken by the acquisition system which we have designed for this purpose and which has been installed in the finish line of a stainless steel production factory. We present here a more robust and reliable algorithm than the initial one, which has been adapted to deal with non-ideal conditions such as non-perfect homogeneous lighting, different surface finish, water marks, etc., which usually occur in practice. © 2010 IEEE.

Residual oxides detection and measurement in stainless steel production lines
C.G. Spinola, J.M. Bonelo, J.M. Cañero, S. Espejo, S. Morilla, R.M. Luque, M.J. Martín-Vazquez, F. GarcÍa-Vacas, C. Gálvez-Fernández, J. Vizoso and J. Muñoz-Pérez
Conference - IEEE International Conference on Computational Intelligence for Measurement Systems and Applications CIMSA 2009
[abstract]
In this paper, we present a system to detect and measure the amount of residual oxide stains remaining in the surface of stainless steel coils after the pickling process in a production line. The system is able to acquire clear images of the stainless steel surface with the appropriate illumination and magnification, while it is being produced. These images are processed and analyzed in real time in order to detect and measure the oxide stains which typically are between 50 and 200 microns in size. We present here an outline of the acquisition system and the image processing algorithm which has been designed to detect this sort of defect. © 2009 IEEE.

Procesamiento de imágenes para la detección de óxidos residuales en líneas de producción de laminados metálicos
C. González-Spínola, J.M. Bonelo-Sanchez, C.J. Gálvez-Fernández, J.M. Cañero- Nieto, M.J. Martin-Vazquez, J. Vizoso-Laporte and S. Espejo-Meana
Conference - Seminario anual de automática, electronica industrial e instrumentación SAAEI 2008
[abstract]
En este artículo se presenta un algoritmo para la detección de óxidos residuales en la superficie de láminas de acero inoxidable. El algoritmo analiza en tiempo real imágenes del material en movimiento, tomadas por un sistema de adquisición instalado en una línea de producción, y detecta manchas de óxido de tamaño mayor que 50μm. Se presenta el algoritmo básico y las correcciones introducidas para resolver las deficiencias detectadas.

Data Matrix Code Recognition using the Eye-RIS Vision System
A. Jimenez-Marrufo, A. Mendizabal, S. Morillas-Castillo, R. Dominguez-Castro, S. Espejo, R, Romay-Juarez and A. Rodriguez-Vazquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2007
[abstract]
This demo illustrates the processing capabilities of the Eye-RIS vision systems; specifically using the Eye-RIS v1.2. These systems employ an AnaFocus's a proprietary architecture where processing is realized in two steps. The first stage of the architecture embeds sensors, parallel processing analog and mixed-signal circuitry, control circuitry and memory. This front-stage is implemented through dedicated bio-inspired chips. The second stage of the Eye-RIS vision system architecture is a digital microprocessor. The combination of parallel preprocessing and serial post-processing makes the Eye-RIS systems very efficient particularly the Eye-RIS systems are capable to close the sensor-processing-actuation loop at a high speed. In this demo, the Eye-RIS v1.2 is used to recognize data matrix codes at more than 200 codes/sec rate.

ACE16k based stand-alone system for real-time pre-processing tasks
L. Carranza, F. Jiménez Garrido, G. Liñán-Cembrano, E. Roca, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.

ACE16k-Ds: un Sistema autónomo programable para el preprocesamiento de imágenes en tiempo real
L. Carranza-González, F.J. Jimenez-Garrido, G. Liñán-Cembrano, E. Roca-Moreno, S. Espejo-Meana and A. Rodríguez-Vázquez
Conference - Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2004
[abstract]
Este artículo describe un sistema electrónico autónomo y programable, denominado ACE16k-DS, que permite sensar y procesar imágenes en tiempo real. La arquitectura del sistema está basada en el chip ACE16k y en la FPGA Xc4028xl de Xilinx en la que se han sintetizado una Unidad de Control Programable de propósito específico y un generador de vídeo digital. Las imágenes son sensadas y procesadas, en modo analógico, en el chip ACE16k, siguiendo instrucciones secuenciadas por la Unidad de Control Programable. El generador de vídeo digital permite visualizar, en una pantalla TFT, las imágenes procesadas en tiempo real.

CMOS mixed-signal flexible vision chips
G. Liñán-Cembrano, L. Carranza-González, S. Espejo-Meana, R. Domínguez-Castro and A. Rodríguez-Vázquez
Book Chapter - Smart Adaptive Systems on Silicon, pp 103-118, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_7    ISBN: 978-1-4757-1051-9    » doi
[abstract]
Today, with 0.18μm technologies fully mature for mixed-signal design, CMOS compatible optical sensors available, and with 0.09μm knocking at the door of designers, we have the pieces to confront the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last years towards the realization of Vision Systems on Chips. Such VSoCs are targeted to integrate in a semiconductor substrate the functions of sensing, image processing in space and time, high-level processing and control of actuators. Based on newest discoveries of neurobiologists about the behavior of mammalian retinas, a new generation of flexible mixed-signal vision chips has been created which feature better Speed vs. Power figures than DSP-based systems. These devices are true mixed-signal microprocessors including standard digital I/O, embedded image and program memories. This chapter presents some concepts related to the architectures, circuits and methodologies associated to the design of these chips. Due to space limitations, and for the sake of illustrating different topics related to the design of such a kind of vision chips we will concentrate on the series of ACE devices developed by our group since 1996, referring the interested reader to some of the references at the end of the chapter.

Vertebrate retina emulation using multi-layer array-processor mixed-signal chips
R. Carmona-Galán, A. Rodríguez-Vázquez, R. Domínguez-Castro and S. Espejo Meana
Book Chapter - Smart Adaptive Systems on Silicon, pp 85-101, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_6    ISBN: 978-1-4757-1051-9    » doi
[abstract]
A bio-inspired model for an analog programmable array processor (APAP), based on stu dies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented here.

A 1000 FPS@128x128 vision processor with 8-bit digitized I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference - European Solid-State Circuits Conference ESSCIRC 2004
[abstract]
This paper presents a mixed-signal programmable, chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-mum fully digital CMOS technology, contains similar to 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm(2) and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be: programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions - applications using exposures of about 50 mus have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory) and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

ACE16k: The third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs
A. Rodríguez-Vázquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro and S. Espejo-Meana
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 851-863, 2004
IEEE    DOI: 10.1109/TCSI.2004.827621    ISSN: 1057-7122    » doi
[abstract]
Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm(2) and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3 x 3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
R. Carmona-Galán, F. Jiménez-Garrido, C.M. Domínguez-Mata, R. Domínguez-Castro, S. Espejo-Meana, I. Petras and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 5, pp 913-925, 2004
IEEE    DOI: 10.1109/TCSI.2004.827641    ISSN: 1057-7122    » doi
[abstract]
Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple, resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-mum CMOS technology.

ACE16k: a 128x128 focal plane analog processor with digital I/O
G.L. Cembrano, A. Rodríguez-Vázquez, S. Espejo Meana and R. Domínguez-Castro
Journal Paper - International Journal of Neural Systems, vol. 13, no. 6, pp 427-434, 2003
WORLD SCIENTIFIC PUBLISHING    DOI: 10.1142/S0129065703001765    ISSN: 0129-0657    » doi
[abstract]
This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.

An improved elementary processing unit for high-density CNN-based mixed-signal microprocessors for vision
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - Journal of Circuits, Systems and Computers, vol. 12, no. 6, pp 675-690, 2003
WORLD SCIENTIFIC PUBLISHING    DOI: 10.1142/S0218126603001100    ISSN: 0218-1266    » doi
[abstract]
This paper presents the architecture of the (E) under bar lementary (P) under bar rocessing (U) under bar nit - EPU which has been employed to design a CNN-Based 128 x 128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3 x 3 convolution masks,1 or information propagative CNN templates.(2) Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128 x 128 EPUs and a completely digital interface, in a standard fully-digital 0.35 mum CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm(2) and 100 GOP/J.

Programmable retinal dynamics in a CMOS mixed-signal array processor chip
R. Carmona, F. Jiménez-Garrido, R. Domiguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - Conference on Bioengineered and Bioinspired Systems 2003
[abstract]
The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5mum CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 x 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.

Analog weight buffering strategy for CNN chips
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Carmona, S. Espejo and R. Domínguez Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, accuracy is ultimately limited by the controlling signals. This paper presents a buffering strategy intended to achieve 8-bit equivalent accuracy in the distribution of the internal analog signals, as employed in the chips ACE4k [1], ACE16k [2], and CACE1k [3].

A versatile sensor interface for programmable vision systems-on-chip
A. Rodríguez-Vázquez, G. Liñán, E. Roca, S. Espejo and R. Dominguez-Castro
Conference - Conf. on Sensors and Camera Systems for Scientific, Industrial, and Digital Photography 2003
[abstract]
This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35mum n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 x 128 identical cells, each cell corresponding to a pixel. Die size is 11.885 x 12.230mm(2) and cell size is 75.7mum x 73.3mum. Each cell contains 198 transistors dedicated to functions like processing, storage, and sensing. The system is oriented to real-time, single-chip image acquisition and processing. Since each pixel performs the basic functions of sensing, processing and storage, data transferences are fully parallel (image-wide). The programmability of the processing functions enables the realization of complex image processing functions based on the sequential application of simpler operations. This paper provides a general overview of the system architecture and functionality, with special emphasis on the optical interface.

A mixed-signal early vision chip with embedded image and programming memories and digital I/O
G. Liñán-Cembrano, A. Rodríguez-Vázquez, R. Domiguez-Castro and S. Espejo
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35mum standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

A bio-inspired two-layer mixed-signal flexible programmable chip for early vision
R.C. Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, T. Roska, C. Rekeczky, I. Petras and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1313-1336, 2003
IEEE    DOI: 10.1109/TNN.2003.816377    ISSN: 1045-9227    » doi
[abstract]
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the Visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 mum. CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.

Mismatch-induced trade-offs and scalability of analog preprocessing visual microprocessor chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range. The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenaRíos, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.

Ultra-high frame rate focal plane image sensor and processor
A. Zarándy, R. Domínguez-Castro and S. Espejo
Journal Paper - IEEE Sensors Journal, vol. 2, no. 6, pp 559-565, 2002
IEEE    DOI: 10.1109/JSEN.2002.806895    ISSN: 1530-437X    » doi
[abstract]
Application examples of a fully-programmable analogic focal plane array processor are introduced. One mixed-signal sensory/processing chip is presented, which is capable to capture, process, and evaluate over 10,000 images in a second. Morphological analysis of silhouettes and sparks were done and real-time decision making was performed running on this extraordinary high frame-rate. © 2002 IEEE.

A processing element architecture for high-density focal plane analog programmable array processors
G. Liñán-Cembrano, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
The architecture of the elementary Processing Element - PE- used in a recently designed 128x128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 x 3 convolution masks. The vision chip has been implemented in a standard 0.35mum CMOS technology. The main PE related figures are: 180 cells/mm(2), 18 MOPS/cell; and 180 muW/cell.

Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper explores different trade-offs associated to the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of processors), as fabrication technologies scale down into deep sub-micron.

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5mum CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper.

Bio-inspired analog VLSI design realizes programmable complex spatio-temporal dynamics on a single chip
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2002
[abstract]
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed in 0.5 mum CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper.

CE16K: A 128x128 focal plane analog processor with digital I/O.
G. Liñán, A. Rodríguez-Vázquez, S. Espejo and R. Domínguez-Castro
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
This paper presents a new generation 128x128 Focal-Plane. Analog Programmable Array Processor FPAPAP-, from a system level perspective, which has been manufactured in a 0.35mum standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy -8b-requirements of most real time -early-vision processing applications. It is easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 90% of them working in analog mode, and exhibits a relatively low power consumption -<4W, i.e. less than 1muW per transistor. Computing vs. power peak values are in the order of 1TeraOPS/W, while maintained VGA processing throughputs of 100Frames/s are possible with about 10-20 basic image processing tasks on each frame.

CMOS realization of a 2-layer CNN universal machine chip
R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo and A. Rodríguez-Vázquez
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the possibilities of these complex spatio-temporal dynamics in image processing, a prototype chip has been developed implementing this CNN model with analog signal processing blocks. This chip has been designed in a 0.5 mum CMOS technology. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 x 10(6) transistors, most of them operating in analog mode) are presented in this paper(a).

A multimode gray-scale CMOS optical sensor for Visual computers
G. Liñán, A. Rodríguez-Vázquez, S. Espejo, R. Domínguez-Castro and E. Roca
Conference - IEEE International Workshop on Cellular Neural Networks and Their Applications CNNA 2002
[abstract]
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as well as the mechanism for transducing the photogenerated charges into the correspondent pixel voltage. Both linear or logarithmic compression acquisition modes are available. This makes the sensor very suitable to be used in very different illumination conditions.

Architectural and basic circuit considerations for a flexible 128x128 mixed-signal SIMD vision chip
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 179-190, 2002
SPRINGER    ISSN: 0925-1030    
[abstract]
From a system level perspective, this paper presents a 128 x 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 mum standard digital IP-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (similar to7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm(2)) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10-20 basic image processing tasks on each frame.

ACE4k: An analog I/O 64 x 64 visual microprocessor chip with 7-bit analog accuracy
G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 30, no. 2-3, pp 89-116, 2002
JOHN WILEY & SONS    DOI: 10.1002/cta.191    ISSN: 0098-9886    » doi
[abstract]
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 mum standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are: local interactions, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time ( < 300 ns for linear convolutions) and using a low power budget ( < 1.2 W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with > 7-bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7-bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templatesigma-either directly or through template decomposition. This means the 100% of the 3 x 3 linear templates reported in Roska et al. 1998, [1]. Copyright (C) 2002 John Wiley Sons, Ltd.

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