Spanish National Research Council · University of Seville
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Author: Ginés Arteaga, Antonio J.
Year: Since 2002
All publications
Fast adaptive comparator offset calibration in pipeline ADC with self-repairing thermometer to binary encoder
A.J. Ginés, E. Peralías, C. Aledo and A. Rueda
Journal Paper - International Journal of Circuit Theory and Applications, vol. 47, no. 3, pp 333-349, 2019
JOHN WILEY & SONS    DOI: 10.1002/cta.2594    ISSN: 0098-9886    » doi
[abstract]
This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15-bit resolution (74 dB-Signal-to-noise plus Distortion Ratio [SNDR]). A self-repairing (SR) thermometer-to-binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one-half least-significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15-bit pipeline ADC using a novel calibrated dynamic-latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

Assessing AMS-RF test quality by defect simulation
V. Gutierrez, A. Gines and G. Leger
Journal Paper - IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp 55-63, 2019
IEEE    DOI: 10.1109/TDMR.2019.2894534    ISSN: 1530-4388    » doi
[abstract]
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on practical cases of study that it is beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality. The computational burden of defect and fault simulations is taken into account and accurate statistical estimates of defect and fault escapes are provided to allow safe early stopping of the simulations.

SAR ADCs with Redundant Split-capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
This paper analyzes the effect of redundancy in Successive Approximation Register (SAR) ADCs with splitcapacitor DAC (Split-CDAC). It also presents a general hardware-based model which provides closed-relationships, suitable for design, between the capacitor scale factors, the bridge capacitance and the practical implementation of the digital correction logic. In conventional binary Split-CDAC (without redundancy), the voltage at the floating nets in the array could exceed the ADC references, stressing the operation of switches. Using the proposed model, we will show that this effect also occurs in SAR ADCs with redundancy, but with some particularities depending on the selection of the weighting coefficients in the digital correction logic. We will demonstrate the excursion can be controlled, as in the binary case, with a simple DAC modification which includes an extra limiting capacitor.

Redundant SAR ADCs with Split-Capacitor DAC
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2018
[abstract]
This paper presents an unified formulation for Successive Approximation Register (SAR) ADCs with splitcapacitor arrays providing explicit expressions, suitable for design, of the relationships between capacitors and the weighting coefficient in the digital correction logic. A closed-form estimation of the optimum limiting capacitor to control the voltage excursion in the floating node of the Least Significant Bit (LSB) array is, in the authors´ bibliography best knowledge, firstly derived in this work. The proposed hardware-based formulation has been verified by behavioral and electrical simulations.

AMS-RF test quality: Assessing defect severity
V. Guiterrez, A. Gines and G. Leger
Conference - IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
[abstract]
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on a practical case of study that it may be beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality.

Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach
A. Gines, A. Lopez-Angulo, E. Peralias and A. Rueda
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
This paper analyzes the state-of-the-art in Successive-Approximation-Register (SAR) ADCs with digital redundancy using a unified nomenclature and modeling. Redundancy provides tolerance intervals for dealing with comparison errors during the SAR search algorithm due to incomplete settling in the DAC. Employing redundancy improves conversion speed/power trade-off as well as relaxes switch sizes and comparator design. The proposed description presents a common theoretical and physical framework for analyzing existing (apparently different) techniques in the bibliography, independently of the practical realization (binary or arbitrary scaled capacitors with redundant bits) and switching schemes. Several examples are modeled and simulated using the proposed approach.

Unified Hardware-Based Description for SAR ADCs with Redundancy
A. Lopez-Angulo, A. Gines, E. Peralias and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
[abstract]
This paper presents an analysis and review of digital redundancy techniques in Successive-Approximation-Register (SAR) ADCs for correction of comparator errors during the SAR search algorithm. The use of redundancy provides safety margin for dealing with incomplete settling in the DAC network, improving conversion speed and power, as well as relaxing switch sizes and comparator design. Techniques like binaryscaled, radix-based or arbitrary weighing capacitors with redundant bits are discussed using a unified nomenclature and modeling. The proposed unified description is closely related to the hardware realization eliminating the gap between theoretical and physical implementations, and allowing a clear identification of pros and cons of different approaches. For illustration purpose, several examples are modeled and simulated using the proposed description.

Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs
A.J. Gines, E. Peralias and A. Rueda
Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp 2966-2970, 2017
IEEE    DOI: 10.1109/TVLSI.2017.2718625    ISSN: 1063-8210    » doi
[abstract]
This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparators produce time-variant offsets depending on the input-signal slope at the sampling instants. These increase residue excursions at the MDAC output, potentially causing overranging and an increment in nonlinear errors. This paper derives close analytical expressions for these effects. The proposed method uses the overranging information to perform a low-cost estimation and correction of the skew error with the following features: 1) very fast convergence (in the order of 1-k input samples); 2) indirect evaluation of the skew error signal, without any previous knowledge of the input signal's frequency distribution; and 3) relatively simple digital logic--basically, two digital comparators and one small accumulator. The method was verified in behavioral and transistor-level simulations. As a demonstrator, its implementation in a 1.8-V 80-dB SNDR 100-Msps SHA-less pipeline ADC in a 0.18-μm CMOS process is shown.

Likelihood-sampling adaptive fault simulation
G. Leger and A. Gines
Conference - International Mixed-Signals Testing Workshop IMSTW 2017
[abstract]
This paper builds upon recent developments that argue for a fault simulation based on defect-likelihood sampling. It first questions, with a number of synthetic experiments, the premises of this approach and offers an alternative simple mechanism for the random selection of defects. Then, it introduces a new layer of variability with the parametrization of the opens and shorts resistivity while keeping the computational cost overhead low by means of an adaptive strategy.

On the limits of machine learning-based test: A calibrated mixed-signal system case study
M.J. Barragan, G. Leger, A. Gines, E. Peralias and A. Rueda
Conference - Design, Automation and Test in Europe DATE 2017
[abstract]
Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system -i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

Black-Box Calibration for ADCs with Hard Nonlinear Errors using a Novel INL-Based Additive Code: A Pipeline ADC Case Study
A.J. Ginés, E.J. Peralías and A. Rueda
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 7, pp 1718-1729, 2017
IEEE    DOI: 10.1109/TCSI.2017.2662085    ISSN: 1549-8328    » doi
[abstract]
This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

A Compact R-2R DAC for BIST Applications
A. Rabal, A. Otin, I. Urriza, A.J. Gines, G. Leger and A. Rueda
Conference - International Mixed-Signals Testing Workshop IMSTW 2016
[abstract]
This paper presents the implementation of a compact R-2RDigital-to-Analog Converter (DAC) for BIST applications of analog and mixed-signal circuits. It focuses on evaluating the DAC design requirements and its possibilities in structural and alternate test methodologies. More concretely, the aim of the paper is the low-cost generation of digitally programmable DC voltages for parametric deviation injection. For the sake of validation, these voltages will be considered to modify the voltage references of bias circuit or cascode voltages in op-amps. The DAC has been implemented in a UMC 65nm LL CMOS process, and comprises a front-end passive R-2R ladder followed by an active buffer based on a two-stage amplifier with Miller's compensation. Special care has been taken in the resistors ladder layout, as a critical parameter to minimize the mismatch impact due to process variations and maximize the final static behavior. The total power consumption and overall die area for the R-2R DAC ladder are 120 μW and 88x64 μm2, respectively. The op-amp design could be optimized depending on the load and driving requirements.

Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference - International Mixed-Signals Testing Workshop IMSTW 2016
[abstract]
This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed highperformance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in the order of 12 bits and 80 Msps of sampling frequency.

A 76nw, 4ks/S 10-Bit SAR ADC with Offset Cancellation for Biomedical Applications
M. Delgado-Restituto, M. Carrasco Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference - IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2016
[abstract]
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.

A Low-Energy 10-bit SAR ADC with Embedded Offset Cancellation
M. Delgado-Restituto, M. Carrasco-Robles, R. Fiorelli, A.J. Gines-Arteaga and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2016
[abstract]
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180 nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2 nW at 4 kS/s and achieves 9.5-b ENOB.

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
J. Núñez, A.J. Ginés, E. Peralías and A. Rueda
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 89, no. 33, pp 593-609, 2016
SPRINGER    DOI: 10.1007/s10470-016-0870-6    ISSN: 0925-1030    » doi
[abstract]
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 μm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.

Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference - IEEE European Test Symposium ETS 2016
[abstract]
This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutionsin the order of 13 bits and 100Msps of sampling frequency.

Low-jitter differential clock driver circuits for high-performance high-resolution ADCs
J. Núñez, A.J. Gines, E. Peralías and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18μm commercial CMOS process.

Background Digital Calibration of Comparator Offsets in Pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 203, no. 7, pp 1345-1349, 2015
IEEE    DOI: 10.1109/TVLSI.2014.2335233    ISSN: 1063-8210    » doi
[abstract]
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs
J. Núñez, A.J. Ginés, E.J. Peralías and A. Rueda
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2015
[abstract]
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for highperformance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm).

Power Optimization and Stage Op-amp Linearity Relaxation in Pipeline ADCs with Digital Comparator Offset Calibration
A. Ginés, E. Peralias, C. Aledo and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2014
[abstract]
This paper presents a power optimization technique for Pipeline ADCs using digital background calibration of comparator offsets as an extra design variable. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax the power consumption of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. The proposal was validated using realistic hardware-behavioral models and transistor-level simulations. A 1.8V 15-bit 74dB-SNDR 100Msps Pipeline ADC was used as a demonstrator. Thanks to comparator calibration, the total power of stage subADCs was reduced by 75%, while a factor of 19% was found in stage amplifiers.

INL Systematic Reduced Test Technique for Pipeline ADCs
E. Peralías, A. Ginés and A. Rueda
Conference - IEEE European Test Symposium ETS 2014
[abstract]
This paper presents a procedure to implement a high efficient test of the Integral Non-linearity (INL) of Pipeline ADCs using an extremely reduced set of test input amplitude levels (one order of magnitude lower than the total number of codes in the ADC). For a given architecture, the method provides the way to determine these levels to robustly capture the nonlinearity information. The location of each test level within the input range has low sensitivity to the internal ADC noise, and therefore, they are a good basis to continuously monitor the impact of process, aging and environment conditions variations (PVT) on the non-linearity, as well as miscalibration and possible failures in both foreground and background applications. The proposed method has been validated by realistic behavioral models in several examples.

Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
A.J. Ginés, G. Leger, E. Peralías and A. Rueda
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2014
[abstract]
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.

Sigma-Delta Testability for Pipeline A/D Converters
A. Gines and G. Leger
Conference - Design Automation and Test in Europe DATE 2014
[abstract]
Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixedsignal blocks, particularly if digital correction and calibration is considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplification as integrators with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that do not require any extra pin. In addition, digital test techniques developed for ΣΔ modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18μm CMOS process is used as a case of study for the introduction of the DfT modifications.

Inductor Characterization in RF LC-VCOs
R. Doldan, A.J. Gines and A. Rueda
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
[abstract]
This paper analyzes the characterization of inductors in resonant radio frequency (RF) circuits, with emphasis in LC voltage-controlled oscillators (VCOs). We will demonstrate how inductor quality factor is often underestimated in the vicinity of self-resonance frequency, because its capacitive parasitic contribution is not properly considered. In consequence, some valid inductor geometries could be incorrectly discarded during the initial circuit optimization process. To overcome this design space limitation, the paper presents an alternative method to characterize inductors at the wanted resonant frequency. The comparison between the conventional and the proposed methods is illustrated with the characterization of a complete inductor library in a commercial 90nm CMOS RF technology.

Mixed-Signal Techniques for Robust Auto-Tuning of Split-Tuned PLL Frequency Synthesizers
C. Aledo, A.J. Ginés, E. Peralías and A. Rueda
Conference - Conference on the Design of Circuits and Integrated Systems DCIS 2013
[abstract]
This paper proposes two different phase-locked loop (PLL) auto-tuning techniques for low-cost sub-band selec-tion in split-tuned frequency synthesizers. The methods conti-nuously monitor the tuning voltage Vtune of the voltage-controlled oscillator (VCO) using two comparators whose threshold voltages define the PLL design region. Considering the comparators deci-sion, a simple digital control unit (DCU) generates a correction signal which assures Vtune is always within the allowable range, hence concurrently dealing with process, voltage and tempera-ture (PVT) variations. Two alternative algorithms depending on the DCU implementation have been proposed as trade-off between hardware complexity and convergence response. Both algorithms have been experimentally validated in a 1.2V PLL frequency synthesizer. This PLL block is part of a monolithical 2.4GHz IEEE 802.15.4 ZigBee transceiver implemented in a RF 90nm CMOS technology.

Background Calibration of Comparator Offsets in Pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference - International Conference on Analog VLSI Circuits AVIC 2012
[abstract]
A digital low-cost adaptive technique for calibrating comparator offsets in Pipeline ADCs is proposed in this paper. The method is suitable for a generic topology including standalone dynamic-latch comparators (SA-DLCs) with no external reference and no preamplifier. It performs an accurate blind estimation and an adaptive correction of comparator offsets without redundant hardware or calibration stimuli, and without interruption of the ADC operation (background mode). The method also allows relaxing the power consumption of stage amplifiers, since their output swing and driving capability are significantly reduced. The technique has been validated by realistic hardware-behavioral models and transistor-level simulations.

Self-Biased Input Common-Mode Generation for Improving Dynamic Range and Yield in Inverter-Based Filters
A.J. Ginés, A. Villegas, A. Rueda and E. Peralías
Conference - IEEE International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
A simple and robust circuit for the input commonmode voltage generation in CMOS pseudo-differential inverter-based transconductors is proposed. The solution can improve the in-band IIP3 in 7.8dBVp and the 1-dB compression point in 5.3dBVp compared to conventional approaches, with less noise, power consumption and occupied die area. A 1.2V 3.42mW 1.3-3.7MHz high-linear 8th order bandpass complex filter is presented as demonstrator in a CMOS 90nm process. The yield for an image rejection ration IRR above 50dB is 86%, which represents a 31% improvement respect to the classical approach.

Analysis of steady-state common-mode response in differential LC-VCOs
R. Doldán, A.J. Ginés, E. Peralías and A. Rueda
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2012
[abstract]
This paper analyzes the common-mode response of LC voltage-controlled oscillators (VCOs) in DC and periodic steady state regimes. The dependence of the common-mode voltage (v cm) on the oscillation amplitude is theoretically studied. Closed and simple expressions for v cm suitable for the VCO design and optimization are derived. The agreement with transistor level simulations has been verified in a 1.2V low-power 90nm CMOS case of study.

Blind adaptive estimation of integral nonlinear errors in ADCs using arbitrary input stimulus
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper - IEEE Transactions on Instrumentation and Measurement, vol. 60, no. 2, pp 452-461, 2011
IEEE    DOI: 10.1109/TIM.2010.2051062    ISSN: 0018-9456    » doi
[abstract]
An adaptive digital test procedure for the static characterization of analog-to-digital converters (ADCs) is described in this paper. The proposed technique performs a blind and accurate estimation of the integral nonlinearity (INL) of the ADC under test (ADCUT) without requiring any particular test stimulus. Its practical implementation implies no modifications on the ADCUT analog section and needs a very simple low-cost digital logic, which makes this useful for: 1) simple digital automatic test equipment (ATE)-based ADC static test and 2) built-in self-test (BIST) for ADCs test working either in concurrent (online) or nonconcurrent (offline) modes. The validation of these test methods has been performed through realistic behavioral simulations including noise, mismatch, and nonlinear errors. Experimental results for a custom-designed pipeline ADC and for the commercial AD664 chip are also reported.

Power Optimization of CMOS Programmable Gain Amplifiers with High Dynamic Range and Common-Mode Feed-Forward Circuit
A.J. Gines, R. Doldán, A. Rueda and E. Peralias
Conference - IEEE International Conference on Electronics, Circuits and Systems ICECS 2010
[abstract]
A 1.2V 1.95mW low-power Programmable Gain Amplifier (PGA) with high-input range is proposed and implemented in a 90nm CMOS process. The PGA is formed by three stages with a bandwidth of 20MHz for a 2pF capacitive load. Gain is in the range between 0 and 72dB in steps of 6dB. The stage core consists in a differential super-source follower (SSF) with programmable resistive degeneration. Each stage uses a front-end capacitive decoupling network which allows a robust selection of the operating point for improving linearity and reducing power. Further power saving is achieved with a common-mode feed-forward circuit (CMFFC), based on a simple current conveyor. The total PGA area is 165×33μm2 in a 90nm CMOS process. Post-layout simulations at maximum gain show a THD of -57dB and -42dB for output amplitudes of 0.6Vpp and 1.2Vpp, respectively. Input referred noise is just 10.2nVrms/√Hz from 1MHz to 4MHz.

A low-power programmable gain amplifier with optimized input range in 90nm CMOS process
A.J. Ginés, R. Doldán, A. Rueda and E. Peralías
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2010
[abstract]
Abstract not available

A 5 GHz LC-VCO with active common mode feedback circuit in sub-micrometer cmos technology
R. Doldán-Lorenzo, A.J. Ginés-Arteaga, A. Rueda and E. Peralías
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2010
[abstract]
A 1.2V 5GHz low-cost voltage-controlled oscillator (VCO) with active common mode feedback has been implemented in a CMOS/RF 90nm technology for a robust I/Q generation using a frequency divider-by-2 (DIV2). As the input common mode of the DIV2 affects critically its performance, a calibration method to correct the output common mode of the VCO has been proposed and validated through post-layout simulations.

An adaptive BIST for INL estimation of ADCs without histogram evaluation
A.J. Ginés, E. Peralías and A. Rueda
Conference - IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop IMS3TW 2010
[abstract]
A robust low-cost test solution for static characterization of analog-to-digital converters (ADCs) is presented in this paper. It uses an adaptive algorithm to perform a blind and accurate estimation of the Integral Non-Linearity (INL) of the ADC under test (ADCUT). Its main applications are for: a) simple off-line ADC test using modern mixed-signal ATEs (Automatic Test Equipments) without requiring any dedicated input stimulus, b) Built-in Self-test (BIST) for ADC INL evaluation either in concurrent (on-line) or non-concurrent (off-line) modes. The test validation has been performed through realistic behavioral simulations including noise, mismatch and non-linear errors. Experimental results for a custom-designed 10-bit Successive Approximation (SAR) ADC are also reported. ©2010 IEEE.

On chopper effects in discrete-time ΣΔ modulators
G. Leger, A.J. Ginés-Arteaga, E. Peralías-Macias and A. Rueda
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, no. 9, pp 2438-2449, 2010
IEEE    DOI: 10.1109/TCSI.2010.2043996    ISSN: 1549-8328    » doi
[abstract]
Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation
A.J. Ginés, R. Doldán, M.J. Barragán, A. Rueda and E. Peralías
Conference - International Symposium on Circuits and Systems ISCAS 2010
[abstract]
In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude between 0 degrees C and 100 degrees C with negligible impact on the phase noise. Worst case estimations of the VCO phase noise after layout parasitic extraction are -110.1dBc/Hz and -126.6dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. Its nominal current consumption is 198μA (plus 22.5μA for biasing) and it occupies 370x530μm2.

Random Chopping in Sigma-Delta Modulators
G. Léger, A. Gines, E. Peralias and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2009
[abstract]
ΣΔ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result ΣΔ modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of applications and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Frequency-shaped random chopping has been proposed to minimize the impact of reference voltage interference. It is shown in this paper that the chopper signal is not the only term that modulates the offset and Flicker noise and that unwanted crosstalk can significantly degrade the performance of the modulator.

On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation
A.J. Ginés, E. Peralías and A. Rueda
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
An adaptive digital built-in self-test (BIST) for the static characterisation of analogue-to-digital converters (ADCs) has been developed in this work. The proposed technique performs a blind and accurate estimation of the Integral Non-Linearity (INL) of the ADC under test (ADCUT) without affecting to the normal converter operation, using any test stimuli or replicated hardware. The practical implementation of the BIST technique implies no modifications on the analogue section of the ADCUT and uses a very simple low-cost digital logic, which overcomes the classical area overhead of histogram-based approaches for INL measurement.

A survey on digital background calibration of ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference - European Conference on Circuit Theory and Design ECCTD 2009
[abstract]
In this paper, a general description of digital ADC calibration approaches in current state-of-the-art is presented, with particular emphasis in Pipeline converters. The study performs a classification of the existing techniques considering two basic aspects: a) the principle of operation and the particular errors which can be compensated after calibration, b) the process from which a measurement of the errors, and therefore the calibrated output code, is obtained. Attention will be paid to those approaches applied in background mode and hence not requiring the interruption of the normal ADC operation.

A 2.5MHz bandpass active complex filter with 2.4MHz bandwidth for wireless communications
A. Villegas, R. Bianca, A. Ginés, R. Doldán, M.A. Jalón, A.J. Acosta, E. Peralías, D. Vázquez and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2008
[abstract]
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V).

Calibración digital concurrente en convertidores A/D de tipo pipeline
A.J. Ginés-Arteaga
Thesis - Date of defense: 18/07/2008
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
Abstract not avaliable

A 5 GHz wide tuning range LC-VCO in sub-micrometer CMOS technology
R.D. Lorenzo, A.J. Ginés-Arteaga, A. Rueda and E. Peralías
Conference - IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
[abstract]
A 1.2V low-cost voltage-controlled oscillator (VCO) has been implemented in a CMOS/RF 90nm technology. The VCO, which uses a LC- tank topology, has a centre frequency of 5GHz with a 30% tuning range from 4.24GHz to 5.74GHz. Worst case estimations of the phase noise after layout and package parasitic extraction are -98.8dBc/Hz and -115dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. The power consumption is 2.52mW and it occupies less than 0.07mm(2).

A 1.2V 5.14 mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4 GHz ZigBee applications
A.J. Ginés, R. Doldán, A. Villegas, A.J. Acosta, M.A Jalón, D. Vázquez, A. Rueda and E. Peralías
Conference - IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008
[abstract]
A low-cost 1.2V 5.14mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90nm CNIOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of-105.9dBc/Hz at 1MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209x422 mu m(2).

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 57, no. 1-2, pp 57-68, 2008
SPRINGER    DOI: 10.1007/s10470-008-9195-4    ISSN: 0925-1030    » doi
[abstract]
A novel swapping technique for stage non-linear error calibration in Pipeline ADCs (analogue-to-digital converters) is presented in this paper. The proposed algorithm obtains an estimation of the mismatch between sampling capacitors in the MDAC (multiplying digital-to-analogue converter) inside each stage, without the necessity of interrupting the ADC operation, and therefore, suitable for background calibration applications. The technique also shows its applicability for the amplifier finite DC-gain error, providing a low-cost solution for full calibration of the main static errors in the Pipeline topology with less convergence time, memory resources and simpler calibration hardware than other existing calibration methods. In addition, this work overcomes practical limitations of previous adaptive approaches based on capacitor swapping by introducing a novel modulation scheme. This new scheme minimizes the impact on the analogue part and employs a very simple digital modulation logic.

Novel swapping techniques for background calibration of capacitor mismatching in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference - Symposium on Integrated Circuits and System Design SBCCI 2007
[abstract]
A novel swapping technique for calibration of the stage non-linear errors in Pipeline ADCs is proposed in this paper. The algorithm obtains an estimation of the mismatching between sampling capacitors in practical SC implementations of the multiplying-DAC without the necessity of interrupting the converter operation, and therefore, suitable for both foreground and background calibration applications. This work overcomes the practical limitations of previous adaptive approaches based on the capacitor swapping introducing a novel modulation scheme which minimizes the impact on the analogue part and employs a simple calibration logic.

Improved background algorithms for pipeline ADC full calibration
A.J. Ginés, E. Peralías and A. Rueda
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
A unified description of the correlation-based techniques for background calibration of Pipeline ADCs using additive modulation at the MDAC output is presented in this paper. Two different algorithms for full calibration of this kind of converter which at least a factor 2 improvement in convergence speed, memory resources and stage output swing requirements over previous MDAC modulation approaches are also proposed.

Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs(1)
A.J. Ginés, E. Peralías and A. Rueda
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2006
[abstract]
This paper presents a theoretical analysis of the statistical requirements of a background correlation-based technique for calibration of Pipeline ADCs. The calibration algorithm estimates adaptively the appropriate additive error codes which compensate both the gain and non-linear errors in the stage under calibration (SUC). Close equations for the transient evolution towards the stationary situation are obtained. Expressions for the effective number of bits (ENOB) and signal-to-noise ratio (SNR) at any updating step are also derived.

Full calibration digital techniques for pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference - International Symposium on Circuits and Systems ISCAS 2005
[abstract]
This paper presents a new digital algorithm for full calibration of Pipeline ADCs with digital redundancy. The proposed algorithm corrects both the MDAC gain error of the stage under calibration (SUC) and its non-linear errors. It is based on the modulation of the analogue output of the SUC using a digital control signal to introduce a constant displacement in the references of the comparators in the SUC sub-ADC without reduction of the input dynamic rate. This process can be performed without interruption of the conversion (background mode) including a digital pseudo-random number generator (RNG). The foreground implementation of this algorithm uses a DC calibration stimulus which relaxes the hardware requirements.

Noisy signal based background technique for gain error correction in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
The paper presents a new digital technique for background calibration of gain errors in pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration (SUC) and the global gain error associated with the least significant stages. This process is performed without interruption of the conversion and without reduction of the dynamic range. It uses a stage with two input-output characteristics depending on the value of a digital pseudorandom noisy signal to modulate the output residue of the SUC and to estimate the calibration code by an adaptive averaging process. The proposed method introduces no significant modifications in the analogue blocks of the pipeline ADCs, making this technique a very promising alternative for background calibration of the nonlinearity associated with the gain errors. Simulation results have proved the stability of the algorithm and the tracking capability for fast gain error changes considering second order effects in both the sub-ADC of the SUC and the back-end stages.

Digital background gain error correction in pipeline ADCs
A.J. Ginés, E. Peralías and A. Rueda
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
This paper presents a new digital technique for background calibration of gain errors in Pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.

Digital background calibration technique for pipeline ADCs with multi-bit stages
A.J. Ginés, E. Peralías and A. Rueda
Conference - Symposium on Integrated Circuits and Systems Design SBCCI 2003
[abstract]
This paper presents a technique for background calibration of Pipeline ADCs with multi-bit stages, based on an adaptive approach. Different implementations Of the LMS algorithm have been studied, concluding that the traditional SS-LMS algorithm has inherent convergence problems in high accuracy ADCs that can be solved considering a SD-LMS implementation.

A mixed-signal design reuse methodology based on parametric behavioural models with non-ideal effects
A.J. Ginés, E. Peralías, A. Rueda, N.M. Madrid and R. Seepold
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2002
[abstract]
Current System-on-Chip (SoC) designs incorporate an increasing number of mixed-signal components. Design reuse techniques have proved successful for digital design but these rules are difficult to transfer to mixed-signal design. A top-down methodology is missing but the low level of abstraction in designs makes system integration and verification a very difficult, tedious and complex task. This paper presents a contribution to mixed-signal design reuse where a design methodology is proposed based on modular and parametric behavioural components. They support a design process where non-ideal effects can be incorporated in an incremental way, allowing easy architectural selection and accurate simulations. A working example is used through the paper to highlight and validate the applicability of the methodology.

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