Found results matching for:
Author: Pau Ortega Castro
Year: Since 2002
Journal Papers
Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation
P. Ortega-Castro, E. Camacho-Ruiz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Journal Paper · IEEE Open Journal of the Solid-State Circuits Society (Early Access)
abstract
doi
In increasingly interconnected systems, security has become a critical concern. In this context, delay-based Physical Unclonable Functions (PUFs), such as Ring Oscillator (RO) PUFs, have emerged as key hardware security primitives by providing unique, unpredictable, and reliable responses, addressing security challenges related to key storage and device authentication. To ensure robustness, RO-PUF designs traditionally resort to analog-driven implementation flows, which suffer from high design overhead and limit scalability across technology nodes. We present a configurable RO-PUF design integrated following a standard-cell-based, fully digital semi-custom-design methodology, significantly reducing design effort while enabling portability across planar CMOS technologies. The proposed architecture integrates fully on-chip Helper Data Algorithm (HDA) combined with a lightweight Error Correction Code (ECC) to support key generation, obfuscation, and recovery. Furthermore, it was fabricated in TSMC 65 nm technology and extensively characterized across diverse operating conditions, including process, voltage, and temperature (PVT) variations, achieving state-of-the-art metrics.
Conferences
VLSI Integration of a Physical Unclonable Function as identifier and key generator
P. Ortega-Castro, M.C. Martinez-Rodriguez and P. Brox
Conference · Demo in the University Fait at DATE (Design, Automation and Test in Europe Conference) 2025, Marzo 31-Abril 2, 2025 (https://www.date-conference.com)
abstract
Abstract not available
VLSI integration of a RO-based PUF into a 65 nm technology
P. Ortega-Castro, L.F. Rojas-Muñoz, J.M. Mora-Gutiérrez, P. Brox and M.C. Martínez-Rodríguez
Conference · IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
abstract
doi
Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO oscillating frequencies and generate unique identifiers (ID). Its structure makes it suitable for, both, FPGA and ASIC applications. This paper presents a RO-PUF implementation using a semi-custom design methodology in TSMC 65 nm technology which has been validated through the entire design process, manufactured and experimentally characterized. Results show a good performance and robustness against temperature and voltage variations while obtaining up to three bits from each execution to generate digital IDs.
Cryptographic Security Through a Hardware Root of Trust
L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, E. Camacho-Ruiz, P. Navarro-Torrero, A. Karmakar, C. Fernández-García, E. Tena-Sánchez, F.E. Potestad-Ordóñez, A. Casado-Galán, P. Ortega-Castro, A.J. Acosta-Jiménez, C.J. Jiménez-Fernández and P. Brox
Conference · Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024
abstract
doi
This work presents a novel approach to a Hardware Root-of-Trust that leverages System-on-Chip technology for the implementation of hardware cryptographic functions. Taking advantage of the processing power of a System-on-Chip, the solution established promotes hardware-based security solutions over software-only solutions. The proposed Root-of-Trust, developed around a Xilinx Zynq-7000 SoC device, integrates components based on cryptographic algorithms and physical phenomena. This innovative Root-of-Trust is tailored to support a spectrum of security tasks within cryptographic systems, including device-specific identifiers and keys, encryption and decryption, hashing, and signature generation and verification. The study adopts a unified design methodology, capitalizing on collaborative efforts to efficiently develop hardware primitives that significantly contribute to enhancing security in computing environments. Aligned with the advantages of reconfigurable hardware, this Hardware Root-of-Trust addresses the critical need for robust hardware-level security and introduces a set of countermeasures to fortify the design against potential threats.
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