Spanish National Research Council · University of Seville
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Author: Léger, Gildas
Year: Since 2002
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Yield recovery of mm-wave power amplifiers using variable decoupling cells and one-shot statistical calibration
F. Cilici, M.J. Barragan, S. Mir, E. Lauga-Larroze, S. Bourdel and G. Leger
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
[abstract]
Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

Assessing AMS-RF test quality by defect simulation
V. Gutierrez, A. Gines and G. Leger
Journal Paper - IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp 55-63, 2019
IEEE    DOI: 10.1109/TDMR.2019.2894534    ISSN: 1530-4388    » doi
[abstract]
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on practical cases of study that it is beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality. The computational burden of defect and fault simulations is taken into account and accurate statistical estimates of defect and fault escapes are provided to allow safe early stopping of the simulations.

Single Event Transient injection in large mixed-signal circuits
V. Gutierrez and G. Leger
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
Abstract not avaliable

AMS-RF test quality: Assessing defect severity
V. Guiterrez, A. Gines and G. Leger
Conference - IEEE Int. Symposium on On-Line Testing and Robust System Design IOLTS 2018
[abstract]
In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on a practical case of study that it may be beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality.

Mixed-signal test automation: Are we there yet?
G. Leger and M.J. Barragan
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
Nowadays, traditional specification-based functional test continues to be the golden standard for AMS-RF production test. However, the wide variety of AMS-RF circuits and the huge number of their associated specifications make functional test automation a challenging task. Obviously, testing an RF transceiver is completely different from testing an Analog-to-Digital Converter, and they actually require different dedicated test equipment. That being said, there exist some attempts to systematic functional test for some circuit families, essentially Built-In Self Test (BIST) approaches [1]-[5]. BIST techniques move the test problem to the design stage by embedding test instruments together with the Device Under Test (DUT). The path to automation of such approaches would parallel that of ‘conventional ’ automated design synthesis [6] since co-design is mandatory.

Why is systematic AMS-RF test not there yet?
G. Leger and M. Barragán
Conference - How to survive in an unreliable world, IEEE CEDA Spain Chapter / NANOVAR Workshop 2017
[abstract]
For many years, both the academy and the industry have been pursuing the goal of systematic, and possibly automated, AMS-RF test. Many approaches tried to parallel what had been successful for digital circuit, where test considerations are fully embedded in the design flow. In this talk, we will briefly review what has been done in the field of AMS-RF test, what is the current state-of-the-art and finally, we will try to point out what is the major bottleneck for systematic test methodologies.

Likelihood-sampling adaptive fault simulation
G. Leger and A. Gines
Conference - International Mixed-Signals Testing Workshop IMSTW 2017
[abstract]
This paper builds upon recent developments that argue for a fault simulation based on defect-likelihood sampling. It first questions, with a number of synthetic experiments, the premises of this approach and offers an alternative simple mechanism for the random selection of defects. Then, it introduces a new layer of variability with the parametrization of the opens and shorts resistivity while keeping the computational cost overhead low by means of an adaptive strategy.

On the limits of machine learning-based test: A calibrated mixed-signal system case study
M.J. Barragan, G. Leger, A. Gines, E. Peralias and A. Rueda
Conference - Design, Automation and Test in Europe DATE 2017
[abstract]
Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system -i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

Brownian distance correlation-directed search: A fast feature selection technique for alternate test
G. Leger and M.J. Barragan
Journal Paper - Integration, the VLSI Journal, vol. 55, pp 401-414, 2016
ELSEVIER    DOI: 10.1016/j.vlsi.2016.05.003    ISSN: 0167-9260    » doi
[abstract]
Machine-learning indirect test relies on powerful statistical algorithms to build prediction models that relate cheap measurements to costly performance metrics. Though many works in the past have been focused on proposing different models or on ways to improve the reliability of the results, it appears that the main bottleneck of the approach is the definition of an information-rich input space. Finding the appropriate measurements that are both cheap and meaningful is a task that has not yet been automated. In this framework, feature selection is a necessary tool to explore possible candidates. In this paper a hybrid method is proposed that lay between filtering and wrapper-based methods, trying to strike the right balance between accuracy and speed for the particular case of Alternate Test.

A Compact R-2R DAC for BIST Applications
A. Rabal, A. Otin, I. Urriza, A.J. Gines, G. Leger and A. Rueda
Conference - International Mixed-Signals Testing Workshop IMSTW 2016
[abstract]
This paper presents the implementation of a compact R-2RDigital-to-Analog Converter (DAC) for BIST applications of analog and mixed-signal circuits. It focuses on evaluating the DAC design requirements and its possibilities in structural and alternate test methodologies. More concretely, the aim of the paper is the low-cost generation of digitally programmable DC voltages for parametric deviation injection. For the sake of validation, these voltages will be considered to modify the voltage references of bias circuit or cascode voltages in op-amps. The DAC has been implemented in a UMC 65nm LL CMOS process, and comprises a front-end passive R-2R ladder followed by an active buffer based on a two-stage amplifier with Miller's compensation. Special care has been taken in the resistors ladder layout, as a critical parameter to minimize the mismatch impact due to process variations and maximize the final static behavior. The total power consumption and overall die area for the R-2R DAC ladder are 120 μW and 88x64 μm2, respectively. The op-amp design could be optimized depending on the load and driving requirements.

Design Trade-offs for On-chip Driving of High-speed High-performance ADCs in Static BIST Applications
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference - International Mixed-Signals Testing Workshop IMSTW 2016
[abstract]
This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed highperformance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in the order of 12 bits and 80 Msps of sampling frequency.

Guest Editorial: Analog, Mixed-Signal and RF Testing
G. Leger and C. Wegener
Journal Paper - Journal of Electronic Testing, vol. 32, no. 4, pp 405-406, 2016
SPRINGER    DOI: 10.1007/s10836-016-5608-y    ISSN: 0923-8174    » doi
[abstract]
Analog, Mixed-Signal and Radio-Frequency circuits represent a small fraction of the total volume of semiconductor production. However, they pose very specific challenges and headaches -more often than not- to both design and test engineers. For complex systems, the costs of AMS-RF test and test development can lead to a bottleneck in industrialization of a product. This is the reason why a rather small but active community meets on a yearly basis at the International Mixed-Signal Testing Workshop (IMSTW). In 2015 the workshop was held in Paris and brought a number of interesting proposals to public discussion. As program chairs of IMSTW, we decided to invite submissions for a JETTA special issue with a call-for-papers open to contributions reaching beyond the workshop community. Therefore, some papers in this special issue are extended versions of IMSTW papers and others are new contributions.

Linearity Test of High-speed High-performance ADCs using a Self-Testable On-chip Generator
A.J. Gines, E. Peralias, G. Leger, A. Rueda, G. Renaud, M.J. Barragan and S. Mir
Conference - IEEE European Test Symposium ETS 2016
[abstract]
This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutionsin the order of 13 bits and 100Msps of sampling frequency.

Questioning the reliability of Monte Carlo simulation for machine-learning indirect test validation
G. Leger and M.J. Barragán
Conference - IEEE European Test Symposium ETS 2016
[abstract]
Machine learning indirect test -also known as Alternate Test- has shown its potential to reduce test cost while maintaining an interpretation of the results compatible with the standard specification-based test. Since its introduction, many papers have been proposed to refine the idea and address its shortcomings. In particular, the issue of early validation of the test at the design stage has been considered and some methodologies have been proposed to assess test quality. These methodologies rely essentially on Monte Carlo simulations.
In this paper, we propose a set of thought experiments to show that small inaccuracies and variations in the Monte Carlo models included in current technology process design kits may have a significant impact in the validation of machine learning indirect test, in particular in the estimation of test quality metrics. Despite of this, machine learning indirect test has actually succeeded in actual industrial cases. Some hints are thus given to the conditions that the test has to fulfill to guarantee good results.

Feature selection for Alternate Test using wrappers: Application to an RF LNA case study
M.J. Barragán and G. Léger
Conference - Design, Automation and Test in Europe DATE 2015
[abstract]
Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the Alternate Test strategy. Alternate test is an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning techniques are then used to map signatures and performances. One key point that still remains as an open problem is the conception of adequate simple measurement candidates. This work presents efficient algorithms for selecting information rich signatures.

Efficient strategies for feature selection and discovery in machine-learning test applications
M. Barragan and G. Leger
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
Abstract not avaliable

A Hybrid Method for Feature Selection in the Context of Alternate Test
G. Leger and M. J. Barragan
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
[abstract]
Machine-learning test strategy has been developed in the last decade as an alternative to costly specification-driven tests for Analog, Mixed-Signal and RF circuits (AMS-RF). The concept is simple: powerful algorithms are used to map simple measurements onto specifications. But the proper execution requires an information-rich input space. This paper presents an efficient hybrid algorithm to select the best subset of signatures (or features) among a large number of candidates and shows how it can be applied to eventually propose the development of new ones.

A hybrid method for feature selection in the context of Alternate Test
G. Leger and M.J. Barragan
Conference - Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design SMACD 2015
[abstract]
Machine-learning test strategy has been developed in the last decade as an alternative to costly specification-driven tests for Analog, Mixed-Signal and RF circuits (AMS-RF). The concept is simple: powerful algorithms are used to map simple measurements onto specifications. But the proper execution requires an information-rich input space. This paper presents an efficient hybrid algorithm to select the best subset of signatures (or features) among a large number of candidates and shows how it can be applied to eventually propose the development of new ones.

Boundary cost optimization for Alternate Test
G. Leger
Conference - IEEE European Test Symposium ETS 2015
[abstract]
Alternate Test has demonstrated in the last decade that advanced machine-learning tools can leverage the accuracy gap between functional test and indirect, or model-based, test. If a regression approach is taken, a model should be trained for each specification. The advantage is that the results are interpreted just like performance measurements but the drawback is that accuracy is required over the full variation range. On the other hand, a classification approach can be seen as a wiser solution since it locates the pass/fail boundary, which inherently contains all the specification information, in the cheap measurement space. Cost optimization due to imbalance between test escape and yield loss is usually handled by guard-banding on specifications. This is straightforward to translate to regression-based Alternate Test but not for classification-based.
This paper shows that two different asymmetric approaches consistently outperforms an off-the-shelf symmetric algorithm. The first technique is based on manipulating the decision threshold while the second technique directly builds an optimized pass-fail boundary by considering different costs to penalize test escapes and yield losses.

Special session. Hot topics: Statistical test methods
M. Barragan, G. Leger, F. Azais, S. Blanton, A. Singh and A. Sunter
Conference - IEEE VLSI Test Symposium VTS 2015
[abstract]
The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

Combining Adaptive Alternate Test and Multi-Site
G. Leger
Conference - Design, Automation and Test in Europe DATE 2015
[abstract]
Testing analog, mixed-signal and RF circuits represents one of the main cost components for complex SoCs. Multisite Testing is widely accepted as a straightforward technique to reduce the effective test time. This paper shows that an adaptive Alternate Test approach can be compatible with a multisite strategy. The proposed solution consists in ordering offline the signatures acquisition sequence and training incremental regression models for each new feature. These models can be used to diagnose the circuit as good, provided that the estimate of the performance is larger than the specification plus a guard-band related to the model error. If all the sites are diagnosed as good, the test program can be halted before completion. This decision is taken on-line and makes this scheme adaptive. We provide an analytical study of the expected test time reduction and of the test escape penalty that is incurred. Results obtained from post-layout MonteCarlo simulations of an LNA demonstrate the validity of the approach and show that significant test time improvements can be obtained, even for large number of sites, whenever the manufacturing yield is sufficiently high.

A Procedure for Alternate Test Feature Design and Selection
M.J. Barragan and G. Leger
Journal Paper - IEEE Design & Test, vol. 32, no. 1, pp 18-25, 2015
IEEE    DOI: 10.1109/MDAT.2014.2361722    ISSN: 2168-2356    » doi
[abstract]
This paper is a practical illustration of the adoption of alternate tests based upon the judicious selection of the set of parameters to be considered for design as well as to be observed subsequently. The notion of signatures is introduced, and their ability to predict design accuracy is analyzed. The application is demonstrated for an RF LNA circuit.

On-chip sinusoidal signal generation with harmonic cancelation for analog and mixed-signal BIST applications
M. Barragan, G. Leger, D. Vazquez and A. Rueda
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 82, no. 1, pp 67-79, 2015
SPRINGER    DOI: 10.1007/s10470-014-0456-0    ISSN: 0925-1030    » doi
[abstract]
This work presents a technique for the on-chip generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique consists of a modified low-order analog filter, that provides a sinusoidal output as response to a DC input, combined with a harmonic cancellation strategy to improve the linearity of the generated signal. The proposed generator has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. An integrated prototype designed in a 180 nm CMOS technology is presented in order to show the feasibility of the technique. Results obtained from the prototype show a THD around -80 dB.

Single Event Transients trigger instability in Sigma-Delta Modulators
D. Malagon, J.M. de la Rosa, R. del Río and G. Leger
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2014
[abstract]
In this paper we emulate the errors caused by SET in a Flexible 4th-Order Sigma-Delta Modulator with DC-to-44MHz Tunable Center Frequency in 1.2-V 90-nm CMOS. We identify the virtual ground of the integrators as a sensitive node and show that a charge injection may drive the modulator into long-term instability.

Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
A.J. Ginés, G. Leger, E. Peralías and A. Rueda
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2014
[abstract]
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.

Doubly-Segmented Current-Steering DAC Calibration
G. Léger
Conference - Design and Technology of Integrated Systems in Nanoscale Era DTIS 2014
[abstract]
This paper addresses the calibration of segmented current-steering Digital-to-Analog Converters (DACs). In many design cases, current-steering DACs are divided into a thermometer-coded unary section and a binary section. This is done mostly for dynamic reasons. However, the decisions on the segmentation also impact an eventual static calibration. In this paper, we show that the introduction of an intermediate thermometer-coded unary section allows to perform static calibration to a high resolution levels without compromising the dynamic behavior. The individual current sources of the two unary sections are calibrated against two current references and the gain mismatch between sections is calibrated through the biasing circuit.

Sigma-Delta Testability for Pipeline A/D Converters
A. Gines and G. Leger
Conference - Design Automation and Test in Europe DATE 2014
[abstract]
Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixedsignal blocks, particularly if digital correction and calibration is considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplification as integrators with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that do not require any extra pin. In addition, digital test techniques developed for ΣΔ modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18μm CMOS process is used as a case of study for the introduction of the DfT modifications.

A Design for yield approach for redundant flash ADC
H. Youssef Darweesh, G. Leger and A. Rueda
Conference - European Workshop on CMOS Variability VARI 2013
[abstract]
For the design of high-speed ADCs, the traditional speed-accuracy trade-off can only be solved at the expense of power consumption. Using fast small transistors takes full advantage of technology scaling but induces large amounts of random variability. In the case of FLASH ADCs comparator redundancy has been proposed as a way to relax this speedaccuracy trade-off. In this paper, the design of a FLASH ADC using comparator redundancy is addressed from a statistical viewpoint. Closedform expressions for the yield are derived as functions of the redundancy system variables. These expressions bring the possibility to compute adequate cost functions and rapidly explore the design space to select an optimal point. The case of a 6-bit ADC implemented in a 0,18μm CMOS technology is used as a practical application example of this methodology.

Efficient selection of signatures for analog/RF alternate test
M.J. Barragan and G. Leger
Conference - IEEE European Test Symposium ETS 2013
[abstract]
This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model. These two figures evaluate the quality of each signature based on its Brownian distance correlation to the target specifications, and on its local distribution in the proximities of the pass/fail decision boundaries. The proposed methodology is illustrated by its direct application to a DC-based alternate test for LNAs.

Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique
M.J. Barragan, G. Leger, D. Vazquez and A. Rueda
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2013
[abstract]
This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. The proposed generation technique is based on a modified analog filter, that provides a sinusoidal output as the response to a DC input, combined with a harmonic cancellation technique. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. Simulation results are provided in order to validate the proposed generation technique.

A 0.2pJ/conversion-step 6-bit 200MHz flash ADC with redundancy
H. Darwish, G. Léger and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2012
[abstract]
In this paper, a 200MHz 6-bit Flash analog-to-digital converter (ADC) is presented. The principal objective is to obtain a digital-friendly converter. Hence, small and simple latched comparators are used and redundancy allows reducing the offset down to an acceptable level. This obviously requires calibration but reduces power consumption, since small size transistors can be used and the unused comparators are powered down. The proposed ADC is designed in UMC 0:18μm CMOS technology. Full electrical simulations show that the ADC reaches an effective number of bits (ENOB) of 5.3 associated to a signal-to-noise-anddistortion ratio (SNDR) is 33dB. The converter consumes only 1.56mW and has figure-of-merit (FoM) of 0.2 pJ / conversion step.

Multi-condition alternate test of analog, mixed-signal, and RF systems
M.J. Barragán-Asián, G. Léger and J.L. Huertas-Díaz
Conference - IEEE Latin American Test Workshop LATW 2012
[abstract]
This work proposes a generic path to improve Alternate Test strategies. It demonstrates that multi-condition test increases the amount of information present in the test data and consequently decreases the prediction error of the trained models. The ambition of this paper is to be a methodological contribution to the field of AMS-RF test, and formal guidelines are provided that justify the interest of the approach. For the sake of validation, the proposed methodology has been applied to several alternate test strategies for analog, mixed signal, and RF circuits. Promising results are found for the following case studies: an analog filter, a ΣΔ A/D converter, and an RF LNA.

OBT for settling error test of sampled-data systems using signal-dependent clocking
M.J. Barragán-Asián, G. Léger and J.L. Huertas-Díaz
Conference - IEEE European Test Symposium ETS 2012
[abstract]
This work presents a modification of traditional Oscillation-Based Test schemes for sampled-data systems. This new test scheme is based on doubling the sampling frequency when the oscillation changes its sign. This way, the DC level of the output oscillation signal becomes a simple signature sensitive to the settling errors in the device under test and to its oscillation features. The proposed technique is illustrated on a switched-capacitor second-order lowpass filter. This case study is used to show the sensitivity of the proposed signature to the linearity of the DUT. Electrical simulation results are provided to validate the proposal. © 2012 IEEE.

Improving the accuracy of RF alternate test using multi-VDD conditions: Application to envelope-based test of LNAs
M.J. Barragán-Asián, R. Fiorelli-Martegani, G. Leger, A. Rueda and J.L. Huertas-Díaz
Conference - Asian Test Symposium ATS 2011
[abstract]
This work demonstrates that multi-VDD conditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

Alternate test of LNAs through ensemble learning of on-chip digital envelope signatures
M.J. Barragán, R. Fiorelli, G. Léger, A. Rueda and J.L. Huertas
Journal Paper - Journal of Electronic Testing-Theory and Applications, vol. 27, no. 3. pp 277-288, 2011
SPRINGER    DOI: 10.1007/s10836-010-5193-4    ISSN: 0923-8174    » doi
[abstract]
This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique.

Regression Modeling for Digital Test of Sigma-Delta Modulators
G. Leger and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2010
[abstract]
Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.

On chopper effects in discrete-time ΣΔ modulators
G. Leger, A.J. Ginés-Arteaga, E. Peralías-Macias and A. Rueda
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, no. 9, pp 2438-2449, 2010
IEEE    DOI: 10.1109/TCSI.2010.2043996    ISSN: 1549-8328    » doi
[abstract]
Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.

Random Chopping in Sigma-Delta Modulators
G. Léger, A. Gines, E. Peralias and A. Rueda
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2009
[abstract]
ΣΔ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result ΣΔ modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of applications and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Frequency-shaped random chopping has been proposed to minimize the impact of reference voltage interference. It is shown in this paper that the chopper signal is not the only term that modulates the offset and Flicker noise and that unwanted crosstalk can significantly degrade the performance of the modulator.

Low-cost digital detection of parametric faults in cascaded sigma delta modulators
G. Léger and A. Rueda
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 7, pp 1326-1338, 2009
IEEE    DOI: 10.1109/TCSI.2008.2006648    ISSN: 1549-8328    » doi
[abstract]
The test of sigma-delta modulators is cumbersome due to the high performance that they reach. Moreover, technology scaling trends raise seRíous doubts on the intradie repeatability of devices. An increase of variability will lead to an increase in parametric faults that are difficult to detect. In this paper, a design-oriented testing approach is proposed to perform a simple and low-cost detection of variations in important design variables of cascaded Sigma Delta modulators. The digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. A study is presented to tailor signature generation, with test-time minimization in mind, as a function of the desired measurement precision. The developments are supported by experimental results that validate the proposal.

Test of ΣΔ converters
G. Leger and A. Rueda
Book Chapter - Test and Diagnosis of Analogue, Mixed-Signal and RF Integrated Circuits, pp 235-276, 2008
IET    ISBN: 978-0-86341-745-0    
[abstract]
In this chapter, we have tried to provide insights into ΣΔ modulator tests. It has been shown that the ever-increasing levels of functionality integration, the ultimate expression of which is SoC, raise new problems on how to test embedded components such as ΣΔ modulators. These issues may even compromise the test feasibility, or at least they may displace test time from its prominent position in the list of factors that determine the overall test cost. It is clear that considerable research is still necessary to produce a satisfying solution, but the first steps are encouraging. In particular, we believe that solutions based on behavioural model-based BIST may greatly simplify the test requirements.

Digital Tests for Sigma-Delta Modulators
G. Léger
Thesis - Date of defense: 19/03/2007
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
Abstract not avaliable

Experimental validation of a fully digital BIST for cascaded Sigma Delta modulators
G. Léger and A. Rueda
Conference - IEEE European Test Symposium ETS 2006
DOI:     » doi
[abstract]
This work presents a Sigma Delta modulator prototype that gives experimental support to a fully digital Built-In Self-Test scheme. The goal of the proposed BIST is to provide digital signatures that are directly related to some important behavioural parameters of Sigma Delta modulators. As a result, parametric drafts can be detected before they seRíously affect performance. The modulator required modifications are minimal and few gates would be necessary to implement a full BIST version, enabling infield self-test.

A tissue impedance measurement chip for myocardial ischemia detection
A. Yufera, A. Rueda, J.M. Muñoz, R. Doldán, G. Léger and E.O. Rodríguez-Villegas
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 12, pp 2620-2628, 2005
IEEE    DOI: 10.1109/TCSI.2005.857542    ISSN: 1057-7122    » doi
[abstract]
In this paper, the design of a specific integrated circuit for the measurement of tissue impedances is presented. The circuit will be part of a multi-micro-sensor system intended to be used in cardiac surgery for sensing biomedical parameters in living bodies. Myocardium tissue impedance is one of these parameters which allows ischemia detection. The designed chip will be used in a four-electrode based setup where the effect of electrode interfaces are cancelled by design. The chip includes a circuit to generate the stimulus signals (sinusoidal current) and the circuitry to measure the magnitude and phase of the tissue impedance. Several integrated circuits have been designed, fabricated and tested, in a 0.8-mu m CMOS process, working at 3 V of power supply. Some of them including building blocks, and other with the whole measurement system. Experimental tests have shown the circuit feasibility giving expected results for both in-vitro and in-vivo test conditions.

Sine-wave signal characterization using square-wave and Sigma Delta-modulation: Application to mixed-signal BIST
D. Vázquez, G. Huertas, A. Luque, M.J. Barragán, G. Léger, A. Rueda and J.L. Huertas
Journal Paper - Journal of Electronic Testing-Theory and Applications, vol. 21, no. 3, pp 221-232, 2005
SPRINGER    DOI: 10.1007/s10836-005-6352-x    ISSN: 0923-8174    » doi
[abstract]
This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. It is based on a double-modulation, square-wave and sigma-delta, together with a simple Digital Processing Algorithm. It leads to an efficient and robust approach very suitable for BIST applications. In this line, some considerations for on-chip implementation are addressed together with simulation results that validate the feasibility of the proposed approach.

Oscillation-based test strategies
G. Huertas-Sánchez, G. Leger, D. Vázquez, A. Rueda and J.L. Huertas
Book Chapter - Test and Design-For-Testability in Mixed-Signal Integrated Circuits, pp 259-298, 2004
SPRINGER    DOI: 10.1007/978-0-387-23521-9_9    ISBN: 978-1-4419-5422-0    » doi
[abstract]
This chapter aims to present a structural test methodology using the so-called OBT technique. The conceptual bases of the OBT approach are presented as well as many practical details on its application to practical integrated circuits.

A digital test for first-order sigma delta modulators
G. Léger and A. Rueda
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
This paper presents a digital structural test for first order Sigma-Delta modulators. A periodic digital sequence is used as a stimulus to obtain a signature of the integrator leakage. This parameter is known to be related to the modulator precision and its estimation is of great importance to assess if the modulator works as expected. As the proposed technique is fully digital, it is specially suitable to test modulators embedded in complex Mixed-Signal circuits.

Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs
G. Léger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper - IEEE Transactions on Circuits and Systems I, vol. 51, no. 1, pp 140-150, 2004
IEEE    DOI: 10.1109/TCSI.2003.821301    ISSN: 1057-7122    » doi
[abstract]
Using several analog-to-digital converters (ADCs) in parallel with convenient time offsets is considered an efficient way to push the speed limits of data acquisition systems. However, a serious drawback of this time-interleaving technique is that any mismatch between the channels will damage the precision. This paper gives a probabilistic description of the problem, studying the impact of time skews, gain, and offset mismatches. The probability density function of both signal-to-noise ratio (SNR) and spurious-free-dynamic range (SFDR) are explicitly calculated, giving access to important statistical parameters. It is shown that the SNR and SFDR dispersion should not be neglected in making practical considerations for design decisions. © 2004 IEEE.

Method for parameter extraction of analog sine-wave signals for mixed-signal built-in-self-test applications
D. Vázquez, G. Léger, G. Huertas, A. Rueda and J.L. Huertas
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
This paper presents a method for extracting, in the digital domain, the main characteristic parameters of an analog sine-wave signal. The required circuitry for on-chip implementation is very simple and robust, which makes the present approach very suitable for BIST applications. Solutions in this sense are addressed together with simulation results that validate the feasibility of the proposed approach.

Digital test for first-order sigma delta modulators
G. Léger and A. Rueda
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
This paper presents a digital structural test for first order Sigma-Delta modulators. A peRíodic digital sequence is used as a stimulus to obtain a signature of the integrator leakage. This parameter is known to be related to the modulator precision and its estimation is of great importance to assess if the modulator works as expected. As the proposed technique is fully digital, it is specially suitable to test modulators embedded in complex Mixed-Signal circuits.

Cascade ΣΔ modulator with digital correction for finite amplifier gain effects
G. Léger and A. Rueda
Journal Paper - Electronics Letters, vol. 40, no. 21, pp 1322-1323, 2004
IEEE    DOI: 10.1049/el:20046388    ISSN: 0013-5194    » doi
[abstract]
A simple and fully digital solution to correct the effect of amplifier finite gain in cascade SigmaDelta modulators is presented. The main contribution of this study is a simple digital method to evaluate the integrator pole errors, which are further taken into account to modify the reconstruction filter. The method is applied to a 2-1 cascade modulator.

Digital test for the extraction of integrator leakage in first- and second-order sigma delta modulators
G. Léger and A. Rueda
Journal Paper - IEEE Proceedings-Circuits Devices and Systems, vol. 151, no. 4, pp 349-358, 2004
IEEE    DOI: 10.1049/ip-cds:20040558    ISSN: 1350-2409    » doi
[abstract]
A digital technique for evaluating the integrator leakage within first- and second-order EA modulators is proposed. It involves a very small amount of hardware, which makes it specially suitable for built-in self-test (BIST) implementation. Integrator leakage is known to be related to the converter precision and, hence, the proposed test technique serves as an indirect test of the signal-to-noise ratio (SNR) degradation. As an additional result, a strategy has been derived for digitally correcting the SNR loss due to integrator leakage in cascaded modulators.

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits
D. Vázquez, G. Huertas, G. Leger, E. Peralías, A. Rueda and J.L. Huertas
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 201-211, 2002
SPRINGER    DOI: 10.1023/A:1021276218012    ISSN: 0925-1030    » doi
[abstract]
This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.

Practical solutions for the application of the oscillation-based-test in analog integrated circuits
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper presents practical solutions for solving the problems arising when applying Oscillation-Based-Test. It is devoted to discuss a practical on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

SNR probability in time-interleaved ADCs with random channel mismatches
G. Léger, E. Peralías and A. Rueda
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
One of the ways to push the speed limits of Analog to Digital Converters (ADCs) is to time-interleave several channels. However, any mismatch between channels degrades the converter resolution. This work is a deep study of the impact of random time skew, gain and offset mismatches on the Signal-to-Noise-Ratio (SNR). The SNR probability density function (PDF) is determined as a function of both these errors and the number of channels. It provides valuable information about the performance margins that could be expected in a design.

Practical solutions for the application of the oscillation-based-test: Start-up and on-chip evaluation
D. Vázquez, G. Huertas, G. Léger, A. Rueda and J.L. Huertas
Conference - IEEE VLSI Test Symposium VTS 2002
[abstract]
This paper presents practical solutions for two of the main topics arising when applying Oscillation-Based-Test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.

An integrated circuit for tissue impedance measure
A. Yufera, G. Léger, E.O. Rodríguez-Villegas, J.M. Muñoz, A. Rueda, A. Ivorra, R. Gómez, N. Noguera and J. Aguilo
Conference - Conference on Microtechnologies in Medicine & Biology IEEE-EMB 2002
[abstract]
In this paper, the design of aa Integrated Circuit (IC) for the measurement of tissue impedance is presented. The chip is intended to be used in monitoring biomedical parameters in living bodies. Tissue impedance is one of these parameters which allows ischemia monitoring. The designed IC is used in a four-electrode based set-up in order to minimize the effect of electrode-electrolyte interface impedance. A needle shaped probe which contains the four electrodes for the impedance measurement and Integrated Circuits (ICs) required for excitation and measurement purpose have been designed, fabricated and tested in-vivo. The IC has been fabricated in a 0.8mum CMOS process, working at 3V of power supply. Test results have shown the circuit feasibility.

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