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Author: Parra Fernández, M. del Pilar
Year: Since 2002
All publications
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, C. Baena and P. Parra
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based on introducing redundancy, which leads to a greater consumption of resources or a longer processing time. This article presents how the introduction of placement restrictions on ciphers can make it difficult to inject faults by altering the clock signal. It is therefore a countermeasure that neither increases the consumption of resources nor the processing time. This mechanism has been tested on FPGA implementations of the Trivium cipher. Several tests have been performed on a Spartan 3E device from Xilinx and the experimental measurements have been carried out with ChipScope Pro. The tests showed that an adequate floorplanning is a good countermeasure against these kind of attacks.

Aplicaciones docentes del diseño de un picoprocesador
C.J. Jiménez, C. Baena, P. Parra and M. Valencia
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
[abstract]
El conocimiento de la estructura interna y del mecanismo de funcionamiento de microprocesadores es una parte muy importante en la formación de ingenieros en electrónica e informática. Este conocimiento puede profundizarse con experiencias de diseño de procesadores, que reúnen además muchos aspectos vinculados a otros conocimientos básicos. Sin embargo, debido a su complejidad, el diseño de procesadores comerciales no es efectivo desde un punto de vista docente. En la presente comunicación presentamos una experiencia de diseño en VHDL de un procesador muy sencillo que demuestra los múltiples aprendizajes que suponen para el alumno.

Revisting clock-gating: the common place for power reduction
J. Castro, P. Parra and A.J. Acosta
Conference - Iberchip XVI Workshop IWS 2010
[abstract]
Abstract not avaliable

Master-slave flip-flop optimization for fine-grained clock-gating applications
J. Castro, P. Parra and A.J. Acosta
Conference - IEEE Latin American Symposium on Circuits and Systems LASCAS 2010
[abstract]
Abstract not avaliable

Ruido de conmutación en circuitos integrados digitales CMOS
P. Parra-Fernández
Thesis - Date of defense: 30/04/2010
UNIVERSIDAD DE SEVILLA, IMSE-CNM    
[abstract]
Abstract not available

An improved differential pull-down network logic configuration for DPA resistant circuits
J. Castro, P. Parra and A.J. Acosta
Conference - International Conference on Microelectronics ICM 2010
[abstract]
Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation have been widely used. However, the right use of such circuits for secure applications needs not only a fully symmetric structure, but also removing any memory effect that could leak information. We propose an improved memory-less fully symmetric Xor/Xnor pull-down logic configuration, to be used with any differential technique, for immediate application in cryptographic secure applications.

Optimization of clock-gating structures for low-leakage high-performance applications
J. Castro, P. Parra and A.J. Acosta
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2010
[abstract]
Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilities of different CG-styles to save power at a flip-flop level, depending on the input activity, are analysed in this paper. Also, since conventional CG techniques usually do not take into account leakage power, some optimization procedures and guidelines are presented for leakage reduction. Focusing on those structures that do not need a latch to remove undesired transitions in gated clock, a leakage value of a fourth of the original one is achieved without degradation in timing performances.

Aplicación de técnicas de evaluación continua en grupos numerosos de alumnos
M.C. Baena-Oliva, M.J. Bellido-Díaz, A. Estrada-Pérez, J. Juan-Chico, S. Martín-Guillén, A.J. Molina-Cantero, E. Ostua-Aranguena, M.P. Parra-Fernández, O. Rivera-Romero, M.C. Romero-Ternero, J. Ropero-Rodríguez, P. Ruiz de Clavijo-Vázquez, G. Sánchez-Antón, M. Valencia-Barrero and J.M. Gómez-González
Book Chapter - Experiencia de Innovacion Universitaria (I) Curso 2006-2007, vol. 1, pp 350-365, 2009
ICE UNIVERSIDAD DE SEVILLA    ISBN: 978-84-86849-70-2    
[abstract]
Abstract not available

Switching noise optimization in the wake-up phase of leakage-aware power gating structures
J. Castro, P. Parra and A.J. Acosta
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2009
[abstract]
Leakage power dissipation has become a critical issue in advanced process technologies. The use of techniques to reduce leakage power consumption with negligible degradation in performances is needed for current and next technologies. Power gating is an effective technique to reduce leakage, taking advantage of the transistor stacking effect. However, the restoration from standby mode in power-gated circuits usually introduces a large amount of switching noise on the power supply and ground networks, that may affect the normal operation of circuits connected to the same polarizations. This paper analyzes the switching noise generated in the wake-up phase by several power-gating techniques, and their influence on the wake-up time. The best results are for the techniques that redistribute the amount of current flowing through the Vdd and Gnd nodes during the wake-up transition. Simulation results obtained on basic digital cells in a 90 nm technology show a variation of two in switching noise, while maintaining the same wake-up time and leakage saving

A switching noise vision of the optimization techniques for low-power synthesis
J. Castro, P. Parra, M. Valencia and A.J. Acosta
Conference - European Conference on Circuit Theory and Design ECCTD 2007
[abstract]
Different techniques used by a CAD tool that automatically optimize power consumption at gate-level circuit have been investigated in terms of switching noise generation. Such techniques, clock-gating, sleep-mode and others at a gate-level are usual saving power techniques, but are rarely applied to switching noise reduction. The reduction of peaks in supply current is of great interest due to their impact in sensitive parts of a circuit. An estimation of these peaks has been done at a gate level by two different tools (PrimePower and NanoSim, both from Synopsys) providing both the power supply current waveform along time, the average and the peak power for different synthesized circuits to check the effectiveness of such low-power techniques for switching noise reduction. As conclusions, although both tools provide an estimation of peak power, only NanoSim gives accurate values, and how these optimization techniques for low-power are, in general, useful for switching noise reduction.

Asymmetric clock driver for improved power and noise performances
J. Castro, P. Parra, M. Valencia and A.J. Acosta
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.

Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
A.J. Acosta, J.M. Mora, J. Castro and P. Parra
Conference - Conference on VLSI Circuits and Systems III, 2007
DOI: 10.1117/12.724162    » doi
[abstract]
The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire, as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also received much attention, because of the low power requirements of modem integrated systems. In the same way, the buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption, but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible impact on average power consumption.

A methodology for switching noise estimation at gate level
J. Castro, P. Parra and A.J. Acosta
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
This paper provides a simple methodology, based on available CAD tools, able of extracting valuable information on supply current curves, otherwise limited by the layout disposal, making it impracticable for the present high density circuits. The approach starts at HDL level, which will be automatically synthesized to a gate level being the peak power (one peak per clock cycle) measured at this level, giving an idea of the switching noise generated. Although an indirect method, it provides a quantitative value of noise valid for comparison between different proposals. To assess the methodology two different tools are used: PrimePower and NanoSim, both from Synopsys, that generate an average power and a peak power value. We will see that NanoSim is good for noise estimation but this is not the case of PrimePower.

Optimization of master-slave flip-flops for high-performance applications
R. Jiménez, P. Parra, J. Castro, M. Sánchez and A. Acosta
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2006
[abstract]
The design of high-performance master-slave flip-flops is of crucial importance in modem VLSI. The optimization of existing structures is necessary when the requirements of the flip-flop is for low-power, high-speed or low-noise applications. In this work, the optimization via transistor sizing of a well-known master-slave flip-flop is investigated. A detailed analysis of the flip-flop structure provides information useful for optimization, giving an optimum solution for an specific high-performance application.

Selective Clock-Gating for Low-Power Synchronous Counters
P. Parra, A.J. Acosta, R. Jiménez and M. Valencia
Journal Paper - Journal of Low Power Electronics, vol. 1, no. 1, pp 11-19, 2005
AMERICAN SCIENTIFIC PUBLISHERS    DOI: 10.1166/jolpe.2005.003    ISSN: 1546-1998    » doi
[abstract]
With current technologies and applications, dynamic power reduction is of great technological interest. The objective of this paper is to explore the applicability of clock gating techniques to counters in order to reduce the power consumption as well as to compare different power figures in counting structures. Counters are widely used in current VLSI digital circuits, and optimized low-power versions of them are of important concern. Different ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits with different synchronization schemes. The correct selection of bits where clock gating is applied and the suitable composition of groups of bits are essential but are not straightforward when applying this technique. We have found that some specific groupings of bits are the best options when applying clock gating to reduce power consumption.

Performance analysis of full adders in CMOS technologies
J. Castro, P. Parra and A.J. Acosta
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
Full adders are one of the most important building blocks in VLSI digital arithmetic. The area, electrical, timing, power consumed and noise generated characteristics of this cell are strongly dependent on the design technique. An exhaustive work taking into account the above parameters is done, and that complete analysis will be of utility for the community of digital designers. Emphasis will be done in power/noise figures, of most important concern in current CMOS mixed-signal design. The full adders considered are those using complementary CMOS, pass-transistor logic, double pass-transistor logic, and two versions based on CMOS transmission gate. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 mu m CMOS technology. The main results obtained are on one hand, the selection of a logic family for a specific application and, on the other hand, the selection of a specific full adder structure for an optimized parameter option -power, noise or speed.

Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
P. Parra, J. Castro, M. Valencia and A.J. Acosta
Conference - VLSI Circuits and Systems II, 2005
[abstract]
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.

Optimum Current/Voltage Mode Circuit Partitioning for Low Noise Applications
R. Jiménez-Naharro, P. Parra-Fernández, P.M. Sanmartin-Rodriguez and A.J. Acosta-Jimenez
Conference - Design of Circuits and Integrated Systems Conference DCIS 2003
[abstract]
Abstract not avaliable

A new hybrid CBL-CMOS cell for optimum noise/power application
R. Jiménez, P. Parra, P.M. Sanmartín and A.J. Acosta
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2003
[abstract]
The design of a new configurable hybrid current-mode/static CBL-CMOS cell is presented. This cell can be used in order to obtain the optimum partitioning between conventional and low-noise logic in the digital part of a mixed-signal circuit, resulting in a optimum power/noise solution. This new cell has been compared with the original logic families obtaining acceptable results with low hardware cost. A combinational multiplier has been designed as a demonstrator example of the utility of the proposed cells.

Design of Synchronous Counters for Low Noise Low Power Applications Using Clock Gating Techniques
P. Parra-Fernández, A.J. Acosta-Jimenez and M. Valencia-Barrero
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2002
[abstract]
Abstract not avaliable

A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
R. Jiménez, P. Parra, P. Sanmartín and A.J. Acosta
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2002
[abstract]
In this comunication, a new technique to generate flip-flops based on differential structures is presented. This technique is based on the modification of size in transistors of existing differential latches. The limitations of the differential structures to apply this technique are few, so the range of application is high. The main application field is in mixed-signal analog-digital circuits, due to the low switching noise generated by these flip-flops. In this parameter, the behavior is similar in both the proposed flip-flop and the original structure, and better than existing flip-flops.

High-performance edge-triggered flip-flops using weak-branch differential latch
R. Jiménez, P. Parra, P. Sanmartín and A.J. Acosta
Journal Paper - Electronics Letters, vol. 38, no. 21, pp 1243-1244, 2002
IEEE    DOI: 10.1049/el:20020864    ISSN: 0013-5194    » doi
[abstract]
A new technique to build edge-triggered flip-flops based on the use of 'weak' transistors is presented. This technique can be applied to most CMOS differential latches with only some further design considerations. Despite of hardware costs, resulting flip-flops are very suited for high-performance and low-noise applications.

Analysis of high-performance flip-flops for submicron mixed-signal applications
R. Jiménez, P. Parra, P. Sanmartín and A.J. Acosta
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 33, no. 2, pp 145-156, 2002
KLUWER ACADEMIC    DOI: 10.1023/A:1021216015286    ISSN: 0925-1030    » doi
[abstract]
This paper presents a detailed analysis of high-performance edge-triggered memory elements for deep submicron mixed-signal applications. The variations of the main parameters (power, delay, peak of supply current) with supply voltage, as well as timing restrictions have been studied. Especial emphasis has been given to switching-noise generation, an aspect of important concern in mixed-signal applications. We have analyzed the sources of switching noise, noticing that, the less noisy flip-flops are those based on differential structures.

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