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Author: Río Fernández, Rocío del
Year: Since 2002
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Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs
M. Moreno-Garcia, L. Pancheri, M. Perenzonr, R. del Rio, O. Guerra-Vinuesa and A. Rodriguez-Vazquez
Journal Paper - IEEE Sensor Journal, vol. 19, no. 14, pp 5700-5709, 2019
IEEE    DOI: 10.1109/JSEN.2019.2903937    ISSN: 1530-437X    » doi
[abstract]
The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due to their simplicity, a way to reduce the area occupied by the integrated electronics is the use of passive quenching circuits (PQCs) instead of active (AQCs) or mixed (MQCs) ones. However, the recharge phase in PQCs is slower, so the device can be retriggered before this phase ends. This paper studies the phenomena of afterpulsing and retriggering, depending on the characteristics of the SPADs and the working conditions. In order to do that, a test chip containing SPADs of different size has been characterized in several operating environments. A mathematical model has been proposed for fitting afterpulsing phenomenon. It is shown that retriggering can be also described in terms of this model, suggesting that it is linked to carriers trapped in the shallow levels of the semiconductor and that should be taken into account when considering the total amount of afterpulsing events.

Gaussian Pyramid: Comparative Analysis of Hardware Architectures
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
A comparison of architectures for hardware implementation of Gaussian image pyramids is addressed. Architectures consisting of a conventional sensor followed by digital processors are compared to architectures employing per-pixel embedded pre-processing structures. The later is potentially advantageous for enhancing throughput and reducing energy consumption, important features in the IoT context. These advantages are quantified considering different numbers of digital processors and ADCs, and different ADCs types. Results show that the advantages of pre-processing sensors are not granted by default, requiring proper architectural design. The methodology presented for comparing focal-plane and digital approaches allows for the assessment of focal-plane processing advantages.

Live Demonstration: Low-Power Low-Cost Cyber-Physical System for Bird Monitoring
A. García-Rodríguez, R. Rodríguez-Sakamoto, J. Fernández-Berni, R. del Río, J. Marín, M. Baena, J. Bustamante, R. Carmona-Galán and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
This live demonstration showcases a cyber-physical system tailored for inexpensive remote bird monitoring. A comprehensive analysis of the application requirements along with a tight system integration have given rise to a smart autonomous nest-box ready for deployment. This nest-box includes radiofrequency identification (RFID), a weighing scale, two temperature sensors, passive infrared devices (PIR), massive data storage and internet connection via mobile infrastructure. It is powered through a solar panel. The bill of materials has been diminished 77% with respect to the previous version of the nest-box whereas the power consumption has been reduced 84%.

Gaussian Pyramid: Comparative Analysis of Hardware Architectures
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2017
[abstract]
Abstract not avaliable

Gaussian Pyramid: Comparative Analysis of Hardware Architectures
F.D.V.R. Oliveira, J.G.R.C. Gomes, J. Fernandez-Berni, R. Carmona-Galan, R. del Rio and A. Rodriguez-Vazquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 64, no. 9, pp 2308-2321, 2017
IEEE    DOI: 10.1109/TCSI.2017.2709280    ISSN: 1549-8328    » doi
[abstract]
This paper addresses a comparison of architectures for the hardware implementation of Gaussian image pyramids. Main differences between architectural choices are in the sensor front-end. One side is for architectures consisting of a conventional sensor that delivers digital images and which is followed by digital processors. The other side is for architectures employing a non-conventional sensor with per-pixel embedded preprocessing structures for Gaussian spatial filtering. This later choice belongs to the general category of " artificial retina" sensors which have been for long claimed as potentially advantageous for enhancing throughput and reducing energy consumption of vision systems. These advantages are very important in the internet of things context, where imaging systems are constantly exchanging information. This paper attempts to quantify these potential advantages within a design space in which the degrees of freedom are the number and type of ADCs, single-slope, SAR, cyclic, Sigma Delta, and pipeline, and the number of digital processors. Results show that speed and energy advantages of preprocessing sensors are not granted by default and are only realized through proper architectural design. The methodology presented for the comparison between focal-plane and digital approaches is a useful tool for imager design, allowing for the assessment of focal-plane processing advantages.

Design of a Power-Efficient Widely-Programmable Gm-LC Band-Pass Sigma-Delta Modulator for SDR
A. Morgado, R. del Río, J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems, ISCAS 2016
[abstract]
This paper presents the design and layout implementation of a fourth-order band-pass continuous-time Sigma-Delta (SD) modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the feedforward path and a non-return-to-zero digital-to-analog converter with a finite-impulsive-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65- nm CMOS, can digitise signals with up to 57-dB SNDR within 40-MHz bandwidths, with an adaptive power dissipation of 16.7- to-22.8 mW, and a programmable 1.2/2GHz clock rate.

Image feature extraction acceleration
J. Fernández-Berni, M. Suárez-Cambre, R. Carmona-Galán, V. Brea, R. del Río, D. Cabello and Á. Rodríguez-Vázquez
Book Chapter - Image Feature Detectors and Descriptors, SCI, vol. 630, pp 109-132, 2016
SPRINGER    DOI: 10.1007/978-3-319-28854-3_5    ISBN: 978-3-319-28852-9    » doi
[abstract]
Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of dealing with individual pixels at the earliest processing levels. In this regard, conventional system architectures do not take advantage of potential exploitation of parallelism and distributed memory from the very beginning of the processing chain. Raw pixel values provided by the front-end image sensor are squeezed into a high-speed interface with the rest of system components. Only then, after deserializing this massive dataflow, parallelism, if any, is exploited. This chapter introduces a rather different approach from an architectural point of view. We present two Application-Specific Integrated Circuits (ASICs) where the 2-D array of photo-sensitive devices featured by regular imagers is combined with distributed memory supporting concurrent processing. Custom circuitry is added per pixel in order to accelerate image feature extraction right at the focal plane. Specifically, the proposed sensing-processing chips aim at the acceleration of two flagships algorithms within the computer vision community: the Viola-Jones face detection algorithm and the Scale Invariant Feature Transform (SIFT). Experimental results prove the feasibility and benefits of this architectural solution.

Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs
R. Fiorelli, O. Guerra, R. del Rio and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2015
[abstract]
This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors. To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and effective capacitors' value is obtained with an electrical extraction tool using a flattened view of the MOM. Effects of capacitors layout placement in the SAR and their surroundings in the effective capacitance value are quantified. A quantitative study of a 10-bit un-even split-capacitor SAR is done for different combinations of m and l bits. Finally, a qualitative set of guidelines to choose the distribution of these bits is listed.

Energy Efficient Transconductor for Widely Programmable Analog Circuits and Systems
A. Morgado, R. del Río and J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2015
[abstract]
This paper presents a novel transconductor which is widely tunable and reconfigurable to a number of circuit specifications with an adaptive power consumption. Current- starving techniques are combined with programmable output stages so that the output current range and granularity can be arbitrarily set, while increasing energy efficiency with the number of active stages. These characteristics make the proposed circuit very suited to enlarge the autonomy and battery life in a number of portable multi-mode/multi-standard devices, spanning from biomedical applications and mobile phones to wireless sensor networks.

Real-time single-exposure ROI-driven HDR adaptation based on focal-plane reconfiguration
J. Fernández-Berni, R. Carmona-Galán, R. del Río, R. Kleihorst, W. Philips and Á. Rodríguez-Vázquez
Conference - SPIE Real-Time Image and Video Processing 2015
[abstract]
This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of interest concurrently, automatically and asynchronously with a single exposure period. The operation is supported by two intertwined photo-diodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal-plane into independent regions within which automatic concurrent adjustment of the integration time takes place. At pixel level, one of the photo-diodes senses the pixel value itself whereas the other, in collaboration with its counterparts in a particular ROI, senses the mean illumination of that ROI. Additional circuitry interconnecting both photo-diodes enables the asynchronous adjustment of the integration time for each ROI according to this sensed illumination. The sensor can be reconfigured on-the-fly according to the requirements of a vision algorithm.

Bottom-up performance analysis of focal-plane mixed-signal hardware for Viola-Jones early vision tasks
J. Fernández-Berni, R. Carmona-Galán, R. del Río and A. Rodríguez-Vázquez
Journal Paper - International Journal of Circuit Theory and Applications, vol. 43, no. 8, pp 1063-1079, 2015
JOHN WILEY & SONS    DOI: 10.1002/cta.1996    ISSN: 0098-9886    » doi
[abstract]
Focal-plane mixed-signal arrays have traditionally been designed according to the general claim that moderate accuracy in processing is affordable. The performance of their circuitry has been analyzed in these terms without a comprehensive study of the ultimate consequences of such moderate accuracy. In this paper, for the first time to the best of our knowledge, we do carry out this study. We move expectable performance of mixed-signal image processing hardware directly into the vision algorithm making use of it. This permits to close a wider design loop, enabling a more aggressive design of this kind of hardware provided that the algorithm, at the highest level -semantic interpretation of the scene-, can afford it. Thus, we present a thorough analysis of the non-idealities associated with the implementation of a QVGA array tailored for the distinctive characteristics of the Viola-Jones processing framework. The resulting deviation models are then introduced in the processing flow of this framework provided by the OpenCV library. We have found, contrary to what could be expected, that these deviations do not necessarily degrade the performance of the Viola-Jones algorithm. They could be even beneficial for certain high-level specifications. Additionally, we demonstrate the architectural advantages of our approach: exploitation of focal-plane distributed memory and ultra-low-power operation.

Single Event Transients trigger instability in Sigma-Delta Modulators
D. Malagon, J.M. de la Rosa, R. del Río and G. Leger
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2014
[abstract]
In this paper we emulate the errors caused by SET in a Flexible 4th-Order Sigma-Delta Modulator with DC-to-44MHz Tunable Center Frequency in 1.2-V 90-nm CMOS. We identify the virtual ground of the integrators as a sensitive node and show that a charge injection may drive the modulator into long-term instability.

5x5 SPAD Matrices for the Study of the Trade-offs between Fill Factor, Dark Count Rate and Crosstalk in the Design of CMOS Image Sensors
M. Moreno-García, R. del Río, Ó. Guerra, and Á. Rodríguez-Vázquez
Conference - Conference on Ph.D. Research in Microelectronics and Electronics PRIME 2014
[abstract]
CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. There are tradeoffs that involve these two magnitudes and dark count rate (DCR) which are of great interest for the implementation of image sensors. A set of 5x5 matrices of SPADs with different sizes and shapes is designed to study the relationships between FF, crosstalk and DCR, and conceive an accurate behavioural model of SPAD arrays. The testchip is fully operative and preliminary experimental results are presented.

Live Demo: Real-time Focal-plane Face Obfuscation through Programmable Pixelation
J. Fernández-Berni, R. Carmona-Galán, R. del Río, J.A. Leñero-Bardallo, R. Kleihorsty, W. Philipsy and Á. Rodríguez-Vázquez
Conference - Workshop on the Architecture of Smart Cameras WASC 2014
[abstract]
Privacy concerns are hindering the introduction of smart camera networks in application scenarios like retailing analytics, factories or elderly care. Indeed, there is usually no need of dealing with sensitive data when it comes to carrying out a meaningful visual analysis in these scenarios. Time spent by customers in front of a showcase, trajectories of workers around a manufacturing site or fall detection in a nursing home are three examples where video analytics can be performed without compromising privacy. But still the idea of networked cameras pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. New strategies must be developed in order to ensure privacy from the very point where sensitive data are generated: the sensors. Protection measures embedded on-chip at the front-end sensor of each network node significantly reduce the number of trusted system components as well as the impact of potential software flaws. In this demonstration, we present a full-custom QVGA vision sensor that can be reconfigured to implement programmable pixelation of image regions at the focal plane. According to the literature, pixelation provides the best performance in terms of balance between privacy protection and intelligibility of the surveyed scene.

High dynamic range adaptation for ROI tracking based on reconfigurable concurrent dual-sensing
J. Fernández-Berni, R. Carmona-Galán, R. del Río and A. Rodríguez-Vázquez
Journal Paper - Electronics Letters, vol. 50, no. 24, pp 1832-1834, 2014
IET    DOI: 10.1049/el.2014.3136    ISSN: 0013-5194    » doi
[abstract]
A single-exposure technique to extend the dynamic range of vision sensors is presented. It is particularly suitable for vision algorithms requiring region-of-interest (ROI) tracking under varying illumination conditions. The operation is supported by two intertwined photodiodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal plane into independent regions within which automatic concurrent adjustment of the integration time takes place for each frame. At pixel level, one of the photodiodes senses the pixel value itself, whereas the other, in collaboration with its counterparts in every prescribed ROI, senses the mean illumination of that specific ROI. An additional circuitry interconnecting both photodiodes asynchronously determines the integration period for each ROI according to its mean illumination. The experimental results for a quarter video graphics array prototype CMOS vision sensor are reported.

Demo: A prototype vision sensor for real-time focal-plane obfuscation through tunable pixelation
J. Fernández-Berni, R. Carmona-Galán, R. del Río, R. Kleihorst, W. Philips and A. Rodríguez-Vázquez
Conference - IEEE/ACM Int. Conference on Distributed Smart Cameras ICDSC 2014
[abstract]
Privacy concerns are hindering the introduction of smart camera networks in prospective application scenarios like retail analytics, factory monitoring or elderly care. The idea of networked cameras pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. New strategies must be developed in order to ensure privacy from the very point where sensitive data are generated: the sensors. Protection measures embedded on-chip at the front-end sensor of each network node significantly reduce the number of trusted system components as well as the impact of potential software flaws. In this demonstration, we present a full-custom QVGA vision sensor that can be recongured to implement programmable pixelation of image regions at the focal plane. In particular, we show on-the-fly focal-plane face obfuscation supported by the Viola-Jones frontal face detector provided by OpenCV.

Focal-plane sensing-processing: A power-efficient approach for the implementation of privacy-aware networked visual sensors
J. Fernandez-Berni, R. Carmona-Galan, R. del Rio, R. Kleihorst, W. Philips and A. Rodriguez-Vazquez
Journal Paper - Sensors, vol. 14, no. 8, pp. 15203-15226, 2014
MDPI AG    DOI: 10.3390/s140815203    ISSN: 1424-8220    » doi
[abstract]
The capture, processing and distribution of visual information is one of the major challenges for the paradigm of the Internet of Things. Privacy emerges as a fundamental barrier to overcome. The idea of networked image sensors pervasively collecting data generates social rejection in the face of sensitive information being tampered by hackers or misused by legitimate users. Power consumption also constitutes a crucial aspect. Images contain a massive amount of data to be processed under strict timing requirements, demanding high-performance vision systems. In this paper, we describe a hardware-based strategy to concurrently address these two key issues. By conveying processing capabilities to the focal plane in addition to sensing, we can implement privacy protection measures just at the point where sensitive data are generated. Furthermore, such measures can be tailored for efficiently reducing the computational load of subsequent processing stages. As a proof of concept, a full-custom QVGA vision sensor chip is presented. It incorporates a mixed-signal focal-plane sensing-processing array providing programmable pixelation of multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise dynamic range adaptation, integral image computation and multi-resolution filtering. The proposed circuitry is also suitable to build a granular space, becoming the raw material for subsequent feature extraction and recognition of categorized objects.

A QVGA Vision Sensor with Multi-functional Pixels for Focal-Plane Programmable Obfuscation
J. Fernández-Berni, R. Carmona Galán, R. del Río and Á. Rodríguez-Vázquez
Conference - ACM/IEEE International Conference on Distributed Smart Cameras ICDSC 2014
[abstract]
Privacy awareness constitutes a critical aspect for smart camera networks. An ideal awless protection of sensitive information would boost their application scenarios. However, it is still far from being achieved. Numerous challenges arise at diferent levels, from hardware security to subjective perception. Generally speaking, it can be stated that the closer to the image sensing device the protection measures take place, the higher the privacy and security attainable. Likewise, the integration of heterogeneous camera components becomes simpler since most of them will not require to consider privacy issues. The ultimate objective would be to incorporate complete protection directly into a smart image sensor in such a way that no sensitive data would be delivered off-chip while still permitting the targeted video analytics. This paper presents a 320x240-px prototype vision sensor embedding processing capabilities useful for accomplishing this objective. It is based on recongurable focal-plane sensing-processing that can provide programmable obfuscation. Pixelation of tunable granularity can be applied to multiple image regions in parallel. In addition to this functionality, the sensor exploits reconfigurability to implement other processing primitives, namely block-wise high dynamic range, integral image computation and Gaussian filtering. Its power consumption ranges from 42.6mW for high dynamic range operation to 55.2mW for integral image computation at 30fps. It has been fabricated in a standard 0.18μm CMOS process.

Smart imaging for power-efficient extraction of Viola-Jones local descriptors
J. Fernández-Berni, R. Carmona-Galán, R. del Río, J.A. Leñero-Bardallo, M. Suárez-Cambre and A. Rodríguez-Vázquez
Conference - IS&T International Symposium on Electronic Imaging 2014
[abstract]
In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors constitute inputs for trained classifiers which in turn enable diferent high-level vision tasks. While local descriptors certainly alleviate the computation load of subsequent processing stages by preventing them from handling raw images, they still have to deal with individual pixels. Feature vector extraction can thus become a major limitation for conventional embedded vision hardware. In this paper, we present a power-eficicient sensing-processing array conceived to provide the computation of integral images at diferent scales. These images are intermediate representations that speed up feature extraction. In particular, the mixed-signal array operation is tailored for extraction of Haar-like features. These features feed the cascade of classifiers at the core of the Viola-Jones framework. The processing lattice has been designed for the standard UMC 0.18μm 1P6M CMOS process. In addition to integral image computation, the array can be reprogrammed to deliver other early vision tasks: concurrent rectangular area sum, block-wise HDR imaging, Gaussian pyramids and image pre-warping for subsequent reduced kernel filtering.

Undersampling RF-to-Digital CT ΣΔ Modulator with Tunable Notch Frequency and Simplified Raised-Cosine FIR Feedback DAC
S. Asghar, J.M. de la Rosa and R. del Río
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2013
[abstract]
This paper presents a continuous-time fourth-order band-pass Sigma-Delta (SD) Modulator for digitizing radio-frequency signals in software-defined-radio mobile systems. The modulator architecture is made up of two resonators and a 16-level quantizer in the feedforward path and a raised-cosine finite-impulsive- response feedback DAC. The latter is implemented with a reduced number of filter coefficients as compared to previous approaches, which allows to increase the notch frequency programmability from 0.0375fs to 0.25fs, while keeping stability and robustness to circuit-element tolerances. These features are combined with undersampling techniques to achieve an efficient and robust digitization of 0.455-to-5GHz signals with scalable 8-to-15bit effective resolution within 0.2-to-30MHz signal bandwidth, with a reconfigurable 1-to-4GHz sampling frequency.

CMOS Sigma-Delta Converters: Practical Design Guide
J.M. de la Rosa and R. del Río
Book - 426 p, 2013
WILEY-IEEE PRESS    ISBN: 978-1-119-97925-8    » link
[abstract]
This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations -going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues -from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs.

CMOS SPADs Selection, Modeling and Characterization Towards Image Sensors Implementation
M. Moreno-García, O. Guerra, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Conference on Electronics, Circuits, and Systems ICECS 2012
[abstract]
The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance.

A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW Flexible 4th-Order SD Modulator with DC-to-44MHz Tunable Center Frequency in 1.2-V 90-nm CMOS
S. Asghar, R. del Río and J.M. de la Rosa
Conference - IEEE/IFIP International Conference on VLSI and System-on-Chip VLSI-SoC 2012
[abstract]
This paper describes the design of a switched-capacitor fourth-order single-loop ΣΔ modulator with a 5-level embedded quantizer. The loop filter consists of a cascade of resonators with distributed feedforward coefficients, which can be programmed to make the zeros of the noise transfer function variable. As a result, the modulator can be reconfigured either as a lowpass or as a bandpass analog-to-digital converter with a tunable notch frequency and an optimized loop-filter zero placement. The circuit -designed and implemented in a 1.2-V 90-nm CMOS technology- incorporates diverse architecture- and circuit-level strategies to adapt its performance to different sets of specifications with a variable sampling frequency of 100 and 200MHz and scalable power consumption. Post-layout simulations (for a frequency range of DC to 22MHz) and behavioral simulations (from 22 to 44MHz) show a correct operation of the circuit in steps of 1-to-2MHz, featuring an adaptive SNDR of 74-to-86, 57-to-68 and 50-to-59dB within a signal bandwidth of 200kHz, 1MHz and 2MHz, respectively, while dissipating a scalable power consumption of 16-to-22mW.

A power-scalable concurrent cascade 2-2-2 SC ΣΔ modulator for Software Defined Radio
A. Morgado, J.G. García, S. Asghar, L.I. Guerrero, R. del Río and J.M. de la Rosa
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2012
[abstract]
This paper presents a flexible 1.2-V 90-nm CMOS cascade three-stage SC ΣΔ modulator with local resonation in the last two stages, unity signal transfer function and programmable (either 3 or 5 level) quantization in all stages. The chip reconfigures its loop filter order (2nd, 4th, 6th order), the clock frequency (from 40 to 240MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental results demonstrate the flexibility of the proposed modulator, featuring a programmable noise shaping within a 100kHz-to-10MHz signal band, with adaptive power dissipation.

High-efficiency cascade ΣΔ modulators for the next generation software-defined-radio mobile systems
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper - IEEE Transactions on Instrumentation and Measurement, vol. 61, no. 11, pp 2860-2869, 2012
IEEE    DOI: 10.1109/TIM.2012.2200394    ISSN: 0018-9456    » doi
[abstract]
This paper overviews a number of ΣΔ modulation techniques to implement efficient analog-to-digital converters intended for low-voltage wideband multimode wireless telecom systems. The ΣΔ architectures under study combine different strategiesunity signal transfer function (USTF), resonation, loop-filter order reconfiguration, and concurrencyin order to increase performance while keeping high robustness against circuit errors. Practical considerations involving timing issuesderived from the combined use of different noise-shaping techniquesare analyzed in order to evaluate the feasibility of the proposed ΣΔ topologies. As an application, the design, circuit implementation, and experimental characterization of a flexible 1.2-V 90-nm CMOS sixth-order three-stage cascade SC ΣΔ modulator is presented. The modulator uses local resonation in the last two stages and USTF and programmable (either three or five levels) quantization in all stages. The chip reconfigures its loop-filter order (second, fourth, sixth order) and the clock frequency (from 40 to 240 MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental measurements show the flexibility of the proposed circuit, featuring a programmable noise shaping within a 100-kHz-10-MHz signal band, with adaptive power dissipation, thus demonstrating to be a suitable solution to digitize signals in future software-defined-radio mobile terminals. © 1963-2012 IEEE.

High-Efficiency Cascade ΣΔ ADCs for Software-Defined-Radio Mobile Systems
A. Morgado, R. del Río and J.M. de la Rosa
Conference - International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design IWADC 2011
[abstract]
This paper discusses a number of techniques to implement efficient cascade ΣΔ modulators intended for low-voltage, wideband, multi-mode applications. Several architectural strategies -such as loop-filter order reconfiguration and concurrency- are embedded in SMASH topologies with unity signal transfer function and resonation in order to improve the performance, while keeping high robustness against circuit errors. The proposed ΣΔ architectures -properly combined with circuit-level reconfiguration and biasing adaptation techniques- constitute a suited solution to implement analog-to-digital converters in future software-definedradio mobile terminals.

Nanometer CMOS Sigma-Delta Modulators for Software Defined Radios
A. Morgado, R. del Río and J.M. de la Rosa
Book - 288 p, 2011
SPRINGER    ISBN: 978-1-4614-0036-3    » link
[abstract]
This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes. This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview of the state-of-the-art performance, challenges and practical solutions, providing the necessary insight to implement successful design, through an efficient design and synthesis methodology. Readers will learn a number of practical skills from system-level design to experimental measurements and testing.

Circuital and Architectural Challenges for the Design of PET Medical Imaging Systems using CMOS
A. Rodríguez-Vázquez, R. Carmona-Galán, G. Liñán, R. del Río and B. Pérez-Verdú
Conference - International Workshop on Biomedical Applications of Micro-PET, 2010
[abstract]
Abstract not available

Flexible ΣΔ Modulators for Multi-Standard Wireless Transceivers: Novel Architectures and Circuit Solutions
A. Morgado, R. del Río and J.M. de la Rosa
Conference - Design, Automation and Test in Europe Conf. PhD Forum DATE 2010
[abstract]
Abstract not available

A 100kHz-10MHz BW, 78-to-52dB DR,4.6-to-11mW flexible SC sigma-delta modulator in 1.2-V 90-nm CMOS
A. Morgado, R. del Río, J.M. de la Rosa, L. Bos, J. Ryckaert and Van Der Plas
Conference - European Solid State Circuits Conference ESSCIRC 2010
[abstract]
This paper presents an adaptive 1.2-V 90-nm CMOS cascade two-stage (2-2) SC sigma delta modulator with 3-level quantization and unity signal transfer function in both stages. The chip reconfigures its loop filter order (either 2 nd or 4 th- order), clock frequency (from 40 to 240 MHz) and scales power according to the required specifications for different wireless standards, covering: GSM, Bluetooth, GPS, UMTS, DVB-H and WiMAX. Measurements feature a dynamic range of 78/70/71.5/66/62/52dB and a peak signal-to- (noise+distortion) ratio of 72.3/68.0/65.4/63.3/59.1/48.7dB within 100kHz/500kHz/1MHz/2MHz/4MHz/10MHz, while consuming 4.6/5.35/6.2/8/8/11mW, respectively. These results show a competitive performance with the state-of-the-art multi-standard sigma delta modulators, covering one of the widest regions in the DR-vs.-Bandwidth plane. ©2010 IEEE.

Adaptive SMASH ΣΔ converters for the next generation of mobile phones - Design issues and practical solutions
A. Morgado, R. del Río and J.M. de la Rosa
Conference - IEEE International Conference NEWCAS 2010
[abstract]
This paper discusses practical design issues associated to the implementation of sigma delta analog-to-digital converters intended for mobile telecom applications. After a comprehensive description of the proposed adaptive resonation-based Sturdy MASH sigma delta modulator, architectural and circuit-level timing limitations are analysed in detail, showing different design trade-offs. As a result of this analysis, a novel time-saving implementation of the dynamic element matching required in the multi-bit front-end digital-to-analog converter is presented. The circuit solutions found can be applied to SC reconfigurable implementations operating up to 320-MHz sampling frequencies. In order to demonstrate the capabilities of the considered modulator, a case study covering a number of standards, including GSM, Bluetooth, UMTS, DVB-H, WiMax and WLAN is shown. Time-domain behavioural simulations including main circuit-level errors validate the presented study. © 2010 IEEE.

A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications
A. Morgado, R. del Río, J.M. de la Rosa, R. Castro-López and B. Pérez-Verdú
Journal Paper - Microelectronics Journal, vol. 41, no. 5, pp 277-290, 2010
ELSEVIER    DOI: 10.1016/j.mejo.2010.03.004    ISSN: 0026-2692    » doi
[abstract]
This paper describes the design and experimental characterization of a 0.13 mu m CMOS switched-capacitor reconfigurable cascade Sigma Delta modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode EA prototype shows an overall performance that is competitive with the current state of the art.(1) (C) 2010 Elsevier Ltd. All rights reserved.

A Flexible Resonation-Based Cascade ΣΔ Modulator with Simplified Cancellation Logic
J.M. de la Rosa, A. Morgado, J.G. García and R. del Río
Conference - IEEE International Conference on Electronics, Circuits and Systems ICECS 2009
[abstract]
This paper presents a new two-stage cascade ΣΔ modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity signal transfer function in all stages, make the presented modulator highly tolerant to noise leakages, very robust to non-linearities and mismatches of the loop-filter circuitry, and especially suited for low-voltage implementations at low oversampling ratios. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators, simplifies the switched-capacitor implementation of the resonation and makes the presented architecture very suited for reconfigurable multi-standard applications. As an illustration, a Beyond-3G case study is shown to demonstrate the benefits of the presented approach.

A New Reconfigurable Cascade ΣΔ Modulator Architecture with Inter-Stage Resonation and no Digital Cancellation Logic
A. Morgado, J.G. García, R. del Río and J.M. de la Rosa
Conference - Design of Circuits and Integrated Systems Conference DCIS 2009
[abstract]
This paper presents a new two-stage cascade ΣΔ modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity signal transfer function in all stages, make the presented modulator highly tolerant to noise leakages, very robust to non-linearities and mismatches of the loop-filter circuitry, and especially suited for low-voltage implementations at low oversampling ratios. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators, simplifies the switched-capacitor implementation of the resonation and makes the presented architecture very suited for reconfigurable multi-standard applications. Besides, several practical details about the implementation of the modulator are given throughout the paper. As an illustration, a Beyond-3G case study is shown to demonstrate the benefits of the presented approach.

Resonation-based hybrid continuous-time/discrete-time cascade sigma delta modulators - application to 4G wireless telecom
J.M. de la Rosa, A. Morgado and R. del Río
Conference - VLSI Circuits and Systems Conference at 4th SPIE Microtechnologies for the New Millennium, 2009
[abstract]
This paper presents innovative architectures of hybrid Continuous-Time/ Discrete-Time (CT/DT) cascade sigma delta Modulators sigma delta Ms) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth as compared to conventional sigma delta Ms, the proposed topologies take advantage of the CT nature of the front-end sigma delta M stage, by embedding anti-aliasing filtering as well as their suitability to operate up to the GHz range. Moreover, the presented modulators include multi-bit quantization and Unity Signal Transfer Function (USTF) in both stages to reduce the integrator noutput swings, and programmable resonation to optimally distribute the zeroes of the overall Noise Transfer Function (NTF), such that the in-band quantization noise is minimized for each operation mode. Both local and inter-stage (global) based resonation architectures are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit non-ideal effects. The combination of all mentioned characteristics results in novel hybrid sigma delta Ms, very suited for the implementation of adaptive/reconfigurable Analog-to-Digital Converters (ADCs) intended for the 4th Generation (4G) of wireless telecom systems. © 2009 SPIE.

Hybrid continuous-time/discrete-time cascade sigma delta modulators with programmable resonation
J.M. de la Rosa, A. Morgado and R. del Río
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2009
[abstract]
This paper presents novel architectures of hybrid continuous-time/discrete-time cascade Sigma Delta modulators that combine the benefits of both circuit techniques with programmable noise transfer function resonation and unity signal transfer function in all stages. Both local and inter-stage based resonation topologies are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit implementation. As an application, a multi-standard case study is presented, targeting 5-14 bit programmable effective resolution within a tunable 100kHz-100MHz signal bandwidth.(dagger 1)

Hybrid continuous-time/discrete-time cascade sigma delta modulator with adaptive inter-stage resonation
A. Morgado, J.M. de la Rosa and R. del Río
Journal Paper - Electronics Letters, vol. 45, no. 5, pp 251-252, 2009
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el:20093232    ISSN: 0013-5194    » doi
[abstract]
A novel architecture of a hybrid continuous- time/discrete-time cascade Sigma Delta modulator that takes advantage of both circuit techniques, by including implicit anti-aliasing. filtering and reduced sampling requirements, while presenting high robustness to circuit non-idealities, is presented. These circuital features are combined with programmable resonation to optimally distribute the zeros of the noise transfer function. In addition, the unity signal transfer function is implemented in all the modulator stages in order to reduce the integrator's output swing. All these characteristics make the proposed architecture well suited to the implementation of reconfigurable A/D conversion in future generations of wireless telecom systems.

Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey
J.M. de la Rosa, R. Castro-López, A. Morgado, E.C. Becerra Alvarez, R. del Río, F.V. Fernández and B. Pérez-Verdú
Journal Paper - Microelectronics Journal, vol. 40, no. 1, pp 156-176, 2009
ELSEVIER    DOI: 10.1016/j.mejo.2008.07.001    ISSN: 0026-2692    » doi
[abstract]
The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost. Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical. These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems. (C) 2008 Elsevier Ltd. All rights reserved.

Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers
R. Castro-López, A. Morgado, O. Guerra, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and F. Fernández
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 58, no. 3, pp 227-241, 2009
SPRINGER    DOI: 10.1007/s10470-007-9122-0    ISSN: 0925-1030    » doi
[abstract]
This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.

A Novel Low-Voltage Reconfigurable ΣΔ Modulator for 4G Wireless Receivers
A. Morgado, R. del Río and J.M. de la Rosa
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2008
[abstract]
This paper presents a new adaptable cascade ΣΔ modulator architecture for low-voltage multi-standard applications. It uses two reconfiguration strategies: a programmable global resonation and a variable loop-filter order. These techniques are properly combined in a novel topology that allows to increase the effective resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations including the main circuit-level non-idealities are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSM, UMTS, WLAN and Wi-Max.

La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica
A.J. Acosta, R. del Río and A. Rodríguez-Vázquez
Conference - VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica TAEE 2008
[abstract]
La Electrónica es una disciplina versátil en cuanto a las metodologías y técnicas docentes que pueden emplearse. Frente a las clases magistrales, experiencias de cátedra, tutorías y clases prácticas, el Trabajo Académicamente Dirigido (TAD) se muestra como altamente eficiente a la hora de trasvasar conocimiento al alumno. En esta comunicación se pone de manifiesto la experiencia de innovación docente puesta en funcionamiento en la Licenciatura en Física de la Universidad de Sevilla y que opera satisfactoriamente desde el curso 2002/03.

Two novel cascade ΣΔ modulators for broadband low-voltage A/D conversion
A. Morgado, R. del Río and J.M. de la Rosa
Conference - IEEE International Midwest Symposium on Circuits and Systems MWSCAS 2008
[abstract]
This paper presents two new architectures of cascade Sigma Delta modulators that, based on the use of resonation, increase their effective resolutions compared to previously reported topologies while presenting high robustness to non-linearities of the amplifiers and very relaxed output swing requirements. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architectures very suited for highly-linear broadband A/D conversion(+1).

A low-voltage flexible cascade sigma delta modulator for beyond-3G wireless telecom
A. Morgado, R. del Río and J.M. de la Rosa
Conference - IEEE International Midwest Symposium on Circuits and Systems MWSCAS 2008
[abstract]
This paper presents a new adaptable cascade EA modulator architecture for low-voltage multi-standard applications. It uses two reconfiguration strategies: a programmable global resonation scheme and a variable loop-filter order. These techniques are properly combined in a novel topology that allows to increase the effective resolution in a given bandwidth, whereas keeping relaxed output swing requirements and high robustness to mismatch and to non-linearities of the amplifiers. Time-domain simulations including main circuit-level effects are shown to demonstrate the benefits of the presented modulator when it is configured to cope with the requirements of GSNL UMTS, NVLAN and Wi-Max.(+1)

A triple-mode reconfigurable sigma-delta modulator for multi-standard wireless applications
A. Morgado, R. del Río and J.M. de la Rosa
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 08
[abstract]
This paper presents the implementation and experimental characterization of a reconfigurable Sigma Delta modulator intended for multi-mode wireless receivers that is capable to perform the analog-to-digital conversion for GSM, Bluetooth, and UMTS standards. The Sigma Delta modulator reconfigures its cascade topology and building blocks in order to adapt the performance to the diverse standard specifications with optimized power consumption. The prototype has been implemented in a 130-nm CMOS technology and features dynamic ranges of 86.7/81.0/63.3dB and peak signal-to-(noise+distortion)ratios of 74.0/68.4/52.8dB at 400ksps/2Msps/8Msps, respectively The modulator power consumption is 25.2/25.0/44.5mW of which 11.0/10.5/ 24.8mW are dissipated in the analog circuitry.

Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK
A. Morgado, V.J. Rivas, R. del Río, R. Castro-López, F.V. Fernández and J.M. de la Rosa
Journal Paper - Integration, the VLSI Journal, vol. 41, no. 2, pp 269-280, 2008
ELSEVIER    DOI: 10.1016/j.vlsi.2007.07.001    ISSN: 0167-9260    » doi
[abstract]
This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless receivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise, characterized by the noise figure and the signal-to-noise ratio, and non-linearity, represented by the input-referred second-order and third-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some block-specific errors have also been included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, which makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard direct-conversion receiver intended for 4G telecom systems is modeled and simulated considering the building block requirements for the different standards. (C) 2007 Elsevier B.V. All rights reserved.

Resonation-based cascade ΣΔ modulator for broadband low-voltage A/D conversion
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper - Electronics Letters, vol. 44, no. 2, pp 97-99, 2008
IEEE    DOI: 10.1049/el:20083249    ISSN: 0013-5194    » doi
[abstract]
A novel cascade Sigma Delta modulator architecture is presented that employs inter-stage resonation to increase its effective resolution compared to traditional cascades while presenting very relaxed output swing requirements and, subsequently, high robustness to nonlinearities of the amplifiers. In addition, the use of loop filters based on forward-Euler integrators, instead of backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architecture very suited to wideband A/D conversion.

Cascade ΣΔ modulator for low-voltage wideband applications
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper - Electronics Letters, vol. 43, no. 17, pp 910-911, 2007
IEEE    DOI: 10.1049/el:20071454    ISSN: 0013-5194    » doi
[abstract]
A new cascade SigmaDelta modulator architecture with unity signal transfer function is presented which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.

Resonation-based Cascade ΣΔ Modulators for High-Linearity Broadband A/D Conversion
A. Morgado, R. del Río and J.M. de la Rosa
Conference - XXII Conf. on Design of Circuits and Integrated Systems DCIS 2007
[abstract]
This paper presents two new architectures of cascade ΣΔ modulators that, based on the use of resonation, allow to increase the effective resolution compared to previously reported topologies whereas keeping relaxed output swing and high robustness to non-linearities of the amplifiers. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architectures very suited for the implementation of highly-linear broadband A/D conversion.

CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 2
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course - Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
[abstract]
Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.

CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 1.b
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course - Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
[abstract]
Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.

CMOS Sigma-Delta Converters - From Basics to State-of-the-Art: Session 1.a
R. del Río, B. Pérez-Verdú and J.M. de la Rosa
Course - Master/Doctorate Course at KTH, Stockholm (Sweden), 2007
[abstract]
Based on a comprehensive description of sigma-delta modulation operating principles, this course presents an overview of the advances in architectures, circuits, models, methods and practical considerations for the design of high-performance CMOS sigma-delta A/D interfaces - from system to physical level design - as well as packaging and test. The course is divided into three theoretical lectures and two practical sessions. The first lecture describes the basic concepts, fundamentals and architectures and makes a revision of the state-of-the-art on CMOS sigma-delta ADC integrated circuits. The second lecture moves farther down to the circuit- and physical level to present the building blocks normally used to implement sigma-delta ADCs as well as the impact of their error mechanisms. The analyses and models covered in the first two lectures form the basis of a systematic design methodology described in the third session, where a SIMulink-based SIgma-DElta Simulator (SIMSIDES) is introduced. Finally, as an application, two practical exercises will be carried out by using SIMSIDES in order to put in practice the knowledge learned in the course.

Novel topologies of cascade sigma delta modulators for low-voltage wideband applications
A. Morgado, R. del Río and J.M. de la Rosa
Conference - European Conference on Circuit Theory and Design ECCTD 2007
[abstract]
This work presents two novel topologies of cascade EA modulators with unity signal transfer function that avoid the need of digital filtering in the error cancellation logic. The combination of these two aspects make them highly tolerant to noise leakages, very robust to non-linearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioral simulations are presented that demonstrate the higher efficiency of the proposed topologies compared to existing cascades intended for wideband applications.(dagger 1).

An adaptive sigma delta modulator for multi-standard hand-held wireless devices
A. Morgado, R. del Río and J.M. de la Rosa
Conference - IEEE Asian Solid-State Circuits Conference A-SSCC 2007
[abstract]
This paper describes the design and experimental characterization of a 130-nm CMOS cascade Sigma Delta modulator intended for multi-standard wireless telecom systems. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Bluetooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5mW, of which 11.0/10.5/24.8 are due to the analog part of the circui(dagger 1).

Design of a 130 nm CMOS reconfigurable cascade sigma delta modulator for GSM/UMTS/Bluetooth
A. Morgado, R. del Río and J.M. de la Rosa
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
This paper reports a 130-nm CMOS programmable cascade Sigma Delta modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UNITS. The modulator is reconfigured at both architecture- and circuit-level in order to adapt its performance to the different standard specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

A SIMULINK block set for the high-level simulation of multistandard radio receivers
A. Morgado, R. del Río and J.M. de la Rosa
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
This paper describes a SIMULINK block set for the behavioral simulation of RF receivers. Building blocks are modeled including their main circuit-level non idealities. These models are incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, what makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As a case study, a direct-conversion receiver intended for 4G telecom systems is modeled and simulated using the proposed toolbox.

Towards systematic design of multi-standard converters
V.J. Rivas, R. Castro-López, A. Morgado, O. Guerra, E. Roca, R. del Río, J.M. de la Rosa and F.V. Fernández
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard YEA modulator meeting the specifications of three wireless communication standards.

Design of a 0.13 μm CMOS cascade expandable sigma delta modulator for multi-standard RF telecom systems
A. Morgado, R. del Río and J.M. de la Rosa
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
This paper reports a 130-nm CMOS programmable cascade Sigma Delta modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit-level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

Behavioral modeling and simulation of multi-standard RF receivers using MATLAB/SIMULINK
A. Morgado, R. del Río and J.M. de la Rosa
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
This paper presents a SIMULINK block set for the behavioral modeling and high-level simulation of RF receiver front-ends. The toolbox includes a library with the main RF circuit models that are needed to implement wireless transceivers, namely: low noise amplifiers, mixers, oscillators, filters and programmable gain amplifiers. There is also a library including other blocks like the antenna, duplexer filter and switches, required to implement reconfigurable architectures. Behavioral models of building blocks include the main ideal functionality as well as the following non-idealities: thermal noise characterized by the Noise Figure (NF) and the Signal-to-Noise Ratio (SNR) and nonlinearity expressed by the input-referred 2nd- and 3rd-order intercept points, IIP2 and IIP3, respectively. In addition to these general parameters, some block specific errors have been also included, like oscillator phase noise and mixer offset. These models have been incorporated into the SIMULINK environment making an extensive use of C-coded S-functions and reducing the number of library block elements. This approach reduces the simulation time while keeping high accuracy, what makes the proposed toolbox very appropriate to be combined with an optimizer for the automated high-level synthesis of radio receivers. As an application of the capabilities of the presented toolbox, a multi-standard Direct-Conversion Receiver (DCR) intended for 4G telecom systems is modeled and simulated considering the building-block requirements for the different standards.

A new cascade sigma delta modulator for low-voltage wideband applications
A. Morgado, R. del Río and J.M. de la Rosa
Journal Paper - Electronics Letters, vol. 43, no. 17, pp 910-911, 2007
INSTITUTION OF ENGINEERING AND TECHNOLOGY-IET    DOI: 10.1049/el:20071454    ISSN: 0013-5194    » doi
[abstract]
A new cascade EA modulator architecture with unity signal transfer function is presented, which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.

A SIMULINK-based Approach for the Behavioral Modeling and Simulation of Multistandard RF Receivers
A. Morgado, R. del Río and J.M. de la Rosa
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2006
[abstract]
This paper presents a toolbox for the simulation of multistandard radio receivers using MATLAB/SIMULINK. Behavioral models of building blocks, including their main circuit errors, are described and incorporated into SIMULINK by combining library blocks with C-coded S-functions in order to reduce the simulation time while keeping high accuracy and interoperability of different circuit models. As a case study, the complete model of a direct-conversion receiver intended for GSM/UMTS/Bluetooth/WLAN is presented. Simulation results are shown for the different standards in order to illustrate the capabilities of the proposed tool.

CMOS cascade sigma-delta modulators for sensors and telecom. Error analysis and practical design
R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez
Book - ACSP, 299 p, 2006
SPRINGER    ISBN: 978-1-4020-4775-6    » link
[abstract]
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures. The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks. The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors. CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.

Reconfiguration of cascade sigma delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2006
[abstract]
This paper presents design considerations for cascade Sigma-Delta Modulators (Sigma Delta Ms) included in multistandard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1(L-2) expandible Sigma Delta M is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach.

Design Considerations for Multistandard Cascade ΣΔ Modulators
A. Morgado, R. del Río, J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2005
[abstract]
This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.

A 0.13μm CMOS Current Steering D/A Converter for PLC and VDSL Applications
J. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa, M. Delgado-Restituto and R. del Río
Conference - XX Conference on Design of Circuits and Integrated Systems DCIS 2005
[abstract]
This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Transistor-level simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 active area.

An approach to the design of the design of multistandard ΣΔ modulators
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Conference - WSEAS Int. Conf. on Electronics, Control and Signal Processing ICECS 2005
[abstract]
This paper discusses issues concerning the design of cascade sigma-delta modulators intended for multistandard wireless receivers. Four standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator topology in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture-and circuit-level in order to adapt the modulator performance to the standards requirements with adaptive power consumption. Time-domain behavioural simulations are shown to validate the presented approach.

A CMOS High-Resolution Automotive Sensor A/D Interface Based on a 110-dB @ 40kS/s Programmable-Gain Cascade 2-1 Sigma-Delta Modulator with Embedded Design-for-Testability Strategies
J.M. de la Rosa, S. Escalera, O. Guerra, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference - Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
[abstract]
Abstract not available

A 12-bit 80 MS/s A/D/A Interface for Power-Line Applications in 0.13μm Digital CMOS Technology
J. Ruiz-Amaya, J.F. Fernández-Bootello, J.M. de la Rosa, R. del Río and M. Delgado-Restituto
Conference - 5th Int. Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications ADDA 2005
[abstract]
Abstract not available

An approach to the design of cascade sigma delta modulators for multistandard wireless transceivers
A. Morgado, J.M. de la Rosa, R. del Río, F. Medeiro, B. Pérez-Verdú, F.V. Fernández and A. Rodríguez-Vázquez
Journal Paper - WSEAS Transactions on Circuits and Systems, vol. 4, no. 12, pp 1811-1818, 2005
WSEAS    ISSN: 1109-2734    
[abstract]
This paper discusses issues concerning the design of reconfigurable cascade sigma-delta modulators for multistandard wireless transceivers. The use of an expandible cascade modulator is considered as the starting point to boost reconfigurability at the architectural level. Then, a top-down methodology is proposed to obtain the cascade candidates that better fulfil the requirements of each standard with adaptive power consumption, taking into account the complexity of the reconfiguration at both architecture- and circuit-level. Several reconfiguration strategies are presented and validated by time-domain behavioural simulations.

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 sigma delta modulator with programmable gain and programmable chopper stabilization
O. Guerra, S. Escalera, J.M. de la Rosa, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
This paper describes a 0.35 μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/ 2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40 degrees C, 175 degrees C). The modulator architecture has been selected after an exhaustive comparison among multiple Sigma Delta M topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.

An embedded 12-bit 80 MS/s A/D/A interface for power-line communications in 0.13 um pure digital CMOS technology
M. Delgado-Restituto, J. Ruiz-Amaya, J.M. de la Rosa, J.F. Fernández-Bootello, L. Díez, R. del Río and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2005
[abstract]
This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13 mu m pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band powerline communications. The A/D converter uses a pipelined structure, whereas the D/A stage is based on segmented current steering techniques. In both cases, specifications are 12-b resolution at 80MS/s and MTPR above 56dB.

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs
J.M. de la Rosa, S. Escalera, B. Pérez-Verdú, F. Medeiro, O. Guerra, R. del Río and A. Rodríguez-Vázquez
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp 2246-2264, 2005
IEEE    DOI: 10.1109/JSSC.2005.857356    ISSN: 0018-9200    » doi
[abstract]
This paper describes a 0.35-mu m CMOS chopper-stabilized switched-capacitor 2-1 cascade Sigma Delta modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0.5, x 1, x 2, and x 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40 degrees C to 175 degrees C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm(2) silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution Sigma Delta modulators.

High-level synthesis of switched-capacitor, switched-current and continuous-time sigma delta modulators using SIMULINK-based time-domain behavioral models
J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernández, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 9, pp 1795-1810, 2005
IEEE    DOI: 10.1109/TCSI.2005.852479    ISSN: 1057-7122    » doi
[abstract]
This paper presents a high-level synthesis tool for Sigma Delta modulators (Sigma Delta Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for Sigma Delta M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Sigma Delta Ms using both discrete-time and continuous-time circuit techniques.

Architectures and design considerations for wireline sigma delta modulators beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Workshop on ADC Modelling and Testing IWADC 2005
[abstract]
In this paper we discuss design considerations for sigma-delta modulators (&USigma;&UDelta; Ms) aimed at high-linearity highspeed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12-15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenaRío. We show that, after proper architecture selection, guided by a simple power estimation method, these &USigma;&UDelta; Ms are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μ m CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade &USigma;&UDelta; Ms to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results. © 2005 Elsevier Ltd. All rights reserved.

Convertidores A/D ΣΔ de altas prestaciones en tecnologías CMOS submicrométricas
R. del Río-Fernández
Thesis - Date of defense: 15/04/2004
UNIVERSIDAD DE SEVILLA, IMSE-CNM    » link
[abstract]
El trabajo desarrollado en esta Tesis pretende demostrar la viabilidad de implementar de forma robusta convertidores sigma-delta de alta velocidad y alta resolución utilizando tecnologías CMOS profundamente submicrométricas orientadas al desarrollo de sistemas-on-chip. Ello conlleva una adecuada selección de arquitecturas, técnicas y bloques de circuito que permitan, no sólo la obtención de moduladores sigma-delta de altas prestaciones, sino también solventar los problemas asociados con la implementación práctica en tecnologías VLSI orientadas al diseño digital (baja tensión de alimentación, mala linealidad y apareamiento de dispositivos, etc.). Los resultados de esta Tesis se demuestran mediante dos prototipos para aplicaciones de banda ancha por cable (ADSL y ADSL+) integrados en tecnologías CMOS de 0.35um (3.3V) y de 0.25um (2.5V). Ambos moduladores utilizan topologías en cascada con cuantización multi-bit y bajo sobremuestreo. Ninguno de los dos prototipos emplea técnicas de calibración, transistores no estándar o tensiones on-chip mayores que la alimentación nominal y sus prestaciones resultan competitivas respecto al actual estado del arte.

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time sigma delta modulators
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, E. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2004
[abstract]
This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of SigmaDelta Modulators (SigmaDeltaMs). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for SigmaDeltaM synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.

A 0.35 μm CMOS 17-bit@40 kS/s sensor A/D interface based on a programmable-gain cascade 2-1 sigma delta modulator
J.M. García-González, S. Escalera, J.M. de la Rosa, O. Guerra, F. Medeiro, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35mum standard CMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) SigmaDelta modulator. The preamplifier, based on hybrid Nested-Miller compensated four-stage opamps, has a fixed gain of 10 and it is capable of handling signals with 20kHz-bandwidth and amplitudes ranging from muVs to hundreds of mVs with a signal-to-(noise+distortion) ratio over 100dB. The modulator architecture has a programmable gain for a better fitting to the characteristics of different sensor outputs. The design of both circuits is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the interface hierarchy. Simulation results show 17-bit@40kS/s for all cases of the modulator gain.

An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma delta modulators in the MATLAB/SIMULINK environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
This paper presents a MATLAB toolbox for the automated high-level sizing of SigmaDelta Modulators (SigmaDeltaMs) based on the combination of an accurate time-domain behavioural simulator and a statistical optimizer. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of SigmaDeltaMs using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques.)

Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+
R. del Río, J.M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro and A. Rodríguez-Vázquez
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 1, pp 47-62, 2004
IEEE    DOI: 10.1109/TCSI.2003.821308    ISSN: 1057-7122    » doi
[abstract]
We present a 90-dB spurious-free dynamic range sigma-delta modulator (E AM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-mum CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB14 b respectively. The SigmaDelta modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the SigmaDelta modulator.

Analysis of error mechanisms in switched-current sigma-delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 175-201, 2004
KLUWER ACADEMIC    DOI: 10.1023/B:ALOG.0000011167.24521.82    ISSN: 0925-1030    » doi
[abstract]
This paper presents a systematic analysis of the major switched-current ( SI) errors and their influence on the performance degradation of SigmaDelta Modulators (SigmaDeltaMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass SigmaDeltaM (2nd-LPSigmaDeltaM) and a 4th-order BandPass SigmaDeltaM (4th-BPSigmaDeltaM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notch frequency position in the case of 4th-BPSigmaDeltaMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI SigmaDeltaMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 mum CMOS SI 4th-BPSigmaDeltaM silicon prototype validate our approach.

SIMSIDES Toolbox: An Interactive Tool for the Behavioural Simulation of Discrete- and Continuous-time ΣΔ Modulators in the MATLAB/SIMULINK Environment
J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, R. del Río, B. Moreno-Reina, B. Pérez-Verdú, R. Tortosa, R. Romay and A. Rodríguez-Vázquez
Conference - Design of Circuits and Integrated Systems Conf. DCIS 2003
[abstract]
This paper presents an user-friendly tool, named SIMSIDES, for the time-domain simulation of ΣΔ modulators in the MATLAB/SIMULINK environment. The tool is able to simulate an arbitrary ΣΔ topology implemented by using discrete-time - switched-capacitor and switched-current - and continuous-time circuit techniques, considering the most important circuit parasitics. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions. The combination of high accuracy, short CPU-time and interoperability of different circuit models, make the tool into a valuable instrument to optimize the design of ΣΔ analog-to-digital converters.

Design and Implementation of a 0.35μm CMOS Programmable-Gain 2-1 Cascade ΣΔ Modulator for Automotive Sensors
J.M. García-González, S. Escalera, J.M. de la Rosa, F. Medeiro, R. del Río, O. Guerra, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2003
[abstract]
Abstract not available

Description Languages and Tools for Behavioural Simulation of ΣΔ Modulators: a Comparative Survey
R. Castro-López, J. Ruiz-Amaya, J.M. de la Rosa, R. Romay, R. del Río, F. Medeiro, F.V. Fernández, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Forum on Specification & Design Languages FDL 2003
[abstract]
Abstract not available

Design Considerations for ΣΔ Modulators Beyond ADSL
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Workshop IBERCHIP 2003
[abstract]
In this paper we discuss design considerations for Sigma-Delta modulators (ΣΔM) aimed at high-linearity, high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range 12-15bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade multi-bit architec-tures in a low-voltage, deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are still promising candidates to achieve post-ADSL performances in coming CMOS processes.

High-order cascade multi-bit ΣΔ modulators
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter - CMOS Telecom Data Converters, pp 307-343, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_9    ISBN: 978-1-4419-5382-7    » doi
[abstract]
Motivated by the commercial success of the wireline communication products, mixed-signal designers are being pushed to integrate A/D and D/A interfaces featuring 12- to 16-bit effective resolution for signal bandwidths well in excess of 1MHz. These specifications must be achieved in a low-voltage scenario, making use of poor performance (and often badly characterized) devices, which decreases the 'analog speed' of deep-submicron CMOS processes.

Sigma-delta CMOS ADCs: An overview of the state-of-the-art
A. Rodríguez-Vázquez, F. Medeiro, J.M. de la Rosa, R. del Río, R. Tortosa and B. Pérez-Verdú
Book Chapter - CMOS Telecom Data Converters, pp 37-91, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_2    ISBN: 978-1-4419-5382-7    » doi
[abstract]
As stated in Chapter 1, analog-to-digital conversion involves a number of tasks, namely:
- Sampling the input signal at frequency f s, with prior anti-aliasing filtering and, in some cases, holding the sampled values.
- Quantizing the input sample values with N bits; i.e., mapping each continuous-valued input sample onto the closest discrete-valued level out of the (2ˆN - 1) discrete levels covering the input signal variation interval.
- Encoding the result in a digital representation.

Bandpass sigma-delta A/D converters: Fundamentals, architectures and circuits
J.M. de la Rosa, B. Pérez-Verdú, R. del Río, F. Medeiro and A. Rodríguez-Vázquez
Book Chapter - CMOS Telecom Data Converters, pp 523-559, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_11    ISBN: 1-4020-7546-4    » doi
[abstract]
The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs

Design methodologies for sigma-delta converters
F.V. Fernández, R. del Río, R. Castro-López, F. Medeiro and B. Pérez-Verdú
Book Chapter - CMOS Telecom Data Converters, pp 523-559, 2003
SPRINGER    DOI: 10.1007/978-1-4757-3724-0_15    ISBN: 978-1-4419-5382-7    » doi
[abstract]
Oversampling converters have become very popular due to their ability to solve problems found in other architectures, like the need for high-accuracy analog antialiasing filtering and the large sensitivity to circuit imperfections and noisy environments.

A modem in CMOS technology for data communication on the low-voltage power line
O. Guerra, C.M. Domínguez-Matas, S. Escalera, J.M. García-González, G. Liñán, R. del Río, M. Delgado-Restituto and A. Rodríguez-Vázquez
Journal Paper - Integration, the VLSI Journal, vol. 36, no. 4, pp 229-236, 2003
ELSEVIER    DOI: 10.1016/j.vlsi.2003.09.007    ISSN: 0167-9260    » doi
[abstract]
This paper presents a CMOS 0.8 mum mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line. It includes all the analog circuitry needed for input interfacing and modulation/ demodulation (low-noise amplifier, PLL-based frequency synthesis, tunable filter banks, and decision circuitry), logic circuitry for control purposes, and an output amplifier used as front-end for an off-chip line driver. The chip demodulates signals down to 283muV(rms) (these are worst case values among 30 randomly-selected samples used as vehicles for detailed electrical characterization; most of the samples featured 200 muV(rms), sensitivity; bit error rate (BER) is below 0.5 x 10(-5)) at 10 kbps, and operates correctly in the whole industrial temperature range, from -45degreesC to 80degreesC, under 5% variations of the 5V supply voltage. This ASIC is now in commercial production. (C)2003 Published by Elsevier B.V.

A 2.5-V CMOS wideband sigma-delta modulator
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - IEEE Instrumentation and Measurement Technology Conference I2MTC 2003
[abstract]
A high-performance SigmaDelta modulator for wireline communication applications is presented It employs a 4th-order cascade multi-bit architecture that requires only 16 oversampling ratio, and has been implemented using fully-differential SC circuits in a 0.25-mum CMOS technology. Measurements show a dynamic range of 84dB operating at Z2MS/s output rate, and 79dB at 4.4MS/s. The whole prototype dissipates 65.8mW from a 2.5-V supply.

Expandible high-order cascade Sigma Delta modulator with constant, reduced systematic loss of resolution
F. Medeiro, R. del Río, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference - IEEE International Instrumentation and Measurement Technology Conference I2MTC 2003
[abstract]
An arbitrary order sigma-delta modulator cascade architecture is presented with only 1-bit loss of resolution due to scaling issues, even with single-bit quantization. This loss is kept with a high overloading point, regardless of the order. Simulations reveal that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization.

Design considerations for an automotive sensor interface sigma delta modulator
F. Medeiro, J.M. de la Rosa, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
In this paper we discuss design considerations for a Sigma-Delta modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. This SigmaDeltaM contains a programmable-gain input interface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently implemented by proper architecture selection and ad hoc sampling and integration capacitor structures. Behavioral simulations of a 17bit 40kS/s modulators are included to illustrate the design considerations.

A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time sigma delta modulators
J. Moreno-Reina, J.M. de la Rosa, F. Medeiro, R. Romay, R. del Río, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2003
[abstract]
This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of SigmaDelta modulators implemented by using switched-capacitor, switched-current and continuous-time Circuits, considering the most important error mechanisms. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions-The outcome is a complete SIMULINK block library that allows interactive, fast and accurate simulation of an arbitrary SigmaDelta topology.

A sigma delta modulator for a programmable-gain, low-power, high-linearity automotive sensor interface
J.M. de la Rosa, F. Medeiro, B. Pérez-Verdú, R. del Río and A. Rodríguez-Vázquez
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
This paper describes the design and electrical implementation of a 0.351mum CMOS 17-bit@40kS/s Sigma-Delta Modulator (SigmaDeltaM) forming part of a sensor interface for automotive applications. First of all, the paper discusses the most important limiting factors and design considerations applicable to a high-resolution SigmaDeltaM for sensor interfaces. After an exhaustive comparison among multiple SigmaDeltaM architectures in terms of resolution, speed and power dissipation, a third-order (2-1) cascade SigmaDeltaM is chosen. For a better fitting to the characteristics of different sensor outputs, the SigmaDeltaM here includes a programmable set of gains (0.5, 1, 2, and 4). The gain programmability is implemented by a reconfigurable capacitor array of unitary capacitors. In order to relax the amplifier dynamics requirements for the different modulator gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. Behavioural simulations considering transistor-level circuit parasitics shows a Dynamic Range (DR.) over 105dB for all cases of the modulator gain.

A 79-dB 4.4MS/s ΣΔ Modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2002
[abstract]
Abstract not available

Design of a broadband ΣΔ modulator in 2.5-V CMOS
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez Verdú and A. Rodríguez-Vázquez
Conference - Design, Automation and Test in Europe Conference and Exhibition DATE 2002
[abstract]
Abstract not available

Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Book Chapter - Analog Circuit Design: Structured Mixed-Mode Design, Multi-Bit Sigma-Delta Converters, Short Range RF Circuits, pp 235-260, 2002
SPRINGER    DOI: 10.1007/0-306-47951-6_11    ISBN: 978-1-4020-7216-1    » doi
[abstract]
This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-um CMOS technology are given and illustrated through experimental results.

A 2.5-V sigma delta modulator in 0.25μm CMOS for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
This paper presents a dual-quantization cascade SC SigmaDelta modulator intended for A/D conversion in ADSL applications. The modulator combines a low oversampling ratio with 3-bit resolution in the last stage, to achieve 14bit@4.4MS/s (16x) and 15bit@2.2MS/s (32x) with no need of correction/calibration mechanisms. It consumes 66mW from a single 2.5-V supply and has been implemented in 0.25-mum CMOS technology.

Correction-free multi-bit sigma-delta modulators for ADSL
R. del Río, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez
Conference - Workshop on Advances in Analog Circuit Design AACD 2002
[abstract]
This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-mum CMOS technology are given and illustrated through experimental results.

Practical study of idle tones in 2nd-order bandpass Sigma Delta modulators
J.M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río and A. Rodríguez-Vázquez
Journal Paper - Microelectronics Journal, vol. 33, no. 11, pp 1005-1009, 2002
ELSEVIER    DOI: 10.1016/S0026-2692(02)00049-6    ISSN: 0026-2692    » doi
[abstract]
This paper studies the tonal behaviour of the quantization noise in 2nd-order bandpass SigmaDelta modulators. Closed-form expressions for the frequency of the idle tones are derived for different locations of the signal centre frequency. The analytical results are validated through experimental measurements taken from a 0.8 mum CMOS prototype realized using fully differential switched-current circuits. (C) 2002 Elsevier Science Ltd. All rights reserved.

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