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Author: Serrano Gotarredona, Teresa
Year: Since 2002
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Neuromorphic spiking neural networks and their memristor-CMOS hardware implementations
L.A. Camuñas-Mesa, B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper - Materials, vol. 12, no. 7, article number 2745, 2019
MDPI AG    DOI: 10.3390/ma12172745    ISSN: 1996-1944    » doi
[abstract]
Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal-Oxide-Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

Learning weights with STDP to build prototype images for classification
A. Vasudevan, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Design and Technology of Integrated Systems in Nanoscale Era DTIS 2019
[abstract]
The combination of Spike Timing Dependent Plasticity (STDP) and latency coding used in a spiking neural network has been shown to learn hierarchical features. In this paper we propose a new way to classify images using an SVM. Prototype images are built from the weights learned in an unsupervised manner using STDP. The prototype images are cross correlated with the input image and the peak of the cross correlation with each prototype image is used as additional features for an SVM. The network, demonstrated on the MNIST data set, achieves 99.15% testing accuracy which is the best reported accuracy for a SNN with unsupervised training.

A current attenuator for efficient memristive crossbars read-out
C. Mohan, J.M. de la Rosa, E. Vianello, L. Perniola, C. Reita, B. Linares-Barranco and T. Serrano-Gotarredona
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2019
[abstract]
This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.

Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization
A. Yousefzadeh, S. Hosseini, P. Holanda, S. Leroux, T. Werner, T. Serrano-Gotarredona and B. Linares-Barranco, B. Dhoedt and P. Simoens
Conference - IEEE International Conference on Artificial Intelligence Circuits and Systems AICAS 2019
[abstract]
Artificial Neural Networks (ANNs) show great performance in several data analysis tasks including visual and auditory applications. However, direct implementation of these algorithms without considering the sparsity of data requires high processing power, consume vast amounts of energy and suffer from scalability issues. Inspired by biology, one of the methods which can reduce power consumption and allow scalability in the implementation of neural networks is asynchronous processing and communication by means of action potentials, so-called spikes. In this work, we use the wellknown sigma-delta quantization method and introduce an easy and straightforward solution to convert an Artificial Neural Network to a Spiking Neural Network which can be implemented asynchronously in a neuromorphic platform. Briefly, we used asynchronous spikes to communicate the quantized output activations of the neurons. Despite the fact that our proposed mechanism is simple and applicable to a wide range of different ANNs, it outperforms the state-of-the-art implementations from the accuracy and energy consumption point of view. All source code for this project is available upon request for the academic purpose.

A Digital Neuromorphic Realization of the 2-D Wilson Neuron Model
M. Nouri, M. Hayati, T. Serrano-Gotarredona and D. Abbot
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 1, 2019
IEEE    DOI: 10.1109/TCSII.2018.2852598    ISSN: 1549-7747    » doi
[abstract]
This brief presents a piecewise linear approximation of the nonlinear Wilson (NW) neuron model for the realization of an efficient digital circuit implementation. The accuracy of the proposed piecewise Wilson (PW) model is examined by calculating time domain signal shaping errors. Furthermore, bifurcation analyses demonstrate that the approximation follows the same bifurcation pattern as the NW model. As a proof of concept, both models are hardware synthesized and implemented on field programmable gate arrays, demonstrating that the PW model has a range of neuronal behaviors similar to the NW model with considerably higher computational performance and a lower hardware overhead. This approach can be used in hardware-based large scale biological neural network simulations and behavioral studies. The mean normalized root mean square error and maximum absolute error of the PW model are 6.32% and 0.31%, respectively, as compared to the NW model.

On the Hardware Efficiency of 1-bit Homeostatic Stochastic STDP
A. Yousefzadeh, E. Stromatias, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Cognitive Computing Conference 2018
[abstract]
Here we propose and demonstrate on FPGA hardware a homeostatic stochastic 1-bit weight STDP rule (whose 19 neurons have separate thresholds for integrating spikes and for triggering STDP update) used in a self-learning 20 feature extraction layer, which when combined with a rudimentary hebbian spiking classifier is capable of classifying with up to 100% accuracy a DVS recorded poker card symbol benchmark.

Scene Context Classification with Event-Driven Spiking Deep Neural Networks
P. Negri, M. Soto, B. Linares-Barranco and T. Serrano-Gotarredona
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2018
[abstract]
Event-Driven computation is attracting growing attention among researchers for several reasons. On one hand, the availability of new bio-inspired retina-like vision sensors that provide spiking outputs, like the Dynamic Vision Sensor (DVS) makes it possible to demonstrate energy efficient and high-speed complex vision tasks. On the other hand, the emergence of abundant new nanoscale devices that operate as tunable two-terminal resistive elements, which when operated through dynamic pulsing techniques emulate learning and processing in the brain, promise an explosion of highly compact energy efficient neuromorphic event-driven applications. In this paper, we focus for the first time on a high-level cognitive task, namely scene context classification, performed by event-driven computations and using real sensory data from a DVS camera.

On practical issues for stochastic STDP hardware with 1-bit synaptic weights
A. Yousefzadeh, E. Stromatias, M. Soto, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 12, article 665, 2018
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2018.00665    ISSN: 1662-4548    » doi
[abstract]
In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it comes to hardware engineering, a key question is always to find the minimum number of necessary bits to keep the neurocomputational system working satisfactorily. Here we present some techniques and results obtained when limiting synaptic weights to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation by replicating a classical biological experiment on visual orientation tuning, using a simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden feature extraction layer of a 2-layer system, where for the second (and output) layer we use already reported SNN classifiers. The systems are tested on two spiking datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and a Poisson-distributed spike representation MNIST dataset version. Tests are performed using the in-house MegaSim event-driven behavioral simulator and by implementing the systems on FPGA (Field Programmable Gate Array) hardware.

Calibration of offset via bulk for low-power HfO2 based 1T1R memristive crossbar read-out system
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Periniolla, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Microelectronic Engineering, vol. 198, pp 35-47, 2018
ELSEVIER    DOI: 10.1016/j.mee.2018.06.011    ISSN: 0167-9317    » doi
[abstract]
Neuromorphic RRAM circuits typically need currents of several mA when many binary memristive devices are activated at the same time. This is due to the low resistance state of these devices, which increases the power consumption and limits the scalability. To overcome this limitation, it is vital to investigate how to minimize the amplitude of the read-out inference pulses sent through the crossbar lines. However, the amplitude of such inference voltage pulses will become limited by the offset voltage of read-out circuits. This paper presents a three-stage calibration circuit to compensate for offset voltage in the wordlines of a memristor-array read-out system. The proposed calibration scheme is based on adjusting the bulk voltage of one of the input differential pair MOSFETs by means of a switchable cascade of resistor ladders. This renders the possibility to obtain calibration voltage steps less than 0.1mV by cascading a few number of stages, whose results are only limited by mismatch, temperature, electrical noise and other fabrication defects. The system is built using HfO2-based binary memristive synaptic devices on top of a 130-nm CMOS technology. Layout-extracted simulations considering technology corners, PVT variations and electrical noise are shown to validate the presented calibration scheme.

Active Perception with Dynamic Vision Sensors. Minimum Saccades with Optimum Recognition
A. Yousefzadeh, G. Orchard, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 4, pp 927-939, 2018
IEEE    DOI: 10.1109/TBCAS.2018.2834428    ISSN: 1932-4545    » doi
[abstract]
Vision processing with dynamic vision sensors (DVSs) is becoming increasingly popular. This type of a bio-inspired vision sensor does not record static images. The DVS pixel activity relies on the changes in light intensity. In this paper, we introduce a platform for the object recognition with a DVS in which the sensor is installed on a moving pan-tilt unit in a closed loop with a recognition neural network. This neural network is trained to recognize objects observed by a DVS, while the pan-tilt unit is moved to emulate micro-saccades. We show that performing more saccades in different directions can result in having more information about the object, and therefore, more accurate object recognition is possible. However, in high-performance and low-latency platforms, performing additional saccades adds latency and power consumption. Here, we show that the number of saccades can be reduced while keeping the same recognition accuracy by performing intelligent saccadic movements, in a closed action-perception smart loop. We propose an algorithm for smart saccadic movement decisions that can reduce the number of necessary saccades to half, on average, for a predefined accuracy on the N-MNIST dataset. Additionally, we show that by replacing this control algorithm with an artificial neural network that learns to control the saccades, we can also reduce to half the average number of saccades needed for the N-MNIST recognition.

Hybrid Neural Network, an Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network
A. Yousefzadeh, G. Orchard, E. Stromatias, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
Interest in event-based vision sensors has proliferated in recent years, with innovative technology becoming more accessible to new researchers and highlighting such sensors' potential to enable low-latency sensing at low computational cost. These sensors can outperform frame-based vision sensors regarding data compression, dynamic range, temporal resolution and power efficiency. However, available mature frame-based processing methods by using Artificial Neural Networks (ANNs) surpass Spiking Neural Networks (SNNs) in terms of accuracy of recognition. In this paper, we introduce a Hybrid Neural Network which is an intermediate solution to exploit advantages of both event-based and frame-based processing. We have implemented this network in FPGA and benchmarked its performance by using different event-based versions of MNIST dataset. HDL codes for this project are available for academic purpose upon request.

Performance Comparison of Time-Step-Driven Versus Event-Driven Neural State Update Approaches in Spinnaker
M. Soto, A. Yousefzadeh, T. Serrano-Gotarredona, F. Galluppi, L. Plana, S. Furber and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
The SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. Many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large number of neurons in real-time. SpiNNaker is using a general purpose ARM processor that gives a high amount of flexibility to implement different methods for processing spikes. Various libraries and packages are provided to translate a high-level description of Spiking Neural Networks (SNN) to low-level machine language that can be used in the ARM processors. In this paper, we introduce and compare three different methods to implement this intermediate layer of abstraction. We have examined the advantages of each method by various criteria, which can be useful for professional users to choose between them. All the codes that are used in this paper are available for academic propose.

An Intrinsic Method for Fast Parameter Update on the Spinnaker Platform
M. Soto, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
Neuromorphic Computing or Spiking (also called Event-Driven) Neural Systems are becoming of high interest as they potentially allow for lower power hardware computing platforms, where power consumption is data driven. Traditional approaches (both in software and in hardware), which are not data driven, rely on generic system state updates, consuming a fixed amount of computing resources at each step, independent on the data itself. In neuromorphic spiking or (event-driven) computing systems power is consumed (in principle) if new data is transferred, either at the system input, system output, or internally between computing nodes. One such neuromorphic event-driven computing platform is the scalable SpiNNaker system, which is aimed for a million ARM core platform, capable of emulating in the order of a billion neurons in real time. An important practical drawback of the platform is the long time it takes to download to the hardware a given computational architecture. This step has to be repeated even if one wants to update a set of parameters. Here we present a method for updating internal parameters without downloading again the full architecture, by adding special neurons into the computing architecture which when they spike change given parameters. This allows to download the computing architecture only once to the SpiNNaker platform, and then take advantage of its highly efficient communication network to command specific parameter changes. This allows for intensive parameter searches in a more efficient manner.

Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA
L.A. Camuñas-Mesa, Y. Domínguez-Cordero, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2018
[abstract]
The development of bio-inspired event-driven neuromorphic Dynamic Vision Sensors (DVS) provides a revolutionary way of capturing visual scenes by generating flows of events representing real-time visual information. Each pixel in a DVS operates autonomously and sends out an event (spike) whenever it senses a change of light greater than a preset threshold. Therefore, the DVS generates a continuous flow of events with a high temporal resolution (sub-microsecond) representing reality dynamically, without frames. Spiking Neural Networks (SNNs) process flows of events using different neuronal and synaptic models, performing tasks like object tracking or shape recognition.

Spiking Hough for Shape Recognition
P. Negri, T. Serrano-Gotarredona and B. Linares-Barranco
Book Chapter - Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, pp 425-432, 2018
SPRINGER    DOI: 10.1007/978-3-319-75193-1_51    ISBN: 978-3-319-75192-4    » doi
[abstract]
The paper implements a spiking neural model methodology inspired on the Hough Transform. On-line event-driven spikes from Dynamic Vision Sensors are evaluated to characterize and recognize the shape of Poker signs. The multi-class system, referred as Spiking Hough, shows the good performance on the public POKER-DVS dataset.

A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation
L.A. Camuñas-Mesa, Y.L. Domínguez-Cordero, A. Linares-Barranco, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 12, Article 63, 2018
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2018.00063    ISSN: 1662-4548    » doi
[abstract]
Convolutional Neural Networks (ConvNets) are a particular type of neural network often used for many applications like image recognition, video analysis or natural language processing. They are inspired by the human brain, following a specific organization of the connectivity pattern between layers of neurons known as receptive field. These networks have been traditionally implemented in software, but they are becoming more computationally expensive as they scale up, having limitations for real-time processing of high-speed stimuli. On the other hand, hardware implementations show difficulties to be used for different applications, due to their reduced flexibility. In this paper, we propose a fully configurable event-driven convolutional node with rate saturation mechanism that can be used to implement arbitrary ConvNets on FPGAs. This node includes a convolutional processing unit and a routing element which allows to build large 2D arrays where any multilayer structure can be implemented. The rate saturation mechanism emulates the refractory behavior in biological neurons, guaranteeing a minimum separation in time between consecutive events. A 4-layer ConvNet with 22 convolutional nodes trained for poker card symbol recognition has been implemented in a Spartan6 FPGA. This network has been tested with a stimulus where 40 poker cards were observed by a Dynamic Vision Sensor (DVS) in 1 s time. Different slow-down factors were applied to characterize the behavior of the system for high speed processing. For slow stimulus play-back, a 96% recognition rate is obtained with a power consumption of 0.85 mW. At maximum play-back speed, a traffic control mechanism downsamples the input stimulus, obtaining a recognition rate above 63% when less than 20% of the input events are processed, demonstrating the robustness of the network.

Bulk-based DC offset calibration for Low-power Memristor Array Read-Out System
C. Mohan, L.A. Camuñas-Mesa, E. Vianello, L. Perniola, C. Reita, J.M. de la Rosa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2017
[abstract]
Memristors in neuromorphic circuits typically need to drive currents of many mA because their Low Resistance State (LRS) is in the order of a few kΩ and many devices need to be activated simultaneously which results in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a three-stage cascaded calibration to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array read-out systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV -only limited in practice by mismatch and electrical noise. The circuit has been designed in 130nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are considered to validate the presented calibration technique.

Passive localization and detection of quadcopter UAVs by using dynamic vision sensor
S. Hoseini, G. Orchard, A. Yousefzadeh, B. Deverakonda, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Iranian Joint Congress on Fuzzy and Intelligent Systems, Conference on Fuzzy Systems and Conference on Intelligent Systems CFIS 2017
[abstract]
We present a new passive and low power localization method for quadcopter UAVs (Unmanned aerial vehicles) by using dynamic vision sensors. This method works by detecting the speed of rotation of propellers that is normally higher than the speed of movement of other objects in the background. Dynamic vision sensors are fast and power efficient. We have presented the algorithm along with the results of implementation.

Event-Driven Stereo Visual Tracking Algorithm to Solve Object Occlusion
L.A. Camunas-Mesa, T. Serrano-Gotarredona, S. Ieng, R. Benosman and B. Linares-Barranco
Journal Paper - IEEE Transactions on Neural Networks and Learning Systems, vol. 29, no. 9, pp 4223-4237, 2017
IEEE    DOI: 10.1109/TNNLS.2017.2759326    ISSN: 2162-237X    » doi
[abstract]
Object tracking is a major problem for many computer vision applications, but it continues to be computationally expensive. The use of bio-inspired neuromorphic event-driven dynamic vision sensors (DVSs) has heralded new methods for vision processing, exploiting reduced amount of data and very precise timing resolutions. Previous studies have shown these neural spiking sensors to be well suited to implementing single-sensor object tracking systems, although they experience difficulties when solving ambiguities caused by object occlusion. DVSs have also performed well in 3-D reconstruction in which event matching techniques are applied in stereo setups. In this paper, we propose a new event-driven stereo object tracking algorithm that simultaneously integrates 3-D reconstruction and cluster tracking, introducing feedback information in both tasks to improve their respective performances. This algorithm, inspired by human vision, identifies objects and learns their position and size in order to solve ambiguities. This strategy has been validated in four different experiments where the 3-D positions of two objects were tracked in a stereo setup even when occlusion occurred. The objects studied in the experiments were: 1) two swinging pens, the distance between which during movement was measured with an error of less than 0.5%; 2) a pen and a box, to confirm the correctness of the results obtained with a more complex object; 3) two straws attached to a fan and rotating at 6 revolutions per second, to demonstrate the high-speed capabilities of this approach; and 4) two people walking in a real-world environment.

On Multiple AER Handshaking Channels over High-Speed Bit-Serial Bidirectional LVDS Links with Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems
A. Yousefzadeh, M. Jablonski, T. Iakymchuk, A. Linares-Barranco, A. Rosado, L.A. Plana, S. Temple, T. Serrano-Gotarredona, S.B. Furber and B. Linares-Barranco
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol 11, no. 5, pp 1133-1147, 2017
IEEE    DOI: 10.1109/TBCAS.2017.2717341    ISSN: 1932-4545    » doi
[abstract]
Address event representation (AER) is a widely employed asynchronous technique for interchanging "neural spikes" between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.

A spiking neural network model of the Lateral Geniculate Nucleus on the SpiNNaker Machine
B. Sen-Bhattacharya, T. Serrano-Gotarredona, L. Balassa, A. Bhattacharya, A.B. Stokes, A. Rowley, I. Sugiarto and S. Furber
Journal Paper - Frontiers in Neuroscience, vol. 11, article 454, 2017
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2017.00454    ISSN: 1662-4548    » doi
[abstract]
We present a spiking neural network model of the thalamic Lateral Geniculate Nucleus (LGN) developed on SpiNNaker, which is a state-of-the-art digital neuromorphic hardware built with very-low-power ARM processors. The parallel, event-based data processing in SpiNNaker makes it viable for building massively parallel neuro-computational frameworks. The LGN model has 140 neurons representing a "basic building block" for larger modular architectures. The motivation of this work is to simulate biologically plausible LGN dynamics on SpiNNaker. Synaptic layout of the model is consistent with biology. The model response is validated with existing literature reporting entrainment in steady state visually evoked potentials (SSVEP)-brain oscillations corresponding to periodic visual stimuli recorded via electroencephalography (EEG). Periodic stimulus to the model is provided by: a synthetic spike-train with inter-spike-intervals in the range 10-50 Hz at a resolution of 1 Hz; and spike-train output from a state-of-the-art electronic retina subjected to a light emitting diode flashing at 10, 20, and 40 Hz, simulating real-world visual stimulus to the model. The resolution of simulation is 0.1 ms to ensure solution accuracy for the underlying differential equations defining Izhikevichs neuron model. Under this constraint, 1 s of model simulation time is executed in 10 s real time on SpiNNaker; this is because simulations on SpiNNaker work in real time for time-steps dt ≥ 1 ms. The model output shows entrainment with both sets of input and contains harmonic components of the fundamental frequency. However, suppressing the feed-forward inhibition in the circuit produces subharmonics within the gamma band ( > 30 Hz) implying a reduced information transmission fidelity. These model predictions agree with recent lumped-parameter computational model-based predictions, using conventional computers. Scalability of the framework is demonstrated by a multi-node architecture consisting of three "nodes," where each node is the "basic building block" LGN model. This 420 neuron model is tested with synthetic periodic stimulus at 10 Hz to all the nodes. The model output is the average of the outputs from all nodes, and conforms to the above-mentioned predictions of each node. Power consumption for model simulation on SpiNNaker is «1 W.

Live Demonstration: Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
A. Yousefzadeh, M. Jabłoński, T. Iakymchuk, A. Linares-Barranco, A. Rosado, A. Plana, T. Serrano-Gotarredona, S. Furber and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
We propose demonstration of a serial link for fast asynchronous communication in massively parallel platforms connected to DVS for real-time implementation of bio-inspired vision processing and spiking neural networks.

Live Demonstration: Hardware Implementation of Convolutional STDP for On-line Visual Feature Learning
A. Yousefzadeh, T Masquelier, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
This is a proposal for live demonstration of a hardware that can learn visual feature online and in real-time during presentation of an object. Input Spikes are coming from a bio-inspired silicon retina or Dynamic Vision Sensor (DVS) and will be processed in a Spiking Convolutional Neural Network (SCNN) that is equipped with Synaptic Time Dependent Plasticity (STDP) learning rule and has been implemented in FPGA.

Hardware Implementation of Convolutional STDP for On-line Visual Feature Learning
A. Yousefzadeh, T Masquelier, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
We present a highly hardware friendly STDP (Spike Timing Dependent Plasticity) learning rule for training Spiking Convolutional Cores in Unsupervised mode and training Fully Connected Classifiers in Supervised Mode. Examples are given for a 2-layer Spiking Neural System which learns in real time features from visual scenes obtained with spiking DVS (Dynamic Vision Sensor) Cameras.

Multiplexing AER Asynchronous Channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
A. Yousefzadeh, M. Jabłoński, T. Iakymchuk, A. Linares-Barranco, A. Rosado, A. Plana, T. Serrano-Gotarredona, S. Furber and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2017
[abstract]
Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging "neural spikes" among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.

An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data
E. Stromatias, M. Soto, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 11, article 350, 2017
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2017.00350    ISSN: 1662-4548    » doi
[abstract]
This paper introduces a novel methodology for training an event-driven classifier within a Spiking Neural Network (SNN) System capable of yielding good classification results when using both synthetic input data and real data captured from Dynamic Vision Sensor (DVS) chips. The proposed supervised method uses the spiking activity provided by an arbitrary topology of prior SNN layers to build histograms and train the classifier in the frame domain using the stochastic gradient descent algorithm. In addition, this approach can cope with leaky integrate-and-fire neuron models within the SNN, a desirable feature for real-world SNN applications, where neural activation must fade away after some time in the absence of inputs. Consequently, this way of building histograms captures the dynamics of spikes immediately before the classifier. We tested our method on the MNIST data set using different synthetic encodings and real DVS sensory data sets such as N-MNIST, MNIST-DVS, and Poker-DVS using the same network topology and feature maps. We demonstrate the effectiveness of our approach by achieving the highest classification accuracy reported on the N-MNIST (97.77%) and Poker-DVS (100%) real DVS data sets to date with a spiking convolutional network. Moreover, by using the proposed method we were able to retrain the output layer of a previously reported spiking neural network and increase its performance by 2%, suggesting that the proposed classifier can be used as the output layer in works where features are extracted using unsupervised spike-based learning methods. In addition, we also analyze SNN performance figures such as total event activity and network latencies, which are relevant for eventual hardware implementations. In summary, the paper aggregates unsupervised-trained SNNs with a supervised-trained SNN classifier, combining and applying them to heterogeneous sets of benchmarks, both synthetic and from real DVS chips.

On the Use of Offset Calibration Techniques for Low-Power Memristor Arrays Read-Out
C. Mohan, T. Serrano-Gotarredona, J.M. de la Rosa and B. Linares-Barranco
Conference - International Conference on Memristive Materials, Devices & Systems MEMRISYS 2017
[abstract]
Neuromorphic RRAM circuits need typically to drive currents of many mA because the low resistance state is in the order of a few kΩ and many devices need to be activated simultaneously, thereby resulting in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a calibration circuit to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array readout systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV -only limited in practice by mismatch and electrical noise. The circuit has been designed in a 130-nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuromorphic circuits. Layout-extracted simulations considering PVT variations are shown to validate the presented calibration technique.

Neuromorphic Systems
C. Bartolozzi, R. Benosman, K. Boahen, G. Cauwenberghs, T. Delbrück, G. Indiveri, S.-C. Liu, S. Furber, N. Imam, B. Linares-Barranco, T. Serrano-Gotarredona, K. Meier, C. Posch and M. Valle
Book Chapter - Wiley Encyclopedia of Electrical and Electronics Engineering, pp 1-22, 2016
JOHN WILEY & SONS    DOI: 10.1002/047134608X.W8328    ISBN: 978-0-471-34608-1    » doi
[abstract]
This article reviews a wide spectrum of state-of-the-art neuromorphic systems, ranging from its principles, sensory elements, and processing aspects to large-scale example systems and commercial outlook. It does not aim to provide a full coverage of present knowledge, but simply provide a comprehensive summary with many pointers to further readings.

Benchmarking Spike-Based Visual Recognition: A Dataset and Evaluation
Q. Liu, G. Pineda-Garcia, E. Stromatias, T. Serrano-Gotarredona and S.B. Furber
Journal Paper - Frontiers in Neuroscience, vol. 10, article 496, 2016
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2016.00496    ISSN: 1662-4548    » doi
[abstract]
Today, increasing attention is being paid to research into spike-based neural computation both to gain a better understanding of the brain and to explore biologically-inspired computation. Within this field, the primate visual pathway and its hierarchical organization have been extensively studied. Spiking Neural Networks (SNNs), inspired by the understanding of observed biological structure and function, have been successfully applied to visual recognition and classification tasks. In addition, implementations on neuromorphic hardware have enabled large-scale networks to run in (or even faster than) real time, making spike-based neural vision processing accessible on mobile robots. Neuromorphic sensors such as silicon retinas are able to feed such mobile systems with real-time visual stimuli. A new set of vision benchmarks for spike-based neural processing are now needed to measure progress quantitatively within this rapidly advancing field. We propose that a large dataset of spike-based visual stimuli is needed to provide meaningful comparisons between different systems, and a corresponding evaluation methodology is also required to measure the performance of SNN models and their hardware implementations. In this paper we first propose an initial NE (Neuromorphic Engineering) dataset based on standard computer vision benchmarksand that uses digits from the MNIST database. This dataset is compatible with the state of current research on spike-based image recognition. The corresponding spike trains are produced using a range of techniques: rate-based Poisson spike generation, rank order encoding, and recorded output from a silicon retina with both flashing and oscillating input stimuli. In addition, a complementary evaluation methodology is presented to assess both model-level and hardware-level performance. Finally, we demonstrate the use of the dataset and the evaluation methodology using two SNN models to validate the performance of the models and their hardware implementations. With this dataset we hope to (1) promote meaningful comparison between algorithms in the field of neural computation, (2) allow comparison with conventional image recognition methods, (3) provide an assessment of the state of the art in spike-based visual recognition, and (4) help researchers identify future directions and advance the field.

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links
A. Yousefzadeh, L.A. Plana, S. Temple, T. Serrano-Gotarredona, S.B. Furber and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 8, pp 763-767, 2016
IEEE    DOI: 10.1109/TCSII.2016.2531092    ISSN: 1549-7747    » doi
[abstract]
Asynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, such as the two-phase handshaken non-return-to-zero (NRZ) 2-of-7 protocol used in the SpiNNaker chips. Interfacing such custom chip links to field-programmable gate arrays (FPGAs) is always of great interest, so that additional functionalities can be experimented and exploited for producing more versatile systems. Present-day commercial FPGAs operate typically in synchronous mode, thus making it necessary to incorporate synchronizers when interfacing with asynchronous chips. This introduces extra latencies and precludes pipelining, deteriorating transmission speed, particularly when sending multisymbols per unit communication packet. In this brief, we present a technique that learns to estimate the delay of a symbol transaction, thus allowing a fast pipelining from symbol to symbol. The technique has been tested on links between FPGAs and SpiNNaker chips, achieving the same throughput as fully asynchronous synchronizerless links between SpiNNaker chips. The links have been tested for periods of over one week without any transaction failure. Verilog codes of FPGA circuits are available as additional material for download.

Introduction to the IEEE-CASS Workshop on Micro/Nanoelectronic Circuits and Systems
T. Serrano-Gotarredona and J.M. de la Rosa
Conference - International Conference on Computer as a Tool EUROCON 2015
[abstract]
Very few social and technological revolutions in the history of humankind have become as vertiginous as the one experienced in the first decade of the 21st century. In fact, it would be very difficult to explain our present society without resorting to the so-called Information Technologies, and particularly to some technological achievements such as the Internet, mobile phones and social networks. Technology downscaling toward deep nanoscale level has allowed to put billions of transistors together in a single chip, thus making it possible to integrate entire systems with increasingly number of applications, which span from consumer electronics and computing to telecom and biomedical devices.

Introduction to the IEEE-CASS workshop on micro/nanoelectronic circuits and systems
T. Serrano-Gotarredona and J.M. de la Rosa
Conference - International Conference on Computer as a Tool EUROCON 2015
[abstract]
Very few social and technological revolutions in the history of humankind have become as vertiginous as the one experienced in the first decade of the 21st century. In fact, it would be very difficult to explain our present society without resorting to the so-called Information Technologies, and particularly to some technological achievements such as the Internet, mobile phones and social networks. Technology downscaling toward deep nanoscale level has allowed to put billions of transistors together in a single chip, thus making it possible to integrate entire systems with increasingly number of applications, which span from consumer electronics and computing to telecom and biomedical devices.

Poker-DVS and MNIST-DVS. Their history, how they were made, and other details
T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 9, article 481, 2015
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2015.00481    ISSN: 1662-4548    » doi
[abstract]
This article reports on two databases for event-driven object recognition using a Dynamic Vision Sensor (DVS). The first, which we call Poker-DVS and is being released together with this article, was obtained by browsing specially made poker card decks in front of a DVS camera for 2-4 s. Each card appeared on the screen for about 20-30 ms. The poker pips were tracked and isolated off-line to constitute the 131-recording Poker-DVS database. The second database, which we call MNIST-DVS and which was released in December 2013, consists of a set of 30,000 DVS camera recordings obtained by displaying 10,000 moving symbols from the standard MNIST 70,000-picture database on an LCD monitor for about 2-3 s each. Each of the 10,000 symbols was displayed at three different scales, so that event-driven object recognition algorithms could easily be tested for different object sizes. This article tells the story behind both databases, covering, among other aspects, details of how they work and the reasons for their creation. We provide not only the databases with corresponding scripts, but also the scripts and data used to generate the figures shown in this article (as Supplementary Material).

High-speed serial interfaces for event-driven neuromorphic systems
M. Jablonski, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Conference on Event-Based Control, Communication and Signal Processing EBCCSP 2015
[abstract]
Neuromorphic Engineering is the discipline of building sensory processing artificial systems inspired in the neural processing found in living beings. Biological neural brains show massive connectivity among neurons, which is not realistic to mimic using wires within silicon chips or between chips. Address-Event-Representation is a technology widely used among neuromorphic engineers to emulate such massive interconnectivity by time-multiplexing fast digital channels by transmitting 'Address Events' between neurons that mimic the neural spikes transmitted in biology. Here we show on-going progress on bitserial SATA AER inter-FPGA communications for multi-Tile scalable neuromorphic systems.

Fast Pipeline 128×128 pixel spiking convolution core for event-driven vision processing in FPGAs
A. Yousefzadeh, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Conference on Event-Based Control, Communication and Signal Processing EBCCSP 2015
[abstract]
This paper describes a digital implementation of a parallel and pipelined spiking convolutional neural network (S-ConvNet) core for processing spikes in an event-driven system. Event-driven vision systems use typically as sensor some bio-inspired spiking device, such as the popular Dynamic Vision Sensor (DVS). DVS cameras generate spikes related to changes in light intensity. In this paper we present a 2D convolution event-driven processing core with 128×128 pixels. S-ConvNet is an Event-Driven processing method to extract event features from an input event flow. The nature of spiking systems is highly parallel, in general. Therefore, S-ConvNet processors can benefit from the parallelism offered by Field Programmable Gate Arrays (FPGAs) to accelerate the operation. Using 3 stages of pipeline and a parallel structure, results in updating the state of a 128 neuron row in just 12ns. This improves with respect to previously reported approaches.

ConvNets Experiments on SpiNNaker
T. Serrano-Gotarredona, B. Linares-Barranco, F. Galluppi, L. Plana and S. Furber
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2015
[abstract]
The SpiNNaker Hardware platform allows emulating generic neural network topologies, where each neuron-to-neuron connection is defined by an independent synaptic weight. Consequently, weight storage requires an important amount of memory in the case of generic neural network topologies. This is solved in SpiNNaker by encapsulating with each SpiNNaker chip (which includes 18 ARM cores) a 128MB DRAM chip within the same package. However, ConvNets (Convolutional Neural Network) posses "weight sharing" property, so that many neuron-to-neuron connections share the same weight value. Therefore, a very reduced amount of memory is required to define all synaptic weights, which can be stored on local SRAM DTCM (data-tightly-coupled-memory) at each ARM core. This way, DRAM can be used extensively to store traffic data for off-line analyses. We show an implementation of a 5-layer ConvNet for symbol recognition. Symbols are obtained with a DVS camera. Neurons in the ConvNet operate in an event-driven fashion, and synapses operate instantly. With this approach it was possible to allocate up to 2048 neurons per ARM core, or equivalently 32k neurons per SpiNNaker chip.

Plasticity in memristive devices for spiking neural networks
S. Saïghi, C.G. Mayr, T. Serrano-Gotarredona, H. Schmidt, G. Lecerf, J. Tomas, J. Grollier, S. Boyn, A.F. Vincent, D. Querlioz, S. La Barbera, F. Alibart, D. Vuillaume, O. Bichler, C. Gamrat and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 9, article 51, 2015
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2015.00051    ISSN: 1662-4548    » doi
[abstract]
Memristive devices present a new device technology allowing for the realization of compact non-volatile memories. Some of them are already in the process of industrialization. Additionally, they exhibit complex multilevel and plastic behaviors, which make them good candidates for the implementation of artificial synapses in neuromorphic engineering. However, memristive effects rely on diverse physical mechanisms, and their plastic behaviors differ strongly from one technology to another. Here, we present measurements performed on different memristive devices and the opportunities that they provide. We show that they can be used to implement different learning rules whose properties emerge directly from device physics: real time or accelerated operation, deterministic or stochastic behavior, long term or short term plasticity. We then discuss how such devices might be integrated into a complete architecture. These results highlight that there is no unique way to exploit memristive devices in neuromorphic systems. Understanding and embracing device physics is the key for their optimal use.

Neuromorphic Sensors, Vision
B. Linares-Barranco and T. Serrano-Gotarredona
Book Chapter - Encyclopedia of Computational Neuroscience, pp 1-5, 2014
SPRINGER    DOI: 10.1007/978-1-4614-7320-6_120-1    ISBN: 978-1-4614-7320-6    » doi
[abstract]
Conventional video cameras are based capturing a sequence of still frames. Improving a camera means normally to increase the total number of pixels (resolution) and/or to increase the number of frames per second that can be captured, while reducing sensor area, power consumption, and possibly fabrication cost. These cameras just capture the light intensities of visual reality. If they are to be used in an artificial vision system (e.g., for robotics), then subsequent computing resources need to be allocated to analyze the sequence of captured frames and extract relevant information for decision making.

Spike-Timing-Dependent-Plasticity in Hybrid Memristive-CMOS Spiking Neuromorphic Systems
T. Serrano-Gotarredona and B. Linares-Barranco
Book Chapter - Memristors and Memristive Systems, pp 353-377, 2014
SPRINGER    DOI: 10.1007/978-1-4614-9068-5_12    ISBN: 978-1-4614-9067-8    » doi
[abstract]
In this chapter we present a very exciting overlap between emergent nanotechnology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nano technology devices to the biological synaptic update rule known as Spike-Time-Dependent-Plasticity found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forwards but also backwards. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large-scale spiking learning systems that follow an STDP learning rule, and how hibrid memristor-CMOS chips can be assembled onto scalable architectures exploiting AER (Address-Event-Representation) technology. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. Our aim here is to simply present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two-terminal memristive type devices.

Spike-Timing-Dependent-Plasticity with Memristors
T. Serrano-Gotarredona, T. Masquelier and B. Linares-Barranco
Book Chapter - Memristor Networks, pp 211-247, 2014
SPRINGER    DOI: 10.1007/978-3-319-02630-5_11    ISBN: 978-3-319-02629-9    » doi
[abstract]
Here we present a very exciting overlap between emergent nano technology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nano technology devices to the biological synaptic update rule known as Spike-Time-Dependent-Plasticity found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage or flux driven memristors and focus our discussions on behavioral macro models for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forwards but also backwards. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We will briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We will illustrate how a V1 visual cortex layer can be assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim here is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three terminal memristive type devices. (A Supplemental Material compressed zip file containing all files used for the simulations can be downloaded from http://www.frontiersin.org/neuromorphic_engineering/10.3389/fnins.2011.00026/abstract.)

Spike-based VITE control with dynamic vision sensor applied to an arm robot
F. Perez-Pena, A. Morgado-Estevez, T. Serrano-Gotarredona, F. Gomez-Rodriguez, V. Ferrer-Garcia, A. Jimenez-Fernandez and A. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2014
[abstract]
Spike-based motor control is very important in the field of robotics and also for the neuromorphic engineering community to bridge the gap between sensing / processing devices and motor control without losing the spike philosophy that enhances speed response and reduces power consumption. This paper shows an accurate neuro-inspired spike-based system composed of a DVS retina, a visual processing system that detects and tracks objects, and a SVITE motor control, where everything follows the spike-based philosophy. The control system is a spike version of the neuroinspired open loop VITE control algorithm implemented in a couple of FPGA boards: the first one runs the algorithm and the second one drives the motors with spikes. The robotic platform is a low cost arm with four degrees of freedom.

Event-driven sensing and processing for high-speed robotic vision
L.A. Camunas-Mesa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE Biomedical Circuits and Systems Conference BioCAS 2014
[abstract]
We present here an overview of a new vision paradigm where sensors and processors use visual information not represented by sequences of frames. Event-driven vision is inherently frame-free, as happens in biological systems. We use an event-driven sensor chip (called Dynamic Vision Sensor or DVS) together with event-driven convolution module arrays implemented on high-end FPGAs. Experimental results demonstrate the application of this paradigm to implement Gabor filters and 3D stereo reconstruction systems. This architecture can be applied to real systems which need efficient and high-speed visual perception, like vehicle automatic driving, robotic applications in non-structured environments, or intelligent surveillance in security systems.

Live demonstration: Event-driven sensing and processing for high-speed robotic vision
L.A. Camunas-Mesa, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE Biomedical Circuits and Systems Conference BioCAS 2014
[abstract]
Fig. 1(a) shows the demo setup. Two DVS boards send events out through parallel buses to a merger board. This board merges all the event flow in one single AER bus, and sends it to a custom-made convolutional board, where a 2D grid array of convolution modules is implemented within a Spartan6 FPGA, as represented in Fig. 1(b) and (c). A USBAERmini2 board is used to timestamp the events coming out of the convolutional board and send them to a computer through a high-speed USB2.0 port. Finally, the output events are represented in the computer in real time using jAER software.

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
T. Iakymchuk, A. Rosado, T. Serrano-Gotarredona, B. Linares-Barranco, A. Jimenez-Fernandez, A. Linares-Barranco and G. Jimenez-Moreno
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2014
[abstract]
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.

Retinomorphic event-based vision sensors: Bioinspired cameras with spiking output
C. Posch, T. Serrano-Gotarredona, B. Linares-Barranco and T. Delbruck
Journal Paper - Proceedings of the IEEE, vol. 102, no. 10, pp 1470-1484, 2014
IEEE    DOI: 10.1109/JPROC.2014.2346153    ISSN: 0018-9219    » doi
[abstract]
State-of-the-art image sensors suffer from significant limitations imposed by their very principle of operation. These sensors acquire the visual information as a series of 'snapshot' images, recorded at discrete points in time. Visual information gets time quantized at a predetermined frame rate which has no relation to the dynamics present in the scene. Furthermore, each recorded frame conveys the information from all pixels, regardless of whether this information, or a part of it, has changed since the last frame had been acquired. This acquisition method limits the temporal resolution, potentially missing important information, and leads to redundancy in the recorded image data, unnecessarily inflating data rate and volume. Biology is leading the way to a more efficient style of image acquisition. Biological vision systems are driven by events happening within the scene in view, and not, like image sensors, by artificially created timing and control signals. Translating the frameless paradigm of biological vision to artificial imaging systems implies that control over the acquisition of visual information is no longer being imposed externally to an array of pixels but the decision making is transferred to the single pixel that handles its own information individually. In this paper, recent developments in bioinspired, neuromorphic optical sensing and artificial vision are presented and discussed. It is suggested that bioinspired vision systems have the potential to outperform conventional, frame-based vision systems in many application fields and to establish new benchmarks in terms of redundancy suppression and data compression, dynamic range, temporal resolution, and power efficiency. Demanding vision tasks such as real-time 3-D mapping, complex multiobject tracking, or fast visual feedback loops for sensory-motor action, tasks that often pose severe, sometimes insurmountable, challenges to conventional artificial vision systems, are in reach using bioinspired vision sensing and processing techniques.

Enhanced event-based stereo vision with Gabor filters
L.A. Camuñas-Mesa, T. Serrano-Gotarredona, S.H. Ieng, R. Benosman and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2014
[abstract]
The recently developed Dynamic Vision Sensors (DVS) sense dynamic visual information asynchronously and code it into trains of events with sub-micro second temporal resolution. This high temporal precision makes the output of these sensors especially suited for dynamic 3D visual reconstruction, by matching corresponding events generated by two different sensors in a stereo setup. This paper explores the use of Gabor filters to extract information about the orientation of the object edges that produce the events, applying the matching algorithm to the events generated by the Gabor filters and not to those produced by the DVS. This strategy provides more reliably matched pairs of events, improving the final 3D reconstruction.

On the use of orientation filters for 3D reconstruction in event-driven stereo vision
L.A. Camuñas-Mesa, T. Serrano-Gotarredona, S.H. Ieng, R.B. Benosman and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 8, article 48, 2014
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2014.00048    ISSN: 1662-4548    » doi
[abstract]
The recently developed Dynamic Vision Sensors (DVS) sense visual information asynchronously and code it into trains of events with sub-micro second temporal resolution. This high temporal precision makes the output of these sensors especially suited for dynamic 3D visual reconstruction, by matching corresponding events generated by two different sensors in a stereo setup. This paper explores the use of Gabor filters to extract information about the orientation of the object edges that produce the events, therefore increasing the number of constraints applied to the matching algorithm. This strategy provides more reliably matched pairs of events, improving the final 3D reconstruction.

Event-driven stereo vision with orientation filters
L.A. Camuñas-Mesa, T. Serrano-Gotarredona, B. Linares-Barranco, S. Ieng and R. Benosman
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2014
[abstract]
The recently developed Dynamic Vision Sensors (DVS) sense dynamic visual information asynchronously and code it into trains of events with sub-micro second temporal resolution. This high temporal precision makes the output of these sensors especially suited for dynamic 3D visual reconstruction, by matching corresponding events generated by two different sensors in a stereo setup. This paper explores the use of Gabor filters to extract information about the orientation of the object edges that produce the events, applying the matching algorithm to the events generated by the Gabor filters and not to those produced by the DVS. This strategy provides more reliably matched pairs of events, improving the final 3D reconstruction.

A 1.5 ns off/on switching-time voltage-mode lvds driver/receiver pair for asynchronous aer bit-serial chip grid links with up to 40 times event-rate dependent power savings
C. Zamarreno-Ramos, R. Kulkarni, J. Silva-Martinez, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 7, no. 5, pp 722-731, 2013
IEEE    DOI: 10.1109/TBCAS.2012.2232925    ISSN: 1932-4545    » doi
[abstract]
This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 μ m CMOS. At 500 mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 μ A ( 343 μ A for the driver and 62.5 μA for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions.

Improved Contrast Sensitivity DVS and its Application to Event-Driven Stereo Vision
T. Serrano-Gotarredona, J. Park, A. Linares-Barranco, A. Jiménez, R. Benosman and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2013
[abstract]
This paper presents a new DVS sensor with one order of magnitude improved contrast sensitivity over previous reported DVSs. This sensor has been applied to a bio-inspired event-based binocular system that performs 3D event-driven reconstruction of a scene. Events from two DVS sensors are matched by using precise timing information of their ocurrence. To improve matching reliability, satisfaction of epipolar geometry constraint is required, and simultaneously available information on the orientation is used as an additional matching constraint.

Mapping from Frame-Driven to Frame-Free Event-Driven Vision Systems by Low-Rate Rate Coding and Coincidence Processing--Application to Feedforward ConvNets
J.A. Pérez-Carrasco, B. Zhao, C. Serrano, B. Acha, T. Serrano-Gotarredona, S. Chen and B. Linares-Barranco
Journal Paper - IEEE Transactions on Pattern Analysis and Machine Intelligence , vol. 35, no. 11, pp 2706-2719, 2013
IEEE    DOI: 10.1109/TPAMI.2013.71    ISSN: 0162-8828    » doi
[abstract]
Event-driven visual sensors have attracted interest from a number of different research communities. They provide visual information in quite a different way from conventional video systems consisting of sequences of still images rendered at a given 'frame rate'. Event-driven vision sensors take inspiration from biology. Each pixel sends out an event (spike) when it senses something meaningful is happening, without any notion of a frame. A special type of event-driven sensor is the so-called dynamic vision sensor (DVS) where each pixel computes relative changes of light or 'temporal contrast.' The sensor output consists of a continuous flow of pixel events that represent the moving objects in the scene. Pixel events become available with microsecond delays with respect to 'reality.' These events can be processed 'as they flow' by a cascade of event (convolution) processors. As a result, input and output event flows are practically coincident in time, and objects can be recognized as soon as the sensor provides enough meaningful events. In this paper, we present a methodology for mapping from a properly trained neural network in a conventional frame-driven representation to an event-driven representation. The method is illustrated by studying event-driven convolutional neural networks (ConvNet) trained to recognize rotating human silhouettes or high speed poker card symbols. The event-driven ConvNet is fed with recordings obtained from a real DVS camera. The event-driven ConvNet is simulated with a dedicated event-driven simulator and consists of a number of event-driven processing modules, the characteristics of which are obtained from individually manufactured hardware modules.

STDP and sTDP variations with memristors for spiking neuromorphic learning systems
T. Serrano-Gotarredona, T. Masquelier, T. Prodromakis, G. Indiveri and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 7, article 2, 2013
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2013.00002    ISSN: 1662-4548    » doi
[abstract]
In this paper we review several ways of realizing asynchronous Spike-Timing-Dependent-Plasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight multiplications, in a way such that it is not necessary to (a) introduce global synchronization and (b) to separate memristor learning phases from memristor performing phases. In the approaches described, neurons fire spikes asynchronously when they wish and memristive synapses perform computation and learn at their own pace, as it happens in biological neural systems. We distinguish between two different memristor physics, depending on whether they respond to the original 'moving wall' or to the 'filament creation and annihilation' models. Independent of the memristor physics, we discuss two different types of STDP rules that can be implemented with memristors: either the pure timing-based rule that takes into account the arrival time of the spikes from the pre- and the post-synaptic neurons, or a hybrid rule that takes into account only the timing of pre-synaptic spikes and the membrane potential and other state variables of the post-synaptic neuron. We show how to implement these rules in cross-bar architectures that comprise massive arrays of memristors, and we discuss applications for artificial vision.

A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems
T. Serrano-Gotarredona, T. Prodromakis and B. Linares Barranco
Journal Paper - IEEE Circuits and Systems Magazine, vol. 13, no. 2, pp 74-88, 2013
IEEE    DOI: 10.1109/MCAS.2013.2256271    ISSN: 1531-636X    » doi
[abstract]
Recent research in nanotechnology has led to the practical realization of nanoscale devices that behave as memristors, a device that was postulated in the seventies by Chua based on circuit theoretical reasonings. On the other hand, neuromorphic engineering, a discipline that implements physical artifacts based on neuroscience knowledge, has related neural learning mechanisms to the operation of memristors. As a result, neuro-inspired learning architectures can be proposed that exploit nanoscale memristors for building very large scale systems with very dense synaptic-like memory elements. At present, the deep understanding of the internal mechanisms governing memristor operation is still an open issue, and the practical realization of very large scale and reliable memristive fabric for neural learning applications is not a reality yet. However, in the meantime, researchers are proposing and analyzing potential circuit architectures that would combine a standard CMOS substrate with a memristive nanoscale fabric on top to realize hybrid memristor-CMOS neural learning systems. The focus of this paper is on one such architecture for implementing the very well established Spike-Timing-Dependent-Plasticity (STDP) learning mechanism found in biology. In this paper we quickly review spiking neural systems, STDP learning, and memristors, and propose a hybrid memristor-CMOS system architecture with the potential of implementing a large scale STDP learning spiking neural system. Such architecture would eventually allow to implement real-time brain-like processing learning systems with about neurons and synapses on one single Printed Circuit Board (PCB).

A 128x128 1.5% Contrast Sensitivity 0.9% FPN 3μs Latency 4mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers
T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp 827-838, 2013
IEEE    DOI: 10.1109/JSSC.2012.2230553    ISSN: 0018-9200    » doi
[abstract]
Dynamic Vision Sensors (DVS) have recently appeared as a new paradigm for vision sensing and processing. They feature unique characteristics such as contrast coding under wide illumination variation, micro-second latency response to fast stimuli, and low output data rates (which greatly improves the efficiency of post-processing stages). They can track extremely fast objects (e.g., time resolution is better than 100 kFrames/s video) without special lighting conditions. Their availability has triggered a new range of vision applications in the fields of surveillance, motion analyses, robotics, and microscopic dynamic observations. One key DVS feature is contrast sensitivity, which has so far been reported to be in the 10-15% range. In this paper, a novel pixel photo sensing and transimpedance pre-amplification stage makes it possible to improve by one order of magnitude contrast sensitivity (down to 1.5%) and power (down to 4mW), reduce the best reported FPN (Fixed Pattern Noise) by a factor of 2 (down to 0.9%), while maintaining the shortest reported latency (3μs) and good Dynamic Range (120 dB), and further reducing overall area (down to 30×31μm per pixel). The only penalty is the limitation of intrascene Dynamic Range to 3 decades. A 128×128 DVS test prototype has been fabricated in standard 0.35μm CMOS and extensive experimental characterization results are provided.

Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets
C. Zamarreño-Ramos, A. Linares-Barranco, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 7, no. 1, pp 82-102, 2013
IEEE    DOI: 10.1109/TBCAS.2012.2195725    ISSN: 1932-4545    » doi
[abstract]
This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating bidirectionally with all four neighbors. Address events include a module label. Each module includes an AER router which decides how to route address events. Two routing approaches have been proposed, analyzed and tested, using either destination or source module labels. Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance. Experimental results are given after testing the approach using high-end Virtex-6 FPGAs. The approach is proposed for both single and multiple FPGAs, in which case a special bidirectional parallel-serial AER link with flow control is exploited, using the FPGA Rocket-I/O interfaces. Extensive test results are provided exploiting convolution modules of 64 $,times,$64 pixels with kernels with sizes up to 11$,times,$ 11, which process real sensory data from a Dynamic Vision Sensor (DVS) retina. One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with $262 times 10^{3}~{rm neurons}$ and almost 32 million synapses.

Frame-free event-based vision sensors and processors: building smart modular mixed-signal brain-like architectures
T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Conference on Analog VLSI Circuits, 2012
[abstract]
Abstract not available

Design of adaptive nano/CMOS neural architectures
T. Serrano Gotarredona and B. Linares Barranco
Conference - IEEE International Conference on Electronics Circuits and Systems ICECS 2012
[abstract]
Memristive devices are a promising technology to implement dense learning synapse arrays emulating the high memory capacity and connectivity of biological brains. Recently, the implementation of STDP learning in memristive devices connected to spiking neurons have been demonstrated as well as the dependency of the form of the learning rule on the shape of the applied spike. In this paper, we propose a fully CMOS integrate-and-fire neuron generating a precisely shaped spike that can be tuned through programmable biases. The implementation of STDP learning is demonstrated through electrical simulations of a 4×4 array of memristors connected to 4 spiking neurons.

A 0.35μm Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links
C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Biomedical Circuits and Systems, vol. 6, no. 5, pp 486-497, 2012
IEEE    DOI: 10.1109/TBCAS.2012.2186136    ISSN: 1932-4545    » doi
[abstract]
This paper presents a low power switchable current mode driver/receiver I/O pair for high speed serial transmission of asynchronous address event representation (AER) information. The sparse nature of AER packets (also called events) allows driver/receiver bias currents to be switched off to save power. The on/off times must be lower than the bit time to minimize the latency introduced by the switching mechanism. Using this technique, the link power consumption can be scaled down with the event rate without compromising the maximum system throughput. The proposed technique has been implemented on a typical push/pull low voltage differential signaling (LVDS) circuit, but it can easily be extended to other widely used current mode standards, such as current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL). A proof of concept prototype has been fabricated in $0.35~mu{rm m}$ CMOS incorporating the proposed driver/receiver pair along with a previously reported switchable serializer/deserializer scheme. At a 500 Mbps bit rate, the maximum event rate is 11 Mevent/s for 32-bit events. In this situation, current consumption is 7.5 mA and 9.6 mA for the driver and receiver, respectively, while differential voltage amplitude is $pm 300~{rm mV}$. However, if event rate is lower than 20–30 Kevent/s, current consumption has a floor of $270~mu{rm A}$ for the driver and $570~mu{rm A}$ for the receiver. The measured ON/OFF switching times are in the order of 1 ns. The serial link could be operated at up to 710 Mbps bit rate, resulting in a maximum 32-bit event rate of 15 Mevent/s . This is the same peak event rate as that obtained with the same SerDes circuits and a non-switched drive- /receiver pair.

A real-time event-driven neuromorphic system for goal-directed attentional selection
F. Galluppi, K. Brohan, S. Davidson, T. Serrano-Gotarredona, J.A. Pérez-Carrasco, B. Linares-Barranco and S. Furber
Conference - International Conference on Neural Information Processing ICONIP2012
[abstract]
Computation with spiking neurons takes advantage of the abstraction of action potentials into streams of stereotypical events, which encode information through their timing. This approach both reduces power consumption and alleviates communication bottlenecks. A number of such spiking custom mixed-signal address event representation (AER) chips have been developed in recent years. In this paper, we present i) a flexible event-driven platform consisting of the integration of a visual AER sensor and the SpiNNaker system, a programmable massively parallel digital architecture oriented to the simulation of spiking neural networks; ii) the implementation of a neural network for feature-based attentional selection on this platform.

Comparison between frame-constrained fix-pixel-value and frame-free spiking-dynamic-pixel convNets for visual processing
C. Farabet, R. Paz, J. Pérez-Carrasco, C. Zamarreño-Ramos, A. Linares-Barranco, Y. LeCun, E. Culurciello, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 6, article 32, 2012
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2012.00032    ISSN: 1662-4548    » doi
[abstract]
Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional Neural Networks (ConvNets) are one example of such architectures that can implement general-purpose bio-inspired vision systems. In standard digital computers 2D convolutions are usually expensive in terms of resource consumption and impose severe limitations for efficient real-time applications. Nevertheless, neuro-cortex inspired solutions, like dedicated Frame-Based or Frame-Free Spiking ConvNet Convolution Processors, are advancing real-time visual processing. These two approaches share the neural inspiration, but each of them solves the problem in different ways. Frame-Based ConvNets process frame by frame video information in a very robust and fast way that requires to use and share the available hardware resources (such as: multipliers, adders). Hardware resources are fixed- and time-multiplexed by fetching data in and out. Thus memory bandwidth and size is important for good performance. On the other hand, spike-based convolution processors are a frame-free alternative that is able to perform convolution of a spike-based source of visual information with very low latency, which makes ideal for very high-speed applications. However, hardware resources need to be available all the time and cannot be time-multiplexed. Thus, hardware should be modular, reconfigurable, and expansible. Hardware implementations in both VLSI custom integrated circuits (digital and analog) and FPGA have been already used to demonstrate the performance of these systems. In this paper we present a comparison study of these two neuro-inspired solutions. A brief description of both systems is presented and also discussions about their differences, pros and cons.

A memristive nanoparticle/organic hybrid synapstor for neuroinspired computing
F. Alibart, S. Pleutin, O. Bichler, C. Gamrat, T. Serrano-Gotarredona, B. Linares-Barranco and D. Vuillaume
Journal Paper - Advanced Functional Materials, vol. 22, no. 3, pp 609-616, 2012
JOHN WILEY & SONS    DOI: 10.1002/adfm.201101935    ISSN: 1616-301X    » doi
[abstract]
A large effort is devoted to the research of new computing paradigms associated with innovative nanotechnologies that should complement and/or propose alternative solutions to the classical Von Neumann/CMOS (complementary metal oxide semiconductor) association. Among various propositions, spiking neural network (SNN) seems a valid candidate. i) In terms of functions, SNN using relative spike timing for information coding are deemed to be the most effective at taking inspiration from the brain to allow fast and efficient processing of information for complex tasks in recognition or classification. ii) In terms of technology, SNN may be able to benefit the most from nanodevices because SNN architectures are intrinsically tolerant to defective devices and performance variability. Here, spike-timing-dependent plasticity (STDP), a basic and primordial learning function in the brain, is demonstrated with a new class of synapstor (synapse-transistor), called nanoparticle organic memory field-effect transistor (NOMFET). This learning function is obtained with a simple hybrid material made of the self-assembly of gold nanoparticles and organic semiconductor thin films. Beyond mimicking biological synapses, it is also demonstrated how the shape of the applied spikes can tailor the STDP learning function. Moreover, the experiments and modeling show that this synapstor is a memristive device. Finally, these synapstors are successfully coupled with a CMOS platform emulating the pre- and postsynaptic neurons, and a behavioral macromodel is developed on usual device simulator.

An event-driven multi-kernel convolution processor module for event-driven vision sensors
L. Camuñas-Mesa, C. Zamarreño-Ramos, A. Linares-Barranco, A.J. Acosta-Jiménez, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 47, no. 2, pp 504-517, 2012
IEEE    DOI: 10.1109/JSSC.2011.2167409    ISSN: 0018-9200    » doi
[abstract]
Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) is not capturing a sequence of still frames, as in conventional video and computer vision systems. In Event-Driven sensors each pixel autonomously and asynchronously decides when to send its address out. This way, the sensor output is a continuous stream of address events representing reality dynamically continuously and without constraining to frames. In this paper we present an Event-Driven Convolution Module for computing 2D convolutions on such event streams. The Convolution Module has been designed to assemble many of them for building modular and hierarchical Convolutional Neural Networks for robust shape and pose invariant object recognition. The Convolution Module has multi-kernel capability. This is, it will select the convolution kernel depending on the origin of the event. A proof-of-concept test prototype has been fabricated in a 0.35 mu m CMOS process and extensive experimental results are provided. The Convolution Processor has also been combined with an Event-Driven Dynamic Vision Sensor (DVS) for high-speed recognition examples. The chip can discriminate propellers rotating at 2 k revolutions per second, detect symbols on a 52 card deck when browsing all cards in 410 ms, or detect and follow the center of a phosphor oscilloscope trace rotating at 5 KHz.

Sistema de reconocimiento de caracteres de alta velocidad basado en eventos
J.A. Pérez-Carrasco, B. Acha, C. Serrano, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - XXVI Edición de URSI 2011
[abstract]
Spike-based processing technology is capable of very high speed throughput, as it does not rely on sensing and processing sequences of frames. Besides, it allows building complex and hierarchically structured cortical-like layers for sophisticated processing. In this paper we summarize the fundamental properties of this sensing and processing technology applied to artificial vision systems and the AER (Address Event Representation) protocol used in hardware spiking systems. Finally a four-layer system is described for character recognition. The system is slightly based on the Fukushima's Neocognitron. Realistic simulations using figures of already existing AER devices are provided, which show recognition delays under 10 μs.

Red neuronal convolucional rápida sin fotogramas para reconocimiento de dígitos
J.A. Pérez-Carrasco, C. Serrano, B. Acha, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - XXVI Edición de URSI 2011
[abstract]
In this paper a bio-inspired six-layer convolutional network (ConvNet) non-frame based for digit recognition is shown. The system has been trained with the backpropagation algorithm using 32x32 images from the MNIST database. The system can be implemented with already physically available spike-based electronic devices. 10000 images have been coded into events separated 50ns to test the non-frame based ConvNet system. The simulation results have been obtained using actual performance figures for existing AER (Address Event Representation) hardware components. We provide simulation results of the system showing recognition delays of a few microseconds from stimulus onset with a recognition rate of 93%. The complete system consists of 30 convolution modules.

Neuromorphic silicon neuron circuits
G. Indiveri, B. Linares-Barranco, T.J. Hamilton, A. van Schaik, R. Etienne-Cummings, T. Delbruck, Shih-Chii Liu, P. Dudek, P. Häfliger, S. Renaud, J. Schemmel, G. Cauwenberghs, J. Arthur, K. Hynna11, F. Folowosele, S. Saighi, T. Serrano-Gotarredona, J. Wijekoon, Y. Wang1 and K. Boahen
Journal Paper - Frontiers in Neuroscience, vol. 5,article 73, 2011
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2011.00073    ISSN: 1662-4548    » doi
[abstract]
Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

A Bioinspired 128x128 Pixel Dynamic-Vision-Sensor
T. Serrano-Gotarredona, J.A. Leñero-Bardallo and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2011
[abstract]
This paper presents a 128x128 dynamic vision sensor. Each pixel detects temporal changes in the local illumination. A minimum illumination temporal contrast of 10% can be detected. A compact preamplification stage has been introduced that allows to improve the minimum detectable contrast over previous designs, while at the same time reducing the pixel area by 1/3. The pixel responds to illumination changes in less than 3.6μs. The ability of the sensor to capture very fast moving objects has been verified experimentally. A frame-based sensor capable to achieve this, would require at least 100K frames per second.

An instant-startup jitter-tolerant manchester-encoding serializer/deserializer scheme for event-driven bit-serial LVDS interchip AER links
C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 58, no. 11, pp 2647-2660, 2011
IEEE    DOI: 10.1109/TCSI.2011.2151070    ISSN: 1549-8328    » doi
[abstract]
This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage differential signaling (LVDS) and two handshaking lines. Each event is represented by a 32-bit word. Two extra preamble bits are used for alignment. Transmission clock is embedded in the data using Manchester encoding. As opposed to conventional LVDS links, the presented approach allows to stop physical communication between data events, so that no "comma" characters need to be transmitted during these pauses. As soon as a new event needs to be transmitted, the link recovers immediately thanks to a built-in control voltage memorization circuit. As a result, power consumption of the serializer and deserializer circuits is proportional to data event rate. The approach is also highly tolerant to clock jitter, due to the asynchronous nature and the Manchester encoding. A chip test prototype has been fabricated in standard 0.35 mu m CMOS including a pair of Serializer and Deserializer circuits. Maximum measured event transmission rate is 15 Meps (mega events per second) for 32-bit events, with a maximum bit transmission speed of 670 Mbps (mega bits per second).

Voltage mode driver for low power transmission of high speed serial AER links
C. Zamarreño-Ramos, T. Serrano-Gotarredona, B. Linares-Barranco, R. Kulkarni and J. Silva-Martínez
Conference - International Symposium on Circuits and Systems ISCAS 2011
[abstract]
This paper presents a voltage-mode high speed driver to transmit serial AER data in scalable multi-chip AER systems. To take advantage of the asynchronous nature of AER (Address Event Representation) streams, this implementation allows an energy efficient burst-mode operation. This is achieved by switching on/off the driver in data pauses to reduce static power consumption. Impedance matching is calibrated continuously to track temperature variations, obtaining an optimal performance without degrading the data rate. Power management techniques for switching drivers are discussed and an internally compensated high speed regulator is presented. The system has been designed in a 0.35 mu m CMOS technology to transmit data rates up to 500Mbps using Manchester enconding. Layout extracted simulation results are presented, which include all interconnect parasitics. Estimated peak rate is 15Meps for 32 bit events. Simulated power consumption of transmitter and receiver at peak rate is 33.2mW, while below 100 Keps is 1.3mW.

On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex
C. Zamarreño-Ramos, L.A. Camuñas-Mesa, J.A. Pérez-Carrasco, T. Masquelier, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Frontiers in Neuroscience, vol. 5, article 26, 2011
FRONTIERS RESEARCH FOUNDATION    DOI: 10.3389/fnins.2011.00026    ISSN: 1662-4548    » doi
[abstract]
In this paper we present a very exciting overlap between emergent nanotechnology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nanotechnology devices to the biological synaptic update rule known as spike-time-dependent-plasticity (STDP) found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage or flux driven memristors and focus our discussions on a behavioral macro-model for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forward but also backward. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We will briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We will illustrate how a V1 visual cortex layer can assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim of this paper is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three-terminal memristive type devices. All files used for the simulations are made available through the journal web site.

A 3.6 μs latency asynchronous frame-free event-driven dynamic-vision-sensor
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp 1443-1455 2011
IEEE    DOI: 10.1109/JSSC.2011.2118490    ISSN: 0018-9200    » doi
[abstract]
This paper presents a 128 x 128 dynamic vision sensor. Each pixel detects temporal changes in the local illumination. A minimum illumination temporal contrast of 10% can be detected. A compact preamplification stage has been introduced that allows to improve the minimum detectable contrast over previous designs, while at the same time reducing the pixel area by 1/3. The pixel responds to illumination changes in less than 3.6 mu s. The ability of the sensor to capture very fast moving objects, rotating at 10 K revolutions per second, has been verified experimentally. A frame-based sensor capable to achieve this, would require at least 100 K frames per second.

The EKV/ACM compact models for mismatch modeling down to 90nm and for new emergent non-CMOS nanotechnology FETs
T. Serrano-Gotarredona and B. Linares-Barranco
Conference - MOS-AK/GSA Workshop 2010
[abstract]


A calibrated spatial contrast AER vision sensor with adjustable contrast threshold
J.A Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Symposium on Circuits and Systems ISCAS 2010
[abstract]
Abstract not available

A 100dB dynamic range event-driven spatial contrast sensor with 100us response time and time-to-first-spike mode
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares Barranco
Conference - European Solid State Circuits Conference ESSCIRC 2010
[abstract]
Bio-inspired vision sensors have some inherent advantages over conventional sequential-still-image sensors. Some of them are high speed, low latency and reduced bandwidth and power consumption. In this paper, we present a new spatial contrast retina with signed output. Its output is zero if there is no contrast. The new sensor includes an optional Time-to-First-Spike mode (TFS) that combines the advantages of AER vision systems and frame-based ones. In TFS mode, times between consecutive frames can be adjusted dynamically by transmitting only relevant information. Both operation modes are ambient-light-independent, to first order. A 32x32 pixel prototype has been fabricated in 0.35um CMOS. Experimental results are provided. ©2010 IEEE.

Spike-based convolutional network for real-time processing
J.A. Pérez-Carrasco, C. Serrano, B. Acha, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Conference on Pattern Recognition ICPR 2010
[abstract]
In this paper we propose the first bio-inspired six-layer convolutional network (ConvNet) non-frame based that can be implemented with already physically available spike-based electronic devices. The system was designed to recognize people in three different positions: standing, lying or up-side-down. The inputs were spikes obtained with a motion retina chip. We provide simulation results showing recognition delays of 16 milliseconds from stimulus onset (time-to-first spike) with a recognition rate of 94%. The weight sharing property in ConvNets and the use of AER protocol allow a great reduction in the number of both trainable parameters and connections (only 748 trainable parameters and 123 connections in our AER system (out of 506998 connections that would be required in a frame-based implementation). © 2010 IEEE.

A 32x32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 Meps throughput
L. Camuñas-Mesa, A. Acosta-Jiménez, C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 58, no. 4, pp 777-790, 2011
IEEE    DOI: 10.1109/TCSI.2010.2078851    ISSN: 1549-8328    » doi
[abstract]
This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, information is represented by a continuous flow of self-timed asynchronous events. Such events can be processed on the fly by event-based convolution chips, providing at their output a continuous event flow representing the 2-D filtered version of the input flow. In this paper we present a 32 x 32 pixel 2-D convolution event processor whose kernel can have arbitrary shape and size up to 32 x 32. Arrays of such chips can be assembled to process larger pixel arrays. Event latency between input and output event flows can be as low as 155 ns. Input event throughput can reach 20 Meps (mega events per second), and output peak event rate can reach 45 Meps. The chip can be configured to discriminate between two simulated propeller-like shapes rotating simultaneously in the field of view at a speed as high as 9400 rps (revolutions per second). Achieving this with a frame-constraint system would require a sensing and processing capability of about 100 K frames per second. The prototype chip has been built in 0.35 mu m CMOS technology, occupies 4.3 x 5.4 mm(2) and consumes a peak power of 200 mW at maximum kernel size at maximum input event rate.

A five-decade dynamic-range ambient-light-independent calibrated signed-spatial-contrast AER retina with 0.1-ms latency and optional time-to-first-spike mode
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, no. 10, pp 2632-2643, 2010
IEEE    DOI: 10.1109/TCSI.2010.2046971    ISSN: 1549-8328    » doi
[abstract]
Address Event Representation (AER) is an emergent technology for assembling modular multiblock bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since the introduction of the technology. Spatial-contrast AER retinae are of special interest since they provide highly compressed data flow without reducing the relevant information required for performing recognition. The reported AER contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighborhood. This resulted in compact circuits but with the penalty of all pixels generating output signals even if they sensed no contrast. In this paper, we present a spatial-contrast retina with a signed output: Contrast is computed as the relative difference (not the ratio) between a pixel's local light and its surrounding spatial average and normalized with respect to ambient light. As a result, contrast is ambient light independent, includes a sign, and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast-computation circuit is based on Boahen's biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive-current-based biasing. As a result, the contrast-computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. The retina includes an optional global reset mechanism for operation in ambient-light-independent Time-to-First-Spike contrast-computation mode. A 32 32 pixel test prototype has been fabricated in 0.35-mu m CMOS. Experimental results are provided.

On neuromorphic spiking architectures for asynchronous STDP memristive systems
J.A. Pérez-Carrasco, C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2010
[abstract]
Neuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways of building neural network systems for sophisticated pattern recognition tasks using memristors. We will focus on spiking signal coding because of its energy and information coding efficiency, and concentrate on Convolutional Neural Networks because of their good scaling behavior, both in terms of number of synapses and temporal processing delay. We propose asynchronous architectures that exploit memristive synapses with specially designed neurons that allow for arbitrary scalability as well as STDP learning. We present some behavioral simulation results for smail neural arrays using electrical circuit simulators, and system level spike processing results on human detection using a custom made event based simulator.

A signed spatial contrast event spike retina chip
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2010
[abstract]
Reported AER (Address Event Representation) contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighbourhood. This results in compact circuits, but with the penalty of all pixels generating output signals even if they sense no contrast. In this paper we present a spatial contrast retina with bipolar output: contrast is computed as the relative normalized difference (not the ratio) between a pixel's local light and its weighted spatial average, normalized to average light. As a result contrast includes a sign, is ambient light independent, and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast computation circuit is based on Boahen's Biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive current based biasing. As a result, the contrast computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. The retina also includes an optional TFS (Time-to-First-Spike) integration mode. A full AER retina version has been fabricated and tested. In the present paper we provide preliminary experimental results.

On scalable spiking ConvNet hardware for cortex-like visual sensory processing systems
L. Camuñas-Mesa, J.A. Pérez-Carrasco, C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2010
[abstract]
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition tasks operating at mili second delay throughputs. Although such hardware would required hundreds of individual convolutional modules and thus is presently not yet available, we discuss methods and technologies for implementing it in the near future. On the other hand, we provide precise behavioral simulations of large scale spiking AER convolutional hardware and evaluate its performance, by using performance figures of already available AER convolution chips fed with real sensory data obtained from physically avaliable AER motion retina chips. We provide simulation results of systems trained for people recognition, showing recognition delays of a few milliseconds from stimulus onset. ConvNets show good up scaling behavior and possibilities for being implemented efficiently with new nano scale hybrid CMOS/nonCMOS technologies.

Neocortical frame-free vision sensing and processing through scalable spiking Convet hardware
L. Camuñas-Mesa, J.A. Pérez-Carrasco, C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares Barranco
Conference - IEEE World Congress on Computational Intelligence WCCI 2010
[abstract]
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition tasks operating at mili second delay throughputs. Although such hardware would require hundreds of individual convolutional modules and thus is presently not yet available, we discuss methods and technologies for implementing it in the near future. On the other hand, we provide precise behavioral simulations of large scale spiking AER convolutional hardware and evaluate its performance, by using performance figures of already available AER convolution chips fed with real sensory data obtained from physically available AER motion retina chips. We provide simulation results of systems trained for people recognition, showing recognition delays of a few miliseconds from stimulus onset. ConvNets show good up scaling behaviour and possibilities for being implemented efficiently with new nano scale hybrid CMOS/nonCMOS technologies.

Fast vision through frameless event-based sensing and convolutional processing: Application to texture recognition
J.A. Pérez-Carrasco, B. Acha, C. Serrano, L. Camuñas-Mesa, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Neural Networks, vol. 21, no. 4, pp 609-620, 2010
IEEE    DOI: 10.1109/TNN.2009.2039943    ISSN: 1045-9227    » doi
[abstract]
Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used for vision, AER sensors and processors are not restricted to capturing and processing still image frames, as in commercial frame-based video technology, but sense and process visual information in a pixel-level event-based frameless manner. As a result, vision processing is practically simultaneous to vision sensing, since there is no need to wait for sensing full frames. Also, only meaningful information is sensed, communicated, and processed. Of special interest for brain-like vision processing are some already reported AER convolutional chips, which have revealed a very high computational throughput as well as the possibility of assembling large convolutional neural networks in a modular fashion. It is expected that in a near future we may witness the appearance of large scale convolutional neural networks with hundreds or thousands of individual modules. In the meantime, some research is needed to investigate how to assemble and configure such large scale convolutional networks for specific applications. In this paper, we analyze AER spiking convolutional neural networks for texture recognition hardware applications. Based on the performance figures of already available individual AER convolution chips, we emulate large scale networks using a custom made event-based behavioral simulator. We have developed a new event-based processing architecture that emulates with AER hardware Manjunath's frame-based feature recognition software algorithm, and have analyzed its performance using our behavioral simulator. Recognition rate performance is not degraded. However, regarding speed, we show that recognition can be achieved before an equivalent frame is fully sensed and transmitted.

Low power LVDS transceiver for AER links with burst mode operation capability
C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Design of Circuits and Integrated Systems Conference DCIS 2009
[abstract]
This paper presents the design and simulation of an LVDS transceiver intended to be used in serial AER links. Traditional implementations of LVDS serial interfaces require a continuous data flow between the transmitter and the receiver to keep the synchronization. However, the serial AER-LVDS interface proposed in [2] operates in a burst mode, having long times of silence without data transmission. This can be used to reduce the power consumption by switching off the LVDS circuitry during the pauses. Moreover, a fast recovery time after pauses must be achieved to not slow down the interface operation. The transceiver was designed in a 90 nm technology. Extensive simulations have been performed demonstrating a 1 Gbps data rate operation for all corners in post-layout simulations. Driver and receiver take up an area of 100x215 μm2 and 100x140 μm2 respectively.

improved AER convolution chip for vision processing with higher resolution and new functionalities
L.A. Camuñas-Mesa, A. Linares-Barranco, A. Acosta, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2009
[abstract]
We present a new neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing system. This chip computes 2-D convolutions with a programmable kernel in real time. Previously, we designed and tested another convolution chip with a size of 32 x 32 pixels [1] and, based on the information obtained from this test, we have designed a new chip with larger resolution (64 x 64 pixels), improved behavior and new functionalities included. This chip receives and generates data in AER format, which is an asynchronous protocol, implementing the convolution of the input images with a programmable kernel. The most important new functionality included in this chip is the multikernel capability, which allows us to program several kernels (up to 32) so that each input event will be processed with the corresponding kernel, depending on the origin of the input event. The paper describes the architecture of the chip, with special emphasis to the new improvements.

Fast and compact simulation models for a variety of FET nano devices by the CMOS EKV equations
T. Serrano-Gotarredona, B. Linares-Barranco, G.Agnus, V. Derycke, J.-P. Bourgoin, F. Alibart, D. Vuillaume, J. Sohn, J. Bendall, M.E. Welland and Gamrat, C.
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2009
[abstract]
In this paper we explore the possibility of using the equations of a well known compact model for CMOS transistors as a parameterized compact model for a variety of FET based nano-technology devices. This can turn out to be a practical preliminary solution for system level architectural researchers, who could simulate behaviourally large scale systems, while more physically based models become available for each new device. We have used a four parameter version of the EKV model equations and verified that fitting errors are similar to those when using them for standard CMOS FET transistors. The model has been used for fitting measured data from three types of FET nano-technology devices obeying different physics, for different fabrication steps, and under different programming conditions.

Exploiting memristance in adaptive asynchronous spiking neuromorphic nanotechnology systems
B. Linares-Barranco and T. Serrano-Gotarredona
Conference - IEEE Conference on Nanotechnology IEEE-NANO 2009
[abstract]
In this paper we show that spike-time-dependent-plasticity (STDP), a powerful learning paradigm for spiking neural systems, can be implemented using a crossbar memristive array combined with neurons that asynchronously generate spikes of a given shape. Such spikes need to be sent back through the neurons input terminal. The shape of the spikes turns out to be very similar to the neural spikes observed in biology for real neurons. The STDP learning function obtained by combining such neurons with memristors is exactly that of the STDP learning function obtained from neurophysiological experiments on real synapses. Using this result, we propose memristive crossbar architectures capable of performing asynchronous STDP learning.

Exploiting memristance for implementing spike-time-dependent-plasticity in neuromorphic nanotechnology systems
B. Linares-Barranco and T. Serrano-Gotarredona
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2009
[abstract]
Abstract not avaliable

A spatial calibrated AER contrast retina with adjustable contrast threshold
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2009
[abstract]
Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since the introduction of the technology. Spatial contrast AER retinae are of special interest since they provide highly compressed data flow without reducing the relevant information required for performing recognition. Reported AER contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighbourhood. This results in compact circuits, but with the penalty of all pixels generating output signals even if they sensed no contrast. In this paper we present a spatial contrast retina with bipolar output: contrast is computed as the relative difference between a pixel's local light and its weighted spatial average. As a result, contrast includes a sign and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast computation circuit is based on Boahen's Biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive current based biasing. As a result, the contrast computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. A full AER retina version has been fabricated. In the present paper we provide simulation and preliminary experimental results.

Plan de Renovación de las Metodologías Docentes. Asignaturas en la Red 2008-2009. Arquitectura de Computadores
D. Cagigas-Muñiz, A.A. Civit-Balcells, M.R. García-Robles, M.R. López-Torres, C.D. Luján-Martínez, J.L. Sevillano-Ramos, R. Senhadji-Navarro, B. Linares-Barranco, T. Serrano-Gotarredona, D. Cascado-Caballero, J.L. Guisado-Lizar, L. Miró-Amarante and A.F. Jiménez-Fernández
Book - 2009
UNIVERSIDAD DE SEVILLA    ISBN: 978-84-692-1211-0    
[abstract]
Abstract not available

CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, L. Camuñas-Mesa, R. Berner, M. Rivas-Pérez, T. Delbrueck, S.C. Liu, R. Douglas, P. Hafliger, G. Jiménez-Moreno, A. Civit-Ballcels, T. Serrano-Gotarredona, A.J. Acosta-Jiménez and B. Linares-Barranco
Journal Paper - IEEE Transactions on Neural Networks, vol. 20, no. 9, pp 1417-1438, 2009
IEEE    DOI: 10.1109/TNN.2009.2023653    ISSN: 1045-9227    » doi
[abstract]
This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

Advanced vision processing systems: spike-based simulation and processing
J.A. Pérez-Carrasco, C. Serrano-Gotarredona, B. Acha-Piñero, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Conference on Advanced Concepts for Intelligent Vision Systems ACIVS 2009
[abstract]
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured neurocortical-like layers for sophisticated processing. The paper describes briefly cortex-like spike event vision processing principles, and the AER, (Address Event Representation) technique used in hardware spiking systems. In this paper we present a simulation AER, tool that we have developed entirely in Visual C++ 6.0. We have validated it using real AER, stimulus and comparing the outputs with real outputs obtained from AER-ba.sed devices. With this tool we can predict the eventual performance of AER-based systems, before the technology becomes mature enough to allow such large systems.

A mismatch calibrated bipolar spatial contrast AER retina with adjustable contrast threshold
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Symposium on Circuits and Systems ISCAS 2009
[abstract]
Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since the introduction of the technology. Spatial contrast AER retinae are of special interest since they provide highly compressed data flow without reducing the relevant information required for performing recognition. Reported AER contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighbourhood. This resulted in compact circuits, but with the penalty of all pixels generating output signals even if they sensed no contrast. In this paper we present a spatial contrast retina with bipolar output: contrast is computed as the relative difference between a pixel's local light and its weighted spatial average. As a result, contrast includes a sign and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute contrast above the adjustable threshold. The pixel contrast computation circuit is based on Boahen's Biharmonic operator contrast circuit, which has been improved to include mismatch calibration and adaptive current based biasing. As a result, the contrast computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much less critical than in the original voltage biasing scheme. A full AER retina version has been submitted for fabrication. In the present paper we provide simulation results.

OTA-C oscillator with low frequency variations for on-chip clock generation in serial LVDS-AER links
C. Zamarreño-Ramos, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2009
[abstract]
This paper presents the design and simulation of an OTA-C oscillator intended to be used as on-chip frequency reference. This reference will be part of the high speed clock generation circuit for Manchester serial LVDS-AER links. A Manchester LVDS receiver can adapt its operation in a limited range of frequencies, so the most important specification is the frequency stability over temperature and process variations. A novel design methodology is presented to design two oscillators in a 9nm technology using transistors with 2.5V supply voltage. Intensive simulations with temperature, process, supply voltage variations and mismatch effects were perfomed in order to analyze the validity of this approach, obtaining Delta f approximate to 7%.

A weak-to-strong inversion mismatch model for analog circuit design
G. Vicente-Sánchez, J. Velarde-Ramírez, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 59, no. 3, pp 325-340, 2009
SPRINGER    DOI: 10.1007/s10470-008-9256-8    ISSN: 0925-1030    » doi
[abstract]
Abstract not available

Fully digital AER convolution chip for vision processing
L. Camuñas-Mesa, A. Acosta-Jiménez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2008
[abstract]
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 x 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 x 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype. ©2008 IEEE.

Event based vision sensing and processing
J.A. Pérez-Carrasco, C. Serrano, B. Acha, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Conference on Image Processing ICIP 2008
[abstract]
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper describes briefly cortex-like spike event vision processing principles, and the AER (Address Event Representation) techique used in hardware spiking systems. Then a texture-based image retrieval using the AER technique is proposed. Realistic behavioral simulations based on existing hardware characteristics, reveal that the application, although processing large kernel convolutions, is capable of performing recognition in less than I Orris.

LVDS interface for AER links with burst mode operation capability
C. Zamarreño-Ramos, R. Serrano-Gotarredona, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2008
[abstract]
This paper presents the design and simulation of a serial AER LVDS communication link. It converts data from classical AER parallel bus with a 4-phase handshaking protocol into a bit stream which is transmitted serially into a single LVDS wire. At the receiver side data from the LVDS cable are transformed back to a parallel AER bus and handshaking signals are also properly managed. The link has been designed in a 90 nms technology. Extensive simulations have been performed demonstrating that the link can operate at a speed of 1 Gbps for all the technology corners, exhibiting a power consumption of 27.8 mW for the transmitter and 12.3 mW for the receiver. In the simulation the transmission channel was modelled as a 50 cm cat5E UTP cable, connected to the AER chip through 5 cm PCB traces modelled as a coupled microstrip transmission line. The design has been completed up to the layout level and has been submitted for fabrication. The transmitter and the receiver take up an area of 311x148 mu m(2) and 300x148 mu m(2) respectively.

Compact calibration circuit for large neuromorphic arrays
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - International Symposium on Circuits and Systems ISCAS 2008
[abstract]
Low current applications, like neuromorphic circuits, where operating currents can be as low as few nano amps or less, suffer from huge transistor mismatches, resulting in around or less than I-bit precision. Here we present a new calibration approach based on individually calibratable current sources made with MOS transistors of digitally adjustable length, which require only N unit transistors. The scheme includes a translinear circuit based tuning scheme, which allows to expand the operating range of the calibrated circuits with graceful precision degradation, over 4 decades of operating currents. Experimental results are provided for 5-bit resolution DACs operating at 20nA.

High-speed character recognition system based on a complex hierarchical AER architecture
J.A Pérez-Carrasco, T. Serrano-Gotarredona, C. Serrano-Gotarredona, B. Acha and B. Linares Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2008
[abstract]
In this paper we briefly summarize the fundamental properties of spikes processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper describes briefly cortex-like spiking vision processing principles, and the AER (Address Event Representation) technique used in hardware spiking systems. Afterwards an example application is described, which is a simplification of Fukushima's Neocognitron. Realistic behavioral simulations based on existing AER hardware characteristics, reveal that the simplified neocognitron, although it processes 52 large kernel convolutions, is capable of performing recognition in less than 10 mu s..

On real-time AER 2-D convolutions hardware for neuromorphic spike-based cortical processing
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez, C. Serrano-Gotarredona, J.A. Pérez-Carrasco, B. Linares-Barranco, A. Linares-Barranco, G. Jiménez-Moreno and A. Civit-Ballcels
Journal Paper - IEEE Transactions on Neural Networks, vol. 19, no. 7, pp 1196-1219, 2008
IEEE    DOI: 10.1109/TNN.2008.2000163    ISSN: 1045-9227    » doi
[abstract]
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address-event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16 x 16 has been implemented with programmable kernel size of up to 16 x 16. The chip has been fabricated in a standard 0.35-mu m complimentary metal-oxide-semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog-digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems.

A calibration technique for very low current and compact tunable neuromorphic cells: Application to 5-bit 20-nA DACs
J.A. Leñero-Bardallo, T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 6, pp 522-526, 2008
IEEE    DOI: 10.1109/TCSII.2007.916864    ISSN: 1549-7747    » doi
[abstract]
Low current applications, like neuromorphic circuits, where operating currents can be as low as a few nanoamperes or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precisions. Recently, a neuromorphic programmable-kernel 2-D convolution chip has been reported where each pixel included two compact calibrated digital-to-analog converters (DACs) of 5-bit resolution, for currents down to picoamperes. Those DACs were based on MOS ladder structures, which although compact require 3N + 1 unit transistors (N is the number of calibration bits). Here, we present a new calibration approach not based on ladders, but on individually calibratable current sources made with MOS transistors of digitally adjustable length, which require only N-sized transistors. The scheme includes a translinear circuit-based tuning scheme, which allows us to expand the operating range of the calibrated circuits with graceful precision degradation, over four decades of operating currents. Experimental results are provided for 5-bit resolution DACs operating at 20 nA using two different translinear tuning schemes. Maximum measured precision is 5.05 and 7.15 b, respectively, for the two DAC schemes.

Image Processing Architecture Based on a Fully Digital Aer Convolution Chip
L.A. Camuñas-Mesa, A.J. Acosta-Jimenez, T. Serrano-Gotarredona, B. Linares-Barranco and R. Serrano Gotarredona
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2007
[abstract]
Abstract not avaliable

Spike events processing for vision systems
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez, A. Linares-Barranco, G. Jiménez-Moreno, A. Civit-Balcells and B. Linares-Barranco
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper includes a few examples that have demonstrated the potential of this technology for highspeed vision processing, such as a multilayer event processing network of 5 sequential cortical-like layers, and a recognition system capable of discriminating propellers of different shape rotating at 5000 revolutions per second (300000 revolutions per minute).

A physical interpretation of the distance tenn in Pelgrom's mismatch model results in very efficient CAD
B. Linares-Barranco and T. Serrano-Gotarredona
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
In 1989 Pelgrom et al. published a mismatch model for MOS transistors, where the standard quadratic deviation of the mismatch in a parameter between two identical transistors, is given by two independent terms: (1) a transistor size-dependent term and (2) an inter-transistor distance-dependent term. To include the distance term, some researchers have developed CAD tools based on the so called (sigma-Space Methodology, which result in very computationally expensive algorithms. Such algorithms become non-viable even for circuits with a reduced number of transistors. On the other hand, by understanding and interpreting correctly the physical origin of Pelgrom's model distance term, one can implement in a straight forward manner this mismatch contribution in a CAD tool. Furthermore, the computational cost results negligible and viable for any number of transistors.

An AER contrast retina with on-chip calibration
J. Costas-Santos, T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2007
[abstract]
We present a contrast retina microchip that provides its output as an AER (Address Event Representation) stream. Contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffusive network. This current based computation produces a large mismatch between neighboring pixels, because the currents can be as low as a few pico amperes. Consequently, a compact calibration circuitry has been included to calibrate each pixel. The paper describes the design of the pixel with its contrast computation and calibration sections. Experimental results are provided for a prototype fabricated in a standard 0.35 mu m CMOS process.

The stochastic I-Pot: A circuit block for programming bias currents
R. Serrano-Gotarredona, L. Camuñas-Mesa, T. Serrano-Gotarredona, J.A. Leñero-Bardallo and B. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 9, pp 760-764, 2007
IEEE    DOI: 10.1109/TCSII.2007.900881    ISSN: 1549-7747    » doi
[abstract]
In this brief, we present the "Stochastic I-Pot." It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number of programmable bias currents. The approach only requires to provide the chip with three external pins, the use of an external current measuring instrument, and a computer. This way, once all internal I-Pots have been characterized, they can be programmed through a computer to provide any desired current bias value with very low error. The circuit block turns out to be very practical for experimenting with new circuits (specially when a large number of biases are required), testing wide ranges of biases, introducing means for current mismatch calibration, offsets compensations, etc. using a reduced number of chip pins. We show experimental results of generating bias currents with errors of 0.38% (8 bits) for currents varying from 176 mu A to 19.6 pA. Temperature effects are characterized.

On an efficient CAD implementation of the distance term in Pelgrom's mismatch model
B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp 1534-1538, 2007
IEEE    DOI: 10.1109/TCAD.2007.893546    ISSN: 0278-0070    » doi
[abstract]
In 1989, Pelgrom et al published a mismatch model for MOS transistors, where the variation of parameter mismatch between two identical transistors is given by two independent terms: a size-dependent term and a distance-dependent term. Some CAD tools based on a nonphysical interpretation of Pelgrom's distance term result in excessive computationally expensive algorithms, which become nonviable even for circuits with a reduced number of transistors. Furthermore, some researchers are reporting new variations on the original nonphysically interpreted algorithms, which may render false results. The purpose of this paper is to clarify the physical interpretation of the distance term of Pelgrom et al. and indicate how to model it efficiently in prospective CAD tools.

A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems
J. Costas-Santos, T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares Barranco
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 54, no. 7, pp 1444-1458, 2007
IEEE    DOI: 10.1109/TCSI.2007.900179    ISSN: 1549-8328    » doi
[abstract]
We present a 32 x 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring,pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mu m x 56 mu m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mu m CMOS process.

An accurate automatic quality-factor tuning scheme for second-order LC filters
F. Bahmani, T. Serrano-Gotarredona and E. Sánchez-Sinencio
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 54, no. 4, pp 745-756, 2007
IEEE    DOI: 10.1109/TCSI.2006.888783    ISSN: 1549-8328    » doi
[abstract]
This paper presents a scheme to accurately tune the quality factor of second-order LC bandpass filters. The information of the magnitude response at the center and one of the cutoff frequencies is used to tune both the amplitude and the quality factor of the filter using two independent yet interacting loops. Furthermore, the synergic interaction between the loops makes the proposed scheme stable and insensitive to the mismatch between the input amplitudes. A chip prototype was implemented in a 0.35-mu m CMOS process and consumes 4.3 mA from a single 1.3-V supply. Measurement results show that at 1.97 GHz the quality factor is tunable from 60 to 220 while the ampltude is tunable between -15 and 0 dBm with worst case quality factor and amplitude tuning accuracies of 10% and 7%, respectively.

A bio-inspired event-based real-time image processor
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A.J. Acosta-Jiménez, B. Linares-Barranco and L.A. Camuñas-Mesa
Conference - IEEE RAS-EMBS International Conference on Biomedical Robotics and Biomechatronics BioRob 2006
[abstract]
AER (Address Event Representation) is an emergent bio-inspired protocol intended to communicate chips containing many processing units, called them neurons or pixels. It exploits the advantages of communicating the activation state of a neuron as pulses, as done in the human brain. The information is sent out sorted beginning with the most relevant. This feature together with the parallel processing of the information allows for performing very fast image processing. In this paper, we explain how AER is suitable for real-time image processing and, as an example, we present results from some AER-based convolution chips which is able to perform convolutions in real time.

High-speed image processing with AER-based components
R. Serrano-Gotarredona, B. Linares-Barranco, T. Serrano-Gotarredona, A.J. Acosta-Jiménez, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, G. Jiménez-Moreno and A. Civit-Ballcels
Conference - International Symposium on Circuits and Systems ISCAS 2006
[abstract]
A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions /see) to show event-based systems capabilities in high speed applications. Event-based schemes allow the most relevant information to propagate faster through the system layers. So image processing is sped up because a rough result may be available when only a little part of the input has arrived. This setup is much faster than the conventional frame-based image processing systems because they would need to proccess more than 10kFrames/s to do the same task proposed here, whereas only few events are required with the event based technique.

An arbitrary kernel convolution AER-transceiver chip for real-time image filtering
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A.J. Acosta-Jiménez and B. Linares-Barranco
Conference - International Symposium on Circuits and Systems ISCAS 2006
[abstract]
A new chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. This is a first prototype of reduced size (16x16 pixels) to validate system level techniques. It has been fabricated in AMS-0.35 mu n, 2-poly, 3-metal technology. Chip inputs and outputs are coded using Address Event Representation (AER). This is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of pixels located on different chips. Pixels generate 'events' according to their activity levels. More active pixels generate more events per unit time and access the interchip communication channel more frequently, whereas pixels with low activity consume less communication bandwidth. This allows to communicate more relevant information in a very short time. Specific PCI boards have been developed to feed images into the chip and to read images out of it.

A neuromorphic cortical-layer microchip for spike-based event processing vision systems
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez and B. Linares Barranco
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 53, no. 12, pp 2548-2566, 2006
IEEE    DOI: 10.1109/TCSI.2006.883843    ISSN: 1057-7122    » doi
[abstract]
We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 x 32 pixels. The convolution processor operates on a pixel array of size 32 x 32, but can process an input space of up to 128 x 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second.

A low-power current mode fuzzy-ART cell
T. Serrano-Gotarredona and B. Linares Barranco
Journal Paper - IEEE Transactions on Neural Networks, vol. 17, no. 6, pp 1666-1673, 2006
IEEE    DOI: 10.1109/TNN.2006.883725    ISSN: 1045-9227    » doi
[abstract]
This paper presents a very large scale integration (VLSI) implementation of a low-power current-mode fuzzy-adaptive resonance theory (ART) cell. The cell is based on a compact new current source multibit memory cell with online learning capability. A small prototype of the designed cell and its peripheral block has been fabricated in the AustriaMicroSystems (AMS)-0.35-mu m technology. The cell occupies a total area of 44 x 34 mu m(2) and consumes a maximum current of 22 nA.

A Programmable Convolution Chip Prototype for Real-Time Image Filtering
R. Serrano-Gotarredona, M.T. Serrano-Gotarredona, A.J. Acosta-Jimenez, B. Linares-Barranco, C. Serrano-Gotarredona, et. al
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2005
[abstract]
Abstract not available

AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodríguez, H. Kolle-Riis, T. Delbrück, S.C. Liu, S. Zahnd, A.M. Whatley, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit, T. Serrano-Gotarredona, A. Acosta-Jiménez and B. Linares-Barranco
Conference - Neural Information Processing Systems Conference NIPS 2005
[abstract]
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a 2D winner-take-all chip, a delay line chip, a learning classifier chip, and a set of PCBs for computer interfacing and address space remappings. The components use a mixture of analog and digital computation and will learn to classify trajectories of a moving object. A complete experimental setup and measurements results are shown.

On Fully Digital Address-Event-Representation Convolution Processing
L. Camuñas-Mesa, A.J. Acosta-Jimenez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2005
[abstract]
Abstract not avaliable

On event generators for Address Event Representation transmitters
R. Serrano-Gotarredona, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
Address Event Representation (AER)[1] is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. In a typical AER transmitter chip, there is an array of neurons that generate events. They send events to a peripheral circuitry (let's call it "AER Generator") that transforms those events to neurons coordinates (addresses) which are put sequentially on an interchip high speed digital bus. Several techniques for implementing AER generators have been published [11-[8]. We have analyzed and studied some of them and have detected some shortcomings in the circuits reported, which may render some false situations under some statistical conditions. The present paper proposes some improvements to overcome such situations. The improved "AER Generator" has been implemented in an AER transmitter system.

A mismatch characterization and simulation environment for weak-to-strong inversion CMOS transistors
J. Velarde-Ramírez, G. Vicente-Sánchez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
Mismatch analysis and simulation is crucial for modem analog design with submicron technologies, where transistors tend to be biased in weak and moderate inversion regions because of the down shrinking of power supply voltage. For optimum analog design where speed, power consumption, area, noise, and accuracy need to be carefully traded off, it is crucial to have available a precise estimation of transistor mismatch in order to avoid overdesign and consequently sacrify unnecessarily speed, power consumption, and area. In this paper we will provide experimental mismatch measurements of different 0.35um CMOS technologies. Each technology has been characterized for a large number of transistor sizes (25-30), by sweeping different width and length values. A large number of transistor curves are measured ranging over different possible biasing conditions. A recent mismatch model will be used to fit the data, and extract electrical parameters. Some of those parameters will be used to adjust the measured mismatch. As a result, a set of standard deviations and correlation coefficients result for the statistical characterization of the mismatch responsible parameters. The resulting electrical parameters, and statistical mismatch parameters are then used in the Spectre simulator of Cadence design environment, to implement the mismatch models using the AHDL behavioral level Spectre description language. The paper shows good agreement between measured data, predicted data, and simulated data.

A digital pixel cell for address event representation image convolution processing
L. Camuñas-Mesa, A. Acosta-Jiménez, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of vaRíous type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

A calibration scheme for subthreshold current mode circuits
J.C. Santos, T. Serrano-Gotarredona and B. Linares-Barranco
Conference - Conference on Bioengineered and Bioinspired Systems II, 2005
[abstract]
Abstract not available

Log-domain circuit techniques for nonlinear neural networks with complex dynamics
T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco
Book Chapter - Smart Adaptive Systems on Silicon, pp 229-251, 2004
SPRINGER    DOI: 10.1007/978-1-4020-2782-6_14    ISBN: 978-1-4757-1051-9    » doi
[abstract]
We have identified a second order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that implements the discrete space version of the selected reaction-diffusion equation [1]. The logarithmic compression of the state variables allows several decades of variation of these state variables within subthreshold operation of the MOS transistors. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. As a demonstrator, we have designed a chip containing a linear array of ten second order dynamics coupled cells. Using this hardware, we have experimentally reproduced two complex spatio-temporal phenomena: the propagation of traveling waves and of trigger waves, as well as isolated oscillatory cells. Because the cells realize a second order dynamics, are coupled to their nearest neighbors only, and allow wide range of parameters programming, they can be called 'Second Order Cellular Neural (or Nonlinear) Networks' (CNNs)

Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques
T. Serrano-Gotarredona, R. Serrano-Gotarredona and B. Linares-Barranco
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2004
[abstract]
This paper describes a hardware implementation of a 2nd order reaction-diffusion system. This hardware is able to emulate complex spatio-temporal behaviors that appear in nature, such as, travelling waves, trigger waves, spiral waves and Turing Patterns. The hardware has been designed using log-domain techniques with MOS transistors operating in the subthreshold regime. In our implementation, the parameters of the reaction-diffusion equation are currents that can be adjusted several decades in order to reproduce different spatio-temporal behaviors. As a demonstrator, a linear array of 10 cells has been integrated in the AMS 0.35mum CMOS technology. We have experimentally reproduced three complex spatio-temporal phenomena: trigger and travelling wave propagation and the emulation of an oscillatory medium.

On leakage current temperature characterization using sub-pico-ampere circuit techniques
B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona and L.A. Camuñas
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2004
[abstract]
Recently, a reliable circuit design technique for current mode signal processing down to femto-amperes was reported [1]. The technique involves logarithmic current splitters for obtaining on-chip sub-pA currents and a special saw-tooth oscillator for current monitoring, while using "source voltage shifting". This way, sub-pA currents can be characterized without driving them off-chip which would require expensive instrumentation with complicated low leakage setups. In this paper we report on characterization of temperature dependence of leakage currents, exploiting these techniques. Currents as low as 0.3fA have been characterized.

On mismatch properties of MOS and resistors calibrated ladder structures
B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona and G. Vicente Sánchez
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2004
[abstract]
The mismatch behavior of MOS and resistor based calibrated ladder structures, used in arrays of DACs, is studied theoretically and experimentally. It is found that the calibrated DAC worst case output current standard deviation is approximately 1/3 that of its individual components. MOS experimental measurements illustrate the discussed mismatch behavior. Directions on how to design ladder DACs for a target precision are provided.

A precise CMOS mismatch model for analog design from weak to strong inversion
T. Serrano-Gotarredona, B. Linares-Barranco and J. Velarde-Ramírez
Conference - ieee International Symposium on Circuits and Systems ISCAS 2004
DOI:     » doi
[abstract]
A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able to predict current mismatch with a mean relative error of 13.5% in the weak inversion region and 5% in strong inversion. This is verified for 12 different curves, sweeping V-G, V-DS and V-S. Since data is available for 30 different sizes, the mismatch model can be expressed as function of transistor width W and L, independently. The proposed model, with explicit W and L dependency has been implemented in the Spectre simulator. Simulations reveal that such precise modeling of mismatch (with explicit W and L dependency) can improve analog circuit performance without penalty on power and area consumption: just by splitting transistors into the optimum number of segments.

A precise 90 degrees quadrature OTA-C VCO between 50-130 MHz
B. Linares-Barranco, T. Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáceres, J.M. Mora and A. Linares-Barranco
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
We present a VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8mum CMOS process. The oscillator is tunable in the frequency range from 50-130 MHz. A symmetric topology assures that the two phases produced by the oscillator present an extremely low phase difference error (less than 2degrees over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.

A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems
B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona and J. Costas-Santos
Conference - International Symposium on Circuits and Systems ISCAS 2004
[abstract]
We present the design and experimental measurements of an integrate-and-fire pixel for Address-Event-Representation (AER) transceiver chips such that (a) input events can be weighted according to a digital word, (b) this weight includes a sign bit, (c) the incoming event is acompanied by a sign bit, and (d) the pixel can be calibrated to compensate for mismatch in large arrays of these pixels. A prototype has been fabricated in the AMS 0.35mum CMOS process, whose experimental measurement results are provided.

A precise 90 degrees quadrature OTA-C oscillator tunable in the 50-130-MHz range
B. Linares-Barranco, T. Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáceres, J.M. Mora and A. Linares-Barranco
Journal Paper - IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 4, pp 649-663, 2004
IEEE    DOI: 10.1109/TCSI.2004.823673    ISSN: 1057-7122    » doi
[abstract]
We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-mum CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided.

Current mode techniques for sub-pico-ampere circuit design
B. Linares-Barranco, T. Serrano-Gotarredona, R. Serrano-Gotarredona and C. Serrano-Gotarredona
Journal Paper - Analog Integrated Circuits and Signal Processing, vol. 38, no. 2-3, pp 103-119, 2004
KLUWER ACADEMIC    DOI: 10.1023/B:ALOG.0000011162.52504.39    ISSN: 0925-1030    » doi
[abstract]
In this paper we explore the low current limit that standard CMOS technologies offer for current mode based VLSI designs. We show and validate a reliable circuit design technique for current mode signal processing down to fempto-amperes. We will take advantage of specific-current extractors and logarithmic current splitters to obtain on-chip sub-pA currents. Then we will use a special on-chip saw-tooth oscillator to monitor and measure currents down to a few fempto-amps. This way, sub-pA currents are characterized without driving them off-chip, nor requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is implemented that uses a 100 fF capacitor and a 3.5 fA bias current to achieve a cut-off frequency of 0.5 Hz and using an area of 12 x 24.35 mum(2) in a standard 0.35 mum CMOS process. A technique for characterizing noise at these currents is described and verified. Also, temperature dependence of leakage currents is measured as well.

CMOS transistor mismatch model valid from weak to strong inversion
T. Serrano-Gotarredona and B. Linares Barranco
Conference - European Solid-State Circuits Conference ESSCIRC 2003
[abstract]
A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS and PMOS transistors for 30 different geometries has been done with this continuos model. The model is able to predict current mismatch with a mean relative error of 13.5% in the weak inversion region and 5% in strong inversion. This is verified for 12 different curves, sweeping V-G, V-DS and V-S.

Compact low-power calibration mini-DACs for neural arrays with programmable weights
B. Linares-Barranco, T. Serrano-Gotarredona and R. Serrano-Gotarredona
Journal Paper - IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1207-1216, 2003
IEEE    DOI: 10.1109/TNN.2003.816370    ISSN: 1045-9227    » doi
[abstract]
This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1,bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8% or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons.

Log-domain implementation of complex dynamics reaction-diffusion neural networks
T. Serrano-Gotarredona and B. Linares Barranco
Journal Paper - IEEE Transactions on Neural Networks, vol. 14, no. 5, pp 1337-1355, 2003
IEEE    DOI: 10.1109/TNN.2003.816374    ISSN: 1045-9227    » doi
[abstract]
In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that implements the spatially discretized version of the selected reaction-diffusion equation. The logarithmic compression of the state variables allows several decades of variation of these state variables within subthreshold operation of the MOS transistors. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. As a demonstrator, we have designed a chip containing a linear array of ten second-order dynamics coupled cells. Using this hardware, We have experimentally reproduced two complex spatio-temporal phenomena: the propagation of travelling waves and of trigger waves, as well as isolated oscillatory cells.

On the design and characterization of femtoampere current-mode circuits
B. Linares-Barranco and T. Serrano-Gotarredona
Journal Paper - IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp 1353-1363, 2003
IEEE    DOI: 10.1109/JSSC.2003.814415    ISSN: 0018-9200    » doi
[abstract]
In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-mum three-metal two-poly standard CMOS process.

Precise 90 degrees quadrature current-controlled oscillator tunable between 50-130 MHz
B. Linares-Barranco, T. Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáceres, J.M. Mora and A. Linares-Barranco
Journal Paper - Electronics Letters, vol. 39, no. 11, pp 823-825, 2003
IEEE    DOI: 10.1049/el:20030558    ISSN: 0013-5194    » doi
[abstract]
A VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8 mum CMOS process is presented. The oscillator is tunable in the frequency range from 50-130 MHz. The two phases produced by the oscillator show an extremely low phase difference error (less than 2degrees over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.

Current-mode fully-programmable piece-wise-linear block for neuro-fuzzy applications
T. Serrano-Gotarredona and B. Linares-Barranco
Journal Paper - Electronics Letters, vol. 38, no. 20, pp 1165-1166, 2002
IEEE    DOI: 10.1049/el:20020831    ISSN: 0013-5194    » doi
[abstract]
A new method to implement an arbitrary piece-wise-linear characteristic in current mode is presented. Each of the breaking points and each slope is separately controllable. As an example a block that implements an N-shaped piece-wise-linearity has been designed. The N-shaped block operates in the subthreshold region and uses only ten transistors. These characteristics make it especially suitable for large arrays of neuro-fuzzy systems where the number of transistors and power consumption per cell is an important concern. A prototype of this block has been fabricated in a 0.35μm CMOS technology. The functionality and programmability of this circuit has been verified through experimental results.

A loss control feedback loop for VCO stable amplitude tuning of RF integrated filters
B. Linares-Barranco and T. Serrano-Gotarredona
Conference - IEEE International Symposium on Circuits and Systems ISCAS 2002
[abstract]
Recently Li and Tsividis introduced a novel Loss Control Feedback Loop for VCO Indirect Tuning of RF Integrated Filters, because conventional loss-control loops were not able to render stable amplitude control for high frequency applications. In this paper we show a slight modification to the classical control loop, rendering stable control. Results are validated through device level simulations.

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