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Author: Valencia Barrero, Manuel
Year: Since 2002
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Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández, M. Valencia-Barrero, C. Baena and P. Parra
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2018
[abstract]
The fault injection in ciphers operation is a very successful mechanism to attack them. The inclusion of elements of protection against this kind of attacks is more and more necessary. These mechanisms are usually based on introducing redundancy, which leads to a greater consumption of resources or a longer processing time. This article presents how the introduction of placement restrictions on ciphers can make it difficult to inject faults by altering the clock signal. It is therefore a countermeasure that neither increases the consumption of resources nor the processing time. This mechanism has been tested on FPGA implementations of the Trivium cipher. Several tests have been performed on a Spartan 3E device from Xilinx and the experimental measurements have been carried out with ChipScope Pro. The tests showed that an adequate floorplanning is a good countermeasure against these kind of attacks.

FPGA design example for maximum operating frequency measurements
C.J. Jiménez-Fernandez, P. Parra-Fernandez, C. Baena-Oliva, M.Valencia-Barrero and F.E. Potestad-Ordoñez
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
[abstract]
The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it is presented with a low complexity, it is not possible to do it in a single practice session. This paper presents, as a demonstrator, the design at RT level and its implementation in FPGA of a digital system that uses the Trivium flow cipher and on which measurements of maximum operating frequency are made. This circuit is designed in three laboratory sessions of about two hours each.

Distance measurement as a practical example of FPGA design
C.J. Jiménez-Fernandez, P. Parra-Fernandez, C. Baena-Oliva, M.Valencia-Barrero and F.E. Potestad-Ordoñez
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2018
[abstract]
Digital design learning at the RT level requires practical examples and as learning progresses, the examples need to become more complex. FPGAs and development boards offer a very suitable platform for the implementation of these designs. However, classroom practice sessions usually last two hours, which does not allow the complexity of the designs be high enough. For this reason, interesting designs that can be made in several sessions are required In this paper, the construction of a distance measuring system is presented as a demonstrator. For this purpose, a distance measurement module based on ultrasound is available and the results are displayed in 7-segment displays on a Nexys4 board.

Vulnerability Analysis of Trivium FPGA Implementations
F.E. Potestad-Ordonez, C.J. Jimenez-Fernandez and M. Valencia-Barrero
Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp 3380-3389, 2017
IEEE    DOI: 10.1109/TVLSI.2017.2751151    ISSN: 1063-8210    » doi
[abstract]
Today, the large amount of information ex-changed among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applications, cryptographic algorithms affording lightweight implementations have been proposed. They constitute the so-called lightweight cryptography. A prominent example is the Trivium stream cipher, one of the finalists of the eSTREAM project. Although cryptographic algorithms are certainly simpler, one of their most critical vulnerability sources in terms of hardware implementations is side channel attacks. In this paper, it is studied the vulnerability of field-programmable gate array (FPGA) implementations of Trivium stream ciphers against fault attacks. The design and implementation of a system that alters the clock signal and checks the outcome is also described. A comparison between real and simulated fault injections is carried out in order to examine their veracity. The vulnerability of different versions of the Trivium cipher and their routing dependences has been tested in two different FPGA families. The results show that all versions of the Trivium cipher are vulnerable to fault attacks, although some versions are more vulnerable than others.

Multiradix Trivium Implementations for Low-Power IoT Hardware
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp 3401-3405, 2017
IEEE    DOI: 10.1109/TVLSI.2017.2736063    ISSN: 1063-8210    » doi
[abstract]
The integration of lightweight symmetric encryption is becoming increasingly widespread in very low-power Internet of Things applications, with the rapid emergence of very low energy block and stream ciphers in portable and wireless systems. Trivium is one of the lightweight stream ciphers shortlisted for the hardware profile of the eSTREAM project. This paper describes low-power multiradix Trivium implementations based on the use of parallelization techniques to reduce dynamic power consumption. The low-power Trivium designs were implemented and characterized in TSMC 90 nm to compare area resources and power reduction. The implementation results show that our proposed designs offer dynamic power savings of 31%-45% with radix-1 and radix-2 when compared with the standard Trivium, and 15% with radix-8. There is no improvement, however, with radix-16.

Trivium hardware implementations for power reduction
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Journal Paper - International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp 188-198, 2017
JOHN WILEY & SONS    DOI: 10.1002/cta.2281    ISSN: 0098-9886    » doi
[abstract]
This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.

Creación de carteles autoexplicativos para laboratorios de electrónica
C.J. Jiménez, C. Baena and M. Valencia
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
[abstract]
Se presenta un proyecto cuyo objetivo ha sido la creación de carteles que, a modo de tutoriales resumidos, muestran de forma muy visual las tareas básicas a realizar en los laboratorios de electrónica. Están dirigidos a alumnos de asignaturas y titulaciones diversas. Se ha elegido la técnica de carteles por ser un medio muy amigable de refrescar informaciones, permitir contenidos altamente autoexplicativos y tener un coste razonablemente bajo. Se han creado ocho carteles que recogen desde el manejo del instrumental hasta la solución de errores comunes, pasando por la verificación y por la realización adecuada de montajes y medidas.

Aplicaciones docentes del diseño de un picoprocesador
C.J. Jiménez, C. Baena, P. Parra and M. Valencia
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2016
[abstract]
El conocimiento de la estructura interna y del mecanismo de funcionamiento de microprocesadores es una parte muy importante en la formación de ingenieros en electrónica e informática. Este conocimiento puede profundizarse con experiencias de diseño de procesadores, que reúnen además muchos aspectos vinculados a otros conocimientos básicos. Sin embargo, debido a su complejidad, el diseño de procesadores comerciales no es efectivo desde un punto de vista docente. En la presente comunicación presentamos una experiencia de diseño en VHDL de un procesador muy sencillo que demuestra los múltiples aprendizajes que suponen para el alumno.

Fault Injection on FPGA implementations of Trivium Stream Cipher using Clock Attacks
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference - Workshop on Trustworthy Manufacturing and Utilization of Secure Devices TRUDEVICE 2016
[abstract]
Nowadays the security of cryptographic circuits is threatened not only by attacks on the algorithm, but also by attacks on the circuit implementation. They are the so-called side channel attacks and within such attacks are the Active Fault Analysis attacks. In literature, there are reported some vulnerability analysis of the Trivium stream cipher against Active Fault Analysis attacks using Differential Fault Analysis (DFA) [1][2]. The DFA technique is a side channel attack in which an attacker is able to inject a fault into the encryption or decryption process, thus retrieving the secret information. For the Trivium cypher, a fault is injected into the inner state. These works shown that if an attacker is able to inject only one fault in the inner state of the Trivium, the key could be retrieved, but none of them checks its feasibility on a specific hardware implementation. In this paper, it is presented an experimental analysis about the behaviour of FPGA implementations of Trivium ciphers against fault injection through the variation of the clock signal. In addition, it is made a comparative analysis between the experimental results obtained after the attack, and the expected results obtained by the simulation and timing analysis, that is, the fault positions of the Trivium inner state obtained experimentally and the fault positions expected by the timing analysis. This analysis was presented in [3] and results show the vulnerabilities of these implementations and the impossibility of determining the fault injections through simulation.

Experimental and Timing Analysis Comparison of FPGA Trivium Implementations Against Clock Fault Injection
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2016
[abstract]
The security of cryptocircuits is today threatened not only by attacks on algorithms but also, and above all, by attacks on the circuit implementations themselves. These are known as side channel attacks. One variety is the Active Fault Analysis attack, that can make a circuit vulnerable by changing its behavior in a certain way. This article presents an experimental fault insertion attack on an FPGA implementation of the Trivium stream cipher. It also compares the faults introduced with the faults expected after a timing analysis. The results show that this implementation is vulnerable to such attacks, and also that it is not possible to estimate the position of the inserted faults by means of timing analysis.

Fault Attack on FPGA Implementations of Trivium Stream Cipher
F.E. Potestad-Ordóñez, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference - IEEE International Symposium on Circuits and Systems, ISCAS 2016
[abstract]
This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented.

Low power implementation of Trivium stream cipher
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández, E. Potestad and M. Valencia-Barrero
Conference - Workshop on Cryptographic Hardware and Embedded Systems CHES 2015
[abstract]
Trivium is a synchronous stream cipher designed to generate up to 264 bits of key stream from an 80-bit secret key and an 80-bit initialization vector (IV). The architecture of this cipher is based on a 288-bit cyclic shift register accompanied by an array of combinational logic (AND, OR and XOR) to provide its feedback. The key stream generation consists mainly on an iterative process which updates some bits in the state register with logic operations to generate one bit of key stream.

A message transmission system with lightweight encryption as a project in a Master subject
C.J. Jiménez, C. Baena, M. Valencia, J.M. Fernández and A. Moreno
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2014
[abstract]
Master subjects should ideally be very practical, to allow students to apply the knowledge they have acquired to the solving of specific problems. This paper proposes the design of a secure communications system using an SPI bus as a Master subject. The system designed uses a stream cipher to encrypt and decrypt data and allows transmission of random length messages. It also uses CRCs to check message integrity.

Low power implementation of Trivium stream cipher
J.M. Mora-Gutiérrez, C.J. Jiménez-Fernández and Valencia-Barrero
Conference - Int. Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS 2012
[abstract]
This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. The design was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implementations. The results show that the application of the technique reduces power consumption by more than 20% with only a slight penalty in area and operating frequency.

Diseño e implementación de multiplicadores de Montgomery en FPGAs
G. Sassaw-Teshome, C.J. Jiménez-Fernández and M. Valencia-Barrero
Conference - Taller sobre Hardware Reconfigurable THR 2012
[abstract]
La multiplicación modular es la operación clave en sistemas de cifrado basados en clave pública, como RSA y curvas elípticas (ECC). Las implementaciones hardware de altas presentaciones de criptoprocesadores RSA y EEC utilizan el algoritmo de Montgomery para llevar a cabo la multiplicación modular, ya que con este algoritmo se realiza la multiplicación modular sin tener que realizar la operación de división. El objetivo principal de este artículo es explorar las prestaciones de varias estructuras que utilizan versiones modificadas del algoritmo de Montgomery para implementaciones de alta velocidad. Presentamos multiplicadores con el algoritmo de Montgomery con sumadores con ahorro de acarreo (CSA) y con diferentes bases, incluyendo esquemas con recodificación de Booth. Las implementaciones llevadas a cabo en este trabajo simplifican la generación de los productos parciales evitando almacenar en memoria los valores del producto parcial que no se consiguen con desplazamiento de registros. Los resultados muestran que las estructuras de alta base son mejores para aplicaciones de alta velocidad.

Evaluación multiagente en la formación de profesores noveles
J. Benjumea, A. Estrada, E. Ostúa, O. Rivera, J. Ropero, F. Sivianes and M. Valencia
Book Chapter - Programa de equipos docentes para la formación de profesores noveles, pp 263-275, 2011
FÉNIX EDITORA    ISBN: 978-84-86849-73-3    
[abstract]
Seis profesores noveles y un mentor de Tecnología Electrónica presentan los resultados de su participación dentro de un programa de formación de noveles. En las actividades de observación, que han sido de cuatro tipos, se han utilizado diferentes instrumentos de evaluación (cuantitativos/cualitativos, cerrados/abiertos) y diversos agentes observadores (el propio novel, alumnos suyos, mentor y especialistas pedagógicos). Se presentan los principales resultados que han obtenido los noveles en estas evaluaciones, resultados que muestran una gran coherencia en el análisis de los distintos agentes. Se extraen asimismo los aspectos mejorables del programa y se destaca su principal beneficio: la mejora docente de los participantes.

Experiencias del equipo docente de iniciación en el departamento de tecnología electrónica
G. Miró-Amarante, J. Viejo and M. Valencia
Book Chapter - Programa de equipos docentes para la formación de profesores noveles, pp 395-404, 2011
FÉNIX EDITORA    ISBN: 978-84-86849-73-3    
[abstract]
Durante el curso 2007/2008 se ha llevado a cabo una nueva experiencia con profesores noveles en el departamento de Tecnología Electrónica. Estos profesores han seguido el Programa de Equipos Docentes para la Formación de Profesores Noveles de la Universidad de Sevilla, cuyo principal objetivo es el apoyo y asesoramiento didáctico y pedagógico de los profesores en el desempeño de sus funciones docentes. En esta publicación se trata el proceso de constitución de dicho equipo, las actividades presenciales y no presenciales desarrolladas a lo largo del curso académico y los resultados obtenidos. También se detallan los principales aspectos positivos y negativos del citado Programa de Formación.

Montaje de un amplificador de audio en las prácticas de electrónica analógica
C.J. Jiménez, A. López, C. León and M. Valencia
Conference - Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica TAEE 2012
[abstract]
En esta comunicación se presenta el rediseño de las prácticas de laboratorio de la asignatura Electrónica Analógica con el objetivo de que el alumno monte un sistema de mediana complejidad. Estas prácticas son obligatorias y se realizan en sesiones de dos horas, por lo que el sistema ha de cumplir con las características de que sea modular y cubra gran parte de los contenidos de la asignatura. La asignatura Electrónica Analógica se imparte en el segundo curso de la titulación de Ingeniería Técnica Industrial, especialidad de Electrónica Industrial.

Metodologia orientada a la elección de FPGAs con prioridad en el consumo de potencia
J.M. Mora-Gutierrez, G. Sassaw-Teshome, C.J. Jiménez-Fernández and M.Valencia-Barrero
Conference - Iberchip XVI Workshop IWS 2010
[abstract]
En este trabajo se presenta una metodología de diseño orientada a explorar el cada vez más amplio conjunto de FPGAs con el fin de seleccionar la mejor opción. Los parámetros que se utilizan para realizar la exploración son los recursos consumidos, la frecuencia de operación y el consumo de potencia. Sobre este último parámetro, el más difícil de medir, se hace un especial énfasis. Se exploran dos fabricantes (Altera y Xilinx), dos familias diferentes de cada fabricante y dos subfamilias dentro de cada familia, una de la gama alta y otra de la gama baja. Esta exploración se ha realizado implementando dos circuitos que realizan la operación división de números de 64 bits usando dos algoritmos con plena vigencia.

Influencia de la caracterización en el flujo de diseño de circuitos CMOS nanometricos
G. Sassaw, C.J. Jiménez and M. Valencia
Conference - Iberchip XVI Workshop IWS 2010
[abstract]
Abstract not avaliable

High radix implementation of montgomery multipliers with CSA
G. Sassaw, C.J. Jiménez and M. Valencia
Conference - International Conference on Microelectronics ICM 2010
[abstract]
Modular multiplication is the key operation in systems based on public key encryption, both for RSA and elliptic curve (ECC) systems. High performance hardware implementations of RSA and ECC systems use the Montgomery algorithm for modular multiplication, since it allows results to be obtained without performing the division operation. The aim of this article is to explore various modified structures of the Montgomery algorithm for high speed implementation. We present the implementation of a modified Montgomery algorithm with CSA and with different radix. In order to optimize the implementation regarding operation speed, we considered carry save adders structures and the Booth recoding scheme. The structure used in this paper simplifies the computation of the partial products avoiding the use of memories to store pre-calculated data for partial products which cannot be achieved by the shifting operation. The result shows that high-radix implementations are better for high speed applications.

HEAPAN: Diseño y evaluación de arquitecturas ILP
D. Peñalosa, C.J. Jiménez and M. Valencia
Conference - II Simposio Internacional de Computación y Electrónica 2009
[abstract]
En la actualidad, los procesadores ASIP (Application- Specific Instrucction set Processors) se utilizan en el diseño de sistemas orientados a una aplicación específica, debido a su flexibilidad y eficiencia. Una forma de hacer estos computadores es mediante el uso de herramientas ADL's (Architectures Design Languages). En este artículo presentaremos una herramienta ADL llamada HEAPAN, la cual está especializada en la resolución de conflictos que se dan en las arquitecturas ILP (Instruction Level Processors). Para ello, esta herramienta utiliza técnicas hardware y planificaciones dinámicas a la hora de ejecutar las instrucciones. HEAPAN puede simular, sintetizar y evaluar arquitecturas de forma fácil y flexible. Con el fin de mostrar las capacidades de esta herramienta, hemos diseñado, simulado y evaluado dos arquitecturas ILP.

Aplicación de técnicas de evaluación continua en grupos numerosos de alumnos
M.C. Baena-Oliva, M.J. Bellido-Díaz, A. Estrada-Pérez, J. Juan-Chico, S. Martín-Guillén, A.J. Molina-Cantero, E. Ostua-Aranguena, M.P. Parra-Fernández, O. Rivera-Romero, M.C. Romero-Ternero, J. Ropero-Rodríguez, P. Ruiz de Clavijo-Vázquez, G. Sánchez-Antón, M. Valencia-Barrero and J.M. Gómez-González
Book Chapter - Experiencia de Innovacion Universitaria (I) Curso 2006-2007, vol. 1, pp 350-365, 2009
ICE UNIVERSIDAD DE SEVILLA    ISBN: 978-84-86849-70-2    
[abstract]
Abstract not available

Logic synthesis
A. Barriga-Barros, C.J. Jiménez-Fernández and M. Valencia-Barrero
Book Chapter - Encyclopedia of Computer Science and Engineering, pp 1753-1762, 2009
JOHN WILEY & SONS    DOI: 10.1002/9780470050118.ecse227    ISBN: 978-0-471-38393-2    » doi
[abstract]
This article addresses logic synthesis, which involves the generation of a circuit at the logic level based on an RT level design specification. The article deals with aspects associated with logic design such as data types, system components, and modes of operation. The hardware description languages will be presented as tools to specify digital systems. Two standard languages (VHDL and Verilog) will be examined in detail, and the use of VHDL for automatic synthesis will be explained to illustrate specific aspects of logic synthesis descriptions. The article ends with an illustrative example of the principal concepts discussed.

A switching noise vision of the optimization techniques for low-power synthesis
J. Castro, P. Parra, M. Valencia and A.J. Acosta
Conference - European Conference on Circuit Theory and Design ECCTD 2007
[abstract]
Different techniques used by a CAD tool that automatically optimize power consumption at gate-level circuit have been investigated in terms of switching noise generation. Such techniques, clock-gating, sleep-mode and others at a gate-level are usual saving power techniques, but are rarely applied to switching noise reduction. The reduction of peaks in supply current is of great interest due to their impact in sensitive parts of a circuit. An estimation of these peaks has been done at a gate level by two different tools (PrimePower and NanoSim, both from Synopsys) providing both the power supply current waveform along time, the average and the peak power for different synthesized circuits to check the effectiveness of such low-power techniques for switching noise reduction. As conclusions, although both tools provide an estimation of peak power, only NanoSim gives accurate values, and how these optimization techniques for low-power are, in general, useful for switching noise reduction.

Asymmetric clock driver for improved power and noise performances
J. Castro, P. Parra, M. Valencia and A.J. Acosta
Conference - International Symposium on Circuits and Systems ISCAS 2007
[abstract]
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.

Partitioning and characterization of high speed adder structures in deep-submicron technologies
A. Estrada, G. Sassaw, C.J. Jiménez and M. Valencia
Conference - Conference on VLSI Circuits and Systems III, 2007
[abstract]
The availability of higher performance (in area, time and power consumption) and greater precision binary adders is a constant requirement in digital systems. Consequently, the design and characterization of adders and, most of all, their adaptation to the requisites of present-day deep-submicron technologies, are today still issues of concern. The binary adder structures in deep-submicron technologies must be revised to achieve the best balance between the number of bits in the adder and its delay, area and power consumption. It is therefore very important to make an effort to carefully optimize adder structures, thus obtaining improvements in digital systems. This communication presents the optimization of adder structures for implementations in deep-submicron technologies through their partitioning into blocks. This partitioning consists of dividing the number of input bits to the adder into several subsets of bits that will constitute the inputs to several adder structures of the same. or of different types. The structures used to accomplish this study range from the more traditional types, such as the carry look ahead adder, the ripple carry adder or the carry select adder, to more innovative kinds, like the parallel prefix adders of the type proposed by Brent-Kung, Han-Carlson, Kogge-Stone or Ladner-Fischer. The analyses carried out allow the characterization of structures implemented in deep-submicron technologies for area, delay and power consumption parameters.

Selective Clock-Gating for Low-Power Synchronous Counters
P. Parra, A.J. Acosta, R. Jiménez and M. Valencia
Journal Paper - Journal of Low Power Electronics, vol. 1, no. 1, pp 11-19, 2005
AMERICAN SCIENTIFIC PUBLISHERS    DOI: 10.1166/jolpe.2005.003    ISSN: 1546-1998    » doi
[abstract]
With current technologies and applications, dynamic power reduction is of great technological interest. The objective of this paper is to explore the applicability of clock gating techniques to counters in order to reduce the power consumption as well as to compare different power figures in counting structures. Counters are widely used in current VLSI digital circuits, and optimized low-power versions of them are of important concern. Different ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits with different synchronization schemes. The correct selection of bits where clock gating is applied and the suitable composition of groups of bits are essential but are not straightforward when applying this technique. We have found that some specific groupings of bits are the best options when applying clock gating to reduce power consumption.

Logic-Timing Simulation and the Degradation Delay Model
M.J. Bellido-Díaz, J. Juan-Chico, M. Valencia-Barrero
Book - 268 p, 2005
IMPERIAL COLLEGE PRESS    ISBN: 1-86094-589-9    » link
[abstract]
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the Degradation Delay Model , developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.

Formación de profesores noveles en tecnología electrónica: una primera aproximación
J. Barbancho-Concejero, D. Guerrero-Martos, C.J. Jiménez-Fernández and M. Valencia-Barrero
Book Chapter - La Formación del Profesorado Universitario: Programa de Equipos Docentes de la Universidad de Sevilla Curso 2003-2004, pp 75-84, 2005
ICE UNIVERSIDAD DE SEVILLA    ISBN: 84-86849-37-3    
[abstract]
Abstract not available

A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
A. Estrada, C.J. Jiménez and M. Valencia
Conference - Conference on VLSI Circuits and Systems II, 2005
[abstract]
Integration technologies have favored the design and implementation of more complex circuits. Thanks to this increased complexity, these circuits are capable of implementing algorithms which a few years ago were too expensive in both area and computational resources. However, they now offer interesting choices which should be considered. This new generation of integrated circuits nevertheless presents other kinds of restrictions that the designer should bear in mind. Parameters such as frequency of operation or power consumption are new restrictions that the designer has to deal with in order to fulfill the conditions established by the circuit functionality. Finally, the shrinking integration scale of current technologies makes the timing behavior of the design differ from previous technologies. Thus, a review of the timing behavior of the digital circuit should be done. So far, arithmetic circuits have been used as a benchmark for the analysis and design procedures of digital circuits. Therefore, it is our goal now to analyze both conventional and modem arithmetic circuits structures for different deep-submicron technologies. To achieve this goal, a good solution is to characterize a set of algorithmic circuits for several deep submicron processes, so that the designer can select the most suitable one depending upon the intended application and existing restrictions. In this paper, the first steps to attain such selection are presented. In particular, we propose a design and VHDL characterization methodology based on an RTL description of each component, on the utilization of an automated synthesis tool, and on the generation of logic characteristics from the logic level. This methodology is applied to a set of adders structures, the results of which are also presented.

Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
P. Parra, J. Castro, M. Valencia and A.J. Acosta
Conference - VLSI Circuits and Systems II, 2005
[abstract]
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.

Switching noise reduction in clock distribution in mixed-mode VLSI circuits
P. Parra, A.J. Acosta and M. Valencia
Conference - Conference on VLSI Circuits and Systems 2003
[abstract]
One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry and the clock generation and distribution logic. It is well known for the mixed-signal community that harmonics of clock signal are easily injected in the analog part. This paper analyzes how some actuations like the insertion of buffers, the suited, placement and routing of the clock tree cells, as well as the suited sizing of devices can save switching noise. In fact, different solutions for the clocking logic generate very different results for switching noise.

Design of Synchronous Counters for Low Noise Low Power Applications Using Clock Gating Techniques
P. Parra-Fernández, A.J. Acosta-Jimenez and M. Valencia-Barrero
Conference - Conference on Design of Circuits and Integrated Systems DCIS 2002
[abstract]
Abstract not avaliable

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